JPS6273776A - Manufacture of junction type field effect transistor - Google Patents

Abstract

PURPOSE:To eliminate a fine division matching by forming holes in the first and second dielectric films, diffusing an impurity through the holes to a semiconductor surface, and forming a gate electrode only in the hole by utilizing the overhangs of the second dielectric film formed by undercutting. CONSTITUTION:An N-type In0.53Gaq0.74As layer 12 is epitaxially grown on a substrate 11, the second dielectric film 14 is sequentially bonded, a hole for diffusing a P-type impurity is formed by RIE, and diffusion is executed. Then, the first dielectric film 13 in the hole is undercut by approx. 1mum by etching to form overhangs of the film 14, a metal film of AuZn is bonded in self-aligning manner to a P-type region 15, and heat treated to form a gate electrode 16. The films 13, 14 are eventually removed with aqueous HF solution, the metal film of AuGeNi is patterned, and then heat treated to form a source electrode 17 and a drain electrode 18.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a high-speed junction field effect transistor used in a frequency band of several 100 Mb/s-Gb/sO.

[Conventional technology]

Figure 2 shows a conventional method for manufacturing a junction field effect transistor (hereinafter abbreviated as J-FET) (Technical Digest I.O.
Technical Dig
est Iαhi'83 (Tokyo), 28B4-3.
186 (1983)), Ino, 53Q1o,...
uAs 1,1 channel layer binding material, n-type Ino, 5aGao,
47As layer 22 is formed (after the dielectric film 23 is completely formed and this is used as a diffusion mask, a P-type layer 24 is formed (
Φ)). Next, a gate electrode 25e is formed on the P type region 24, and a source electrode 26 and a drain electrode 27 are further provided ((C)).

[Problem that the invention seeks to solve]

J. Providing metal wiring on the gate stripe of the FET is important in suppressing an increase in thermal noise.

Here, k is Boltzmann's constant, TlI'i absolute temperature, Δf
is the frequency band, Ci is the input capacitance, and gm is the mutual conductance. α is the noise constant. α: α6 + gm s Rg...
・・・・・・・・・◆+−・(2) (2) In the formula, αO is a constant and takes a value of 0.7 to 1.

Rg is the series resistance of the gate stripe. In equation 0), W and L are the gate width and gate length, respectively, and ρ$ is the sheet resistance of the gate. If it is formed on the gate by diffusion only and is assumed to be 9, then ρS~2 becomes Ω/
It becomes sg. If W-300μ劃L=1μ, then *R
If g = 86 KO and gm = 10 ms, ■
The value of the second term on the right side of the equation is 860, so the value of α is α0
The thermal noise of pJ-FETO, which is thicker than that of , increases significantly. Therefore, providing metal wiring on the gate is an important point in reducing noise.

However, in high-speed FETs, the gate length is generally several micrometers and the width is narrow, so it is extremely difficult to route the gate wiring in the impurity diffusion region using the procedure shown in Figure 2, as strict alignment is required. .

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a J-FET that eliminates the above drawbacks and allows all electrodes to be formed in self-alignment with the gate.

[The tth way to solve the problem]

In order to solve all of the above-mentioned problems, the J-FET manufacturing method of the present invention includes a first dielectric film on the semiconductor surface, a chemical etching rate lower than that of the first dielectric film, and an equivalent re-etching process. Active ion etching (hereinafter abbreviated as IE) speed? A step of sequentially depositing a second dielectric film having a second dielectric film formed on the second dielectric film, and selectively removing only the second and tenth conductor films by RIE using a photoresist as a mask. a step of forming an opening with a photoresist t
- Diffusion of impurities into the semiconductor surface through the opening after removal, and chemical etching to remove the impurities in the opening.
A step of forming an undercut metal layer on the dielectric film, a step of forming a gate electrode only in the opening in a self-aligned manner by fully utilizing the second dielectric film produced by the undercut, and a step of forming a gate electrode only in the opening, and containing gold. shall be.

[Effect]

Although there is no big difference in RIE speed, RIE is applied to a two-layer film obtained by sequentially laminating a first dielectric film with a high chemical etching rate and a second dielectric film with a low chemical etching rate.
After creating an opening using IE, impurity diffusion is performed to form a gate region, and then, by taking advantage of the difference in chemical etching speed, the second dielectric film is covered, and then a metal film for the gate electrode is attached. Therefore, since the gate electrode can be formed in a self-aligned manner in the impurity diffusion region, there is no need for fine alignment compared to the conventional method, and the overall manufacturing yield can be greatly improved.

〔Example〕

FIG. 1 shows an embodiment of the present invention, and shows a method of manufacturing a JFET in which a channel is formed of an Ino, 5sGao, or 47As layer with high mobility. First, as shown in FIG.
A Ga 0.47AS layer 12 is epitaxially grown. At this time, the layer thickness is 2 JIm, and the carrier concentration is n ~ 5 × 10
It should be about yR. Next, as shown in figure (b), n-type I
no, s3Q ao, 47AS layer 120 surface has a thickness of 0.
After sequentially depositing a second dielectric film of about 2 μm of 14-metre gold, the entire photoresist is used as a mask, and an opening for pP type impurity diffusion is created using IE. After the photoresist is removed, Cd3P and source are used. Then, Cd was diffused at 580°C for about 20 minutes. At this time, the Pn junction depth is approximately 1 μm. It should be noted that the first dielectric film 13 is formed using the normal pressure thermal CVD method (
8i0,2 and PSG films formed by heating at 350°C,
The second dielectric film 14 is formed using the plasma CVD method (300
A SiN film formed by heating (heating at °C) is used.
In this case, the 5t02 and PSG films are H
While the etching rate of F' and NH4F with respect to aqueous solution (buffered hydrofluoric acid) K is about an order of magnitude higher, the RLE rate using CF4 gas is almost the same. Also, depending on the CF4 gas, the n-type Ino, 5aGao, and 47 layers 12 are hardly etched. Although an example is shown here using CD for impurity diffusion, it is also possible to use Zn.

Next, as shown in the figure (C), an undercut of about 1 μm is applied to the first dielectric film 13 in the opening for diffusion by buffered hydrofluoric acid, and the area around the second dielectric MA 14 is etched. After all the metal films are formed, a metal film made of AuZn or the like is completely deposited on the surface of the P-type region 15 in a self-aligned manner, and then heat treated to form the gate electrode 16. Finally (d)
As shown in the figure, the first dielectric film 13 and the second dielectric film 14 are removed using an HF aqueous solution (hydrofluoric acid), and then a metal film such as uGeNi is removed using a photoresist using a lift-off method. After that, a complete heat treatment is performed to form the source electrode 17 and the drain electrode 18, and the entire manufacturing process is completed.

〔Effect of the invention〕

As described above, if the present invention is used, it is possible to form a gate electrode in a self-aligned manner in the impurity diffusion region in manufacturing FETs, and there is no need for fine alignment compared to the conventional method. ,,C. It becomes possible to significantly improve the manufacturing yield.

[Brief explanation of drawings]

FIGS. 1(a)-(ψ are process diagrams showing one embodiment of the FET manufacturing method based on the present invention, and FIGS. 2(a)-(C) are process diagrams of a conventional example. 11, 21--Abortion/Humble InP substrate, 1
．． 2.22...n-type IX1 o, 5iQao,
4γAs layer, 13...first dielectric film, 14.
...Second dielectric film, 15.24...P
Mold region, 16.25...Gate electrode, 17.2
6... Source electrode, 18.27... Drain electrode, 23... Dielectric film. Agent Patent Attorney Uchihara Trap Hno-5-111 Haya 1ki Shin Z□□□

Claims (1)

[Claims] a step of sequentially depositing on a semiconductor surface a first dielectric film and a second dielectric film having a chemical etching rate lower than that of the first dielectric film and a reactive ion etching rate equivalent to that of the first dielectric film; selectively removing only the second and first dielectric films by reactive ion etching using a photoresist provided on the dielectric film as a mask to form an opening; and after removing the photoresist. a step of diffusing impurities into the semiconductor surface through the opening; a step of undercutting the first dielectric film in the opening by chemical etching; and a step of undercutting the second dielectric film caused by the undercut. forming a gate electrode only in the opening in a self-aligned manner using the edge of the opening.