JPS6273656A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6273656A JPS6273656A JP60213069A JP21306985A JPS6273656A JP S6273656 A JPS6273656 A JP S6273656A JP 60213069 A JP60213069 A JP 60213069A JP 21306985 A JP21306985 A JP 21306985A JP S6273656 A JPS6273656 A JP S6273656A
- Authority
- JP
- Japan
- Prior art keywords
- input
- semiconductor chip
- output circuit
- output circuits
- elements
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 230000002093 peripheral effect Effects 0.000 abstract 2
- 239000004020 conductor Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 241000219112 Cucumis Species 0.000 description 1
- 235000015510 Cucumis melo subsp melo Nutrition 0.000 description 1
- FJJCIZWZNKZHII-UHFFFAOYSA-N [4,6-bis(cyanoamino)-1,3,5-triazin-2-yl]cyanamide Chemical compound N#CNC1=NC(NC#N)=NC(NC#N)=N1 FJJCIZWZNKZHII-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 239000010902 straw Substances 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11898—Input and output buffer/driver structures
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体装置に関するもので、特に多数の入出力
回路をイｉｉＪ′るＣＭＯＳメしり等に使用されるもの
である。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and is particularly used in a CMOS device having a large number of input/output circuits.
〔発明の技術的′ｌ！を景とその問題点〕半導体装置で
は外部と半導体チップと接続ηるため、半導体チップ、
トの外縁部分に各信号毎の入出力回路が形成されている
が、この入出力回路はメモリ糸子等では特に多くな−）
でいる。この入出力回路は０ＭＯ３素子にあってはボン
ディングｆツイヤによってリードフレームのリード部と
接続されるボンディングパッドと、ｎヂャネル索子と、
ｐヂャネル素子とから構成される。[Technical aspect of the invention! Views and problems] In semiconductor devices, the semiconductor chip is connected to the outside, so
An input/output circuit for each signal is formed on the outer edge of the board, but this input/output circuit is not particularly common in memory threads, etc.)
I'm here. In the 0MO3 element, this input/output circuit includes a bonding pad connected to the lead part of the lead frame by a bonding wire, and an n-channel cable.
It is composed of a p-channel element.
第４図ないし第６図はこの入出力回路の従来例の平面図
を示している。第４図に図示された入出力回路４は、ボ
ンディングパッド１のノＩ′：Ｇ両側にｎチャネル素子
２およびｐヂトネル索子３が位置して構成されている。4 to 6 show plan views of conventional examples of this input/output circuit. The input/output circuit 4 shown in FIG. 4 has an n-channel element 2 and a p-channel element 3 located on both sides of the bonding pad 1.
このように両ヂャネル素子を引き離しているのは、ＣＭ
Ｏ３横Ｘｂ ｌ−形成されるｐｎｐｎのサイリスタ構造
がザージ等によりトリガされ大電流が流れることによっ
て素子破壊を招くラッチアップ現象を防ｉ二するためで
ある。What separates both channel elements in this way is the CM
This is to prevent a latch-up phenomenon that may cause device destruction due to a large current flowing when the pnpn thyristor structure formed is triggered by a surge or the like.
第５図はこの単体の入出力回路４を半導体チップ５に形
成した場合の平面図である。入出力回路４は゛Ｆ１体チ
ッ１５の外柱側に配され、−の入出力回路内のｎチ１Ｆ
ネル索子２（又はｐｆ−ｗネル索子３）が隣接する他の
入出力回路内のｎチャネル素子２（又はｐ ′：ｆ−１
ｐネル素子）と隣り合うように、１なわち同一導電型素
子が隣り合うように位置している。このような配置によ
る入出力回路はｎチャネル素子２とＤ ｆ１７ネル素子
３との間にボンディングパッド１が位ｎし、またＭ接入
出力回路どうしでは同一１１型素子が隣接しているため
入出力回路単体としても、又、全体としてらラッチアッ
プに強くなる。しかしこの配置では横方向に大きなスペ
ースを必要とするため、多数の入出力信号を受＋１持た
Ｖるためには半導体チップのサイズが大きくなる問題点
がある。又、第６図図示の入出力回路６はボンディング
パッド７の上側にｎチトネル木了８（又はｐ″′ｆ−Ｖ
ネル素子）がイ）′Ｉ置し、さらに、この上側にｐ天ｐ
ネルん子９（又はｎ ｙ−トネル素子）が位置したＩｆ
型の入出力回路である。FIG. 5 is a plan view of this single input/output circuit 4 formed on a semiconductor chip 5. The input/output circuit 4 is arranged on the outer column side of the F1 body chip 15, and
Channel element 2 (or pf-w channel element 3) is connected to n-channel element 2 (or p':f-1) in another input/output circuit adjacent to
1, that is, elements of the same conductivity type are located adjacent to each other (p-nel element). In the input/output circuit with this arrangement, the bonding pad 1 is located between the n-channel element 2 and the Df17 channel element 3, and the input/output circuits have the same 11-type elements adjacent to each other, so the input/output circuit is Both the output circuit alone and the entire output circuit are resistant to latch-up. However, since this arrangement requires a large space in the horizontal direction, there is a problem in that the size of the semiconductor chip becomes large in order to receive a large number of input/output signals. In addition, the input/output circuit 6 shown in FIG.
The channel element) is placed a)′I, and the p
If the tunnel element 9 (or ny-tunnel element) is located
It is a type input/output circuit.
゛ｉ導体チップに配りる場合には、ワイヤボンディング
を容易化するために半導体チップの外縁側にボンディン
グパッド７が位置夛−るように入出力回路を形成する。When distributing to an i-conductor chip, the input/output circuit is formed so that the bonding pads 7 are located on the outer edge side of the semiconductor chip to facilitate wire bonding.
従って、この入出力回路の横幅はボンディングパッドの
横幅程度と小さくなるため、半導体チップの一辺あたり
数多く配列げることが可能となっている。しかしながら
、この構）告で【よｎチャネル素子８おＪ：びｐブーＶ
ネル素子９がボンディングパッドの一方側に隣接しＣ配
されるため、両チャネル素子が近接してラッチアップに
弱い問題点がある。Therefore, the width of this input/output circuit is as small as the width of a bonding pad, so it is possible to arrange a large number of circuits on one side of a semiconductor chip. However, with this structure,
Since the channel element 9 is arranged adjacent to one side of the bonding pad, there is a problem in that both channel elements are close to each other and vulnerable to latch-up.
（発明の目的ン
本発明は上記事情を考慮してなされたもので、入出力回
路をラッチアップに強い構造とすると共に、多数の入出
力回路の配設を可能にした半導体装置を提供することを
目的どしている。(Object of the Invention) The present invention has been made in consideration of the above circumstances, and it is an object of the present invention to provide a semiconductor device in which the input/output circuit has a structure that is resistant to latch-up, and in which a large number of input/output circuits can be arranged. The purpose is
〔発明の概要）
上記目的を達成するため、本発明による半導体装置は、
ボンディングパッドの両側にｎチャネル素子およびｐチ
ャネル素子を配したＣＭＯ３入出力回路を形成し、この
入出力回路のうらいずれか一方の素子を半導体チップの
外縁側に、他方の素子を内方側に位置するように入出力
回路を配置するようにしたことを特徴としており、多数
の入出力回路の配設を可能にすると共にラッヂアップ耐
吊を確保している。[Summary of the Invention] In order to achieve the above object, a semiconductor device according to the present invention has the following features:
A CMO3 input/output circuit is formed with an n-channel element and a p-channel element arranged on both sides of the bonding pad, and one of the elements of this input/output circuit is placed on the outer edge side of the semiconductor chip, and the other element is placed on the inner side. It is characterized by arranging the input/output circuits so as to be located at the same position, making it possible to arrange a large number of input/output circuits and ensuring latch-up resistance.
以下、本発明にかかる半導体装置の実施例を添付図面を
参照して具体的に説明づる。Embodiments of the semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings.
第２図は本発明の一実施例の入出力回路１０の平面図、
第１図はこの入出力回路１０を半導体チップ１４に形成
した場合の平面図である。FIG. 2 is a plan view of an input/output circuit 10 according to an embodiment of the present invention;
FIG. 1 is a plan view of this input/output circuit 10 formed on a semiconductor chip 14.
入出力回路１０はボンディングパッド１１、ｎチャネル
素子１２およびｎチャネル素子１３からなり、ボンディ
ングパッド１１はボンディングワイヤによってリードフ
レームのインナーリードと接続されるようになっている
。これらの配列は、中央にボンディングパッド１１が位
置し、ボンディングパッド１１を挟むように上部にｎチ
ャネル素子１２が、下部にｎチャネル素子１３が位置し
ている。すなわら、２つの素子１２．１３とボンディン
グパッド１１は縦一列に配され、入出力回路の横幅はボ
ンディングパッド１１の幅と大差ない１００μｍ程度と
小さくなっている。又、ｎチャネル素子１２およびｐチ
１／ネル素子１３がボンディングパッド１１の両側に配
され、素子間に適切な距離が得られるためラッチアップ
に強い構造となっている。The input/output circuit 10 includes a bonding pad 11, an n-channel device 12, and an n-channel device 13, and the bonding pad 11 is connected to an inner lead of a lead frame by a bonding wire. In these arrays, a bonding pad 11 is located at the center, an n-channel element 12 is located at the upper part, and an n-channel element 13 is located at the lower part so as to sandwich the bonding pad 11. That is, the two elements 12 and 13 and the bonding pad 11 are arranged in a vertical line, and the width of the input/output circuit is as small as about 100 μm, which is not much different from the width of the bonding pad 11. Further, since the n-channel device 12 and the p-channel device 13 are arranged on both sides of the bonding pad 11, and an appropriate distance is obtained between the devices, the structure is resistant to latch-up.
このような入出力回路１０は、第１図に示すように、半
導体チップ１４の外縁側にｐ’ｆ−ｔ−ネル素子１３が
位置し、内側にｎチャネル素子１２が位置するように形
成される。、１／：ｒ：わら、索Ｔ−１２。As shown in FIG. 1, such an input/output circuit 10 is formed such that a p'f-t channel element 13 is located on the outer edge side of a semiconductor chip 14, and an n-channel element 12 is located on the inside. Ru. , 1/:r: straw, cord T-12.
１３を結ぶ線が半導体チップの辺と直交リ−るように入
出力回路を形成する。入出力回路１０は横幅が小さいた
め、半導体チップ１０のｌｌｊ位にさ中に配置る数を増
加させることができる。従って、多数の人出ツノ回路を
形成づることができ、人出力信号の多数化に対応するこ
とｈ゛できる。The input/output circuit is formed so that the line connecting 13 is perpendicular to the side of the semiconductor chip. Since the width of the input/output circuits 10 is small, the number of input/output circuits 10 that can be arranged in the middle of the semiconductor chip 10 can be increased. Therefore, it is possible to form a large number of human output horn circuits, and it is possible to cope with an increase in the number of human output signals.
なお、実施例では、ｐチトネル素子を半導体チップの外
縁側に配したが、ｎチャネル素子を外縁側に配しても同
様な効果を得ることができる。In the embodiment, the p-channel device is arranged on the outer edge side of the semiconductor chip, but the same effect can be obtained even if the n-channel element is arranged on the outer edge side.
また、実施例では両導電型素子を結ぶ線が崖導体チップ
辺と直交するようになつ−Ｃいるが、厳密に９０″でな
くある角瓜をなすように配設してもよい。Further, in the embodiment, the line connecting both conductivity type elements is perpendicular to the edge of the cliff conductor chip, but it may be arranged so as to form a square melon, which is not strictly 90''.
第３図は本発明の他の実施例を示づ平面図であって、第
１図の場合と類似した構成となっているが、コーナ部の
構成が責なる。すなわち、コーナ部の入出力回ＶＢｉｏ
’の構成自体は第２図に示したものと全く同じであるが
、その配設方向はｎチャネル素子およびｎチャネル素子
を結ぶ線が半導体チップの中心を向うようになっている
。このようにコーナ部の入出力回路を配設することによ
りコーナ部のスペースを有効に活用することができる。FIG. 3 is a plan view showing another embodiment of the present invention, which has a structure similar to that of FIG. 1, but the structure of the corner portion is different. In other words, the input/output circuit VBio of the corner part
The configuration itself is exactly the same as that shown in FIG. 2, but the arrangement direction is such that the n-channel elements and the line connecting the n-channel elements face the center of the semiconductor chip. By arranging the input/output circuits in the corners in this manner, the space in the corners can be effectively utilized.
Ｃ発明の効果〕
以上のとおり本発明によれば、ボンディングパッドの両
側に一導電型素子Ｊ５よび逆導電型素子を配して入出力
回路を構成し、この入出力回路を一方の素子を半導体チ
ップ外縁側に他方の素子を内１ノ側に配置しているため
、ラップアップに強い構造とすることができ、また、−
辺に対して多くの入出力回路を配設することができるの
で、同一面積のチップに対して多数の入出力回路を形成
することができる。C Effects of the Invention] As described above, according to the present invention, an input/output circuit is constructed by arranging one conductivity type element J5 and an opposite conductivity type element on both sides of a bonding pad, and this input/output circuit is formed by using a semiconductor with one conductivity type element. Since the other element is placed on the outer edge side of the chip and the other element is placed on the inner side, it is possible to create a structure that is resistant to wrap-up.
Since many input/output circuits can be arranged for each side, a large number of input/output circuits can be formed on a chip having the same area.
第１図は本発明の一実施例に係る半導体装置の入出力回
路の配列を示す平面図、第２図はその入出力回路の構成
を示ず平面図、第３３図は本発明の他の実施例を示す平
面図、第４図は従来装置の入出力回路の平面図、第５図
はその配列を示寸平面図、第６図は別の従来装置の入出
力回路の平面図である。
１．７．１１・・・ボンディングパッド、２，８゜１２
・・・ｎチャネル素子、３，９．１３・・・ｎチャネル
素子、４．６，１０．１０’・・・入出力回路、５゜１
４・・・半導体チップ。
出願人代理人 ４ｊｉ、 藤 −雄Ｑ
汽 １ 図 島２ 図
も３ 口FIG. 1 is a plan view showing the arrangement of input/output circuits of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a plan view not showing the configuration of the input/output circuit, and FIG. FIG. 4 is a plan view of an input/output circuit of a conventional device, FIG. 5 is a plan view showing the arrangement thereof, and FIG. 6 is a plan view of an input/output circuit of another conventional device. . 1.7.11...Bonding pad, 2.8°12
...n channel element, 3,9.13...n channel element, 4.6,10.10'...input/output circuit, 5゜1
4...Semiconductor chip. Applicant's agent 4ji, Fuji-Yu Q Ki 1 Figure Shima 2 Figure 3 Mouth
Claims (1)
導電型素子が配された複数のＣＭＯＳ入出力回路が、そ
の一導電型素子または逆導電型素子のいずれか一方の素
子が半導体チップの外縁側に位置し、他方の素子が半導
体チップの内方側に位置するように配された半導体装置
。 ２、入出力回路の両導電型素子の中心を結ぶ線が半導体
チップの外周辺に対しほぼ９０°をなすように入出力回
路が配置された特許請求の範囲第１項記載の半導体装置
。 ３、半導体チップのコーナ部に位置する入出力回路のみ
が、両導電素子の中心を結ぶ線が半導体チップ中心を向
うように配設された特許請求の範囲第２項記載の半導体
装置。[Claims] 1. In a plurality of CMOS input/output circuits in which elements of one conductivity type and elements of opposite conductivity type are arranged on both sides of a bonding pad, either one of the elements of one conductivity type or the elements of opposite conductivity type A semiconductor device in which one element is located on the outer edge of the semiconductor chip, and the other element is located on the inner side of the semiconductor chip. 2. The semiconductor device according to claim 1, wherein the input/output circuit is arranged such that a line connecting the centers of both conductivity type elements of the input/output circuit makes approximately 90 degrees with respect to the outer periphery of the semiconductor chip. 3. The semiconductor device according to claim 2, wherein only the input/output circuits located at the corners of the semiconductor chip are arranged such that the line connecting the centers of both conductive elements faces the center of the semiconductor chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60213069A JPS6273656A (en) | 1985-09-26 | 1985-09-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60213069A JPS6273656A (en) | 1985-09-26 | 1985-09-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6273656A true JPS6273656A (en) | 1987-04-04 |
Family
ID=16633021
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60213069A Pending JPS6273656A (en) | 1985-09-26 | 1985-09-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6273656A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02137361A (en) * | 1988-11-18 | 1990-05-25 | Toshiba Corp | Semiconductor integrated circuit device |
| JPH02205067A (en) * | 1989-02-03 | 1990-08-14 | Toshiba Corp | Semiconductor circuit device |
| JP2006100436A (en) * | 2004-09-28 | 2006-04-13 | Toshiba Corp | Semiconductor device |
-
1985
- 1985-09-26 JP JP60213069A patent/JPS6273656A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02137361A (en) * | 1988-11-18 | 1990-05-25 | Toshiba Corp | Semiconductor integrated circuit device |
| JPH02205067A (en) * | 1989-02-03 | 1990-08-14 | Toshiba Corp | Semiconductor circuit device |
| JP2006100436A (en) * | 2004-09-28 | 2006-04-13 | Toshiba Corp | Semiconductor device |
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