JPH02137361A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To easily suppress a latch-up phenomenon by a method wherein semiconductor elements whose polarity is different from that of a circuit element generating a substrate current are arranged so as to sandwich a semiconductor element whose polarity is equal to that of the circuit element. CONSTITUTION:With reference to a pad 22, for bonding use, connected to an external output terminal, an N-channel transistor 1 is arranged at the inside of a chip 1 and a P-channel transistor 2 is arranged at the outside, i.e., on the side of a chip end (e). Since the P-channel transistor 2 is arranged on the side of the chip end (e), it is separated from an internal circuit by an amount of the pad region 22. As a result, even when a substrate current causing a latch-up is generated, a substrate resistance becomes large by an amount of a distance from the internal circuit; accordingly, a base current by a parasitic bipolar transistor is limited. Thereby, it is possible to enhance resistance to the latch-up.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor integrated circuit device, and particularly aims to prevent latch-up phenomena.

(Prior Art) In recent years, IC memory has experienced rapid growth in the integrated circuit market, and especially in the last few years, ultraviolet erasable and electrically programmable read-only memory (EPRO)
The market for M) is rapidly expanding. As this market expands, demands for large capacity, high speed, low power consumption, and low price have led to a noticeable movement to reduce power consumption by switching to 0MO3 peripheral devices.

(Problems to be Solved by the Invention) Conventionally, it has been difficult to convert EFROM to CMO8. The reason for this is that high voltage is required during programming,
Also, during writing, a substrate current of about several milliamps flows. This is because this can lead to a "latch-up phenomenon" which causes a large current to flow between the power supplies, which is a problem peculiar to the CMO8 circuit, and even causes destruction of the element. Furthermore, increasing the speed may also cause a "latch-up phenomenon."

By increasing the operating speed, at the output terminal,
Rapid charging and discharging will occur, and due to the capacitance, resistance, and inductor attached to the output terminal, the output potential will exceed
Shooting, undershooting, and ringing occur, and their radical fluctuations generate substrate current, which induces the "latch-up phenomenon."

The present invention has been made in view of the above-mentioned problems, and is based on a MOS semiconductor integrated circuit, in particular an MOS semiconductor integrated circuit made up of CMO8 circuits.
This is a devised element arrangement method aimed at improving the reliability of semiconductor integrated devices by increasing the latch-up resistance of OS semiconductor integrated circuits.

[Structure of the Invention] (Means and Effects for Solving the Problems) The present invention provides (a) a semiconductor substrate of one conductivity type, a semiconductor integrated circuit formed on this semiconductor substrate, and a semiconductor integrated circuit formed on the outside of this semiconductor integrated circuit. A first transistor constituting an output circuit for outputting data, a pad region for connecting the first transistor to an external output terminal, and a space between an end of the substrate and the first transistor. a second transistor having a polarity different from that of the first transistor formed on a well region which is arranged to constitute the output circuit and has a conductivity type opposite to that of the substrate, with respect to the pad region;
The semiconductor integrated circuit device is characterized in that the semiconductor integrated circuit device is arranged on the opposite side of the first transistor.

The present invention also provides a third transistor adjacent to the output circuit having the first transistor and having the same polarity as the first transistor constituting the first circuit;
A fourth transistor having a polarity different from that of the transistor is provided, and the third transistor is connected to the fourth transistor.The present invention also provides a fifth transistor to which a high voltage is supplied;
Adjacent to this is a 'ii6 transistor with the same polarity as the fifth transistor constituting the second circuit, and a seventh transistor with a different polarity from the fifth transistor, and the sixth transistor is The semiconductor integrated circuit device according to item (a) is characterized in that the semiconductor integrated circuit device is arranged between the fifth transistor and the seventh transistor. The present invention also provides an input protection circuit having a signal input terminal, a semiconductor region connected to the input terminal and provided on the substrate and having a conductivity type opposite to that of the substrate, and a third circuit adjacent to the input protection circuit. A ninth transistor having the same polarity as the semiconductor region constituting the semiconductor region and a tenth transistor having a different polarity from the semiconductor region are provided, and the ninth transistor is connected between the tenth transistor and the input protection circuit. The semiconductor integrated circuit device according to item (a) above is characterized in that the semiconductor integrated circuit device is arranged in the above item (a). The present invention also provides an eleventh transistor constituting a semiconductor memory circuit, a twelfth transistor adjacent to the eleventh transistor having at least the same polarity as the eleventh transistor, and a thirteenth transistor having a different polarity from the eleventh transistor. The semiconductor integrated circuit device according to item (a) above, further comprising a decoder circuit including a transistor, in which the twelfth transistor is arranged between the eleventh transistor and the thirteenth transistor. It is.

That is, the present invention provides for a circuit that generates a substrate current in a semiconductor integrated circuit to connect a circuit element that generates a substrate current with a semiconductor element that has the same polarity as the circuit element that generates the substrate current through a semiconductor element that has the same polarity as the circuit element that generates the substrate current. By arranging semiconductor elements, etc.
By separating the circuits and increasing the substrate resistance between the circuits, the substrate current is limited, making it possible to easily suppress the latch conflict phenomenon that causes excessive current between the power supplies and even destroys the element. It is.

(Embodiment) FIG. 1(a) is a pattern plan view of an embodiment of the present invention in the output circuit 21. N, sandwiching the bonding aluminum pad 22 connected to the output terminal.
A channel transistor 2 group 1 and a P channel transistor group 2 are arranged.

In circuits that consume a large amount of current, such as output circuits, and in addition, in circuits that are easily affected by external noise as external terminals, it is important to , which induces substrate current that causes latch-up.

For this reason, as shown in FIG. 1(a), an N-channel transistor 1 is arranged inside the chip with respect to a bonding pad 22 connected to an external output terminal, A P-channel transistor 2 is placed on the side. In this way, by placing the P-channel transistor 2 on the end e side of the chip,
It is separated from the internal circuit by the distance of the pad area 22.

Therefore, even when a substrate current occurs, which is a cause of latch-up, the base current due to the parasitic bipolar transistor is limited because the substrate resistance increases due to the distance from the internal circuit.

This makes it possible to increase the resistance to latch write-up.

FIGS. 1(b) to 1(g) are cross-sectional replicas of FIG. 1(a), where 23 is a P-type substrate, 24 is an N-well layer, and v c
c C power supply terminal, VSS is ground terminal, 251 to 252 and 30 are N+ layers, 26 is polysilicon electrode of N channel transistor group 2 group 1, 27 is P channel transistor group 2
The polysilicon electrodes 281 to 282 and 29 are P
layer, Trl is the P+ layer 281. N-well 24. P board 2
A parasitic PNP bipolar transistor consisting of 3, T'2
is the P layer 282. N-well 24. Parasitic PNP bipolar transistor made of P substrate 23, Tr3 is N well 2
4. P substrate 23. A parasitic NPN bipolar transistor, Tr4, consisting of the N+ layer 251 is connected to the N well 24. P board 2
3. A parasitic NPN bipolar transistor consisting of an N layer 25□, r1 to r3 are N well parasitic resistances, and r4 to r7 are P substrate parasitic resistances.

A method for suppressing the latch-up phenomenon will be described below using an example of the latch-up phenomenon with reference to FIGS. 1(b) to 1(g). In FIG. 1(b), a case will be described in which noise in the positive direction that is higher than the power supply voltage vCC is mixed into the external output terminal 22. At this time, the base of the parasitic PNP bipolar transistor T r 2 is connected to the well parasitic resistance '1+
Since T r 2 remains biased to the power supply vCC through r2, T r 2 turns on, and the P substrate parasitic resistance r5. '
6+ A current 11 flows through r7 to the ground terminal vSS.

When this current L1 flows, a potential gradient is generated in the P substrate 23, and a potential difference is generated between both ends of each of the P substrate parasitic resistances '5+'6+r7. Thereby, the parasitic N′PN
The base of bipolar transistor Tr4 is forward biased and Tr4 is turned on. Therefore, Figure 1 (C
), well parasitic resistance rl+r2. Current 12 flows through r3. In addition, as this current 12 flows, a potential effect occurs across the well parasitic resistance r2 to which the base of the parasitic PNP bipolar transistor Tr1 is connected, and as it becomes lower than the power supply voltage vCC, the base of Trl becomes forward biased, and Trl becomes forward biased. 1 turns on,
As shown in FIG. 1(d), the P substrate parasitic resistance '4. '5+
'6+ A current i3 flows to the ground terminal ■SS via r7. As this current i3 flows, the base of the parasitic NPN bipolar transistor T r ,1 is further biased in the forward direction, and the current 12 increases. By repeating the above operation, even if the noise mixed into the external output terminal 22 subsides, the current continues to flow from the power supply vCC to the ground terminal vSS, and this state continues until the power is turned off. This is the latch-up phenomenon. . In addition, the power supply voltage vCC may temporarily drop due to the influence of other external output circuits (for example,
．． 5V) and the external output terminal 22 has a voltage at the power supply voltage vCC level (for example, 5V),
The base of the parasitic PNP bipolar transistor Tr2 becomes forward biased through the well parasitic resistance rl+r2 and turns on, so a current 11 flows as shown in FIG. Up phenomenon occurs. Next, in FIG. 1(e), a case will also be described in which noise in the negative direction below the ground terminal voltage vSS is mixed into the external output terminal 22. At this time, the base is biased to the ground potential through the P substrate parasitic resistance '6+'7, so the parasitic NPN bipolar transistor Tr
3 turns on and the well parasitic resistance '1+r2゜r3
A current i4 flows through. The flow of this current i4 generates a potential gradient in the N well 24, causing a potential drop at the connection point of the well resistors rl+r2, the base of the parasitic PNP bipolar transistor Trl becomes forward biased, and Trl is turned on. As a result, a current i5 flows through the P substrate parasitic resistance ', 1 + r5 + r6 + r7 to the ground terminal SS as shown in Figure 1(f).
flows. As the current i5 flows in the P substrate 23, a potential gradient is also generated in the P substrate 23, and the base of the parasitic NPN bipolar transistor Tr,1 is forward biased, and Tr4 is turned on.

Therefore, well parasitic resistance r1. r2. A current i6 flows through r3 as shown in FIG. 1(g). This current i6
As a result, the potential gradient within the N-well 24 becomes even larger, and the base of the parasitic PNP bipolar transistor Trl is further biased in the forward direction, so that the current i5 increases. By repeating the above operation, a latch-up phenomenon occurs in which current continues to flow between the power supplies even if the noise has subsided, as described above. In addition, the ground terminal vSS is
Under the influence of other external output circuits, the ground terminal voltage sometimes rises (for example, about 0.5), and even when the external output terminal 22 is at the ground terminal voltage vSS level voltage (for example, OV),
Parasitic NPN via P substrate parasitic resistance r6+r7
Since the base of the bipolar transistor Tr3 is forward biased and turned on, the current i as shown in FIG. 1(e)
4 flows, the same operation as above is repeated, and a latch-up phenomenon occurs. From the above, it can be seen that the cause of the latch-up phenomenon is that the substrate current or well current flows, and the potential gradient due to the parasitic resistance of the substrate or well forward biases the base of the parasitic bipolar transistor. On the other hand, a method for preventing the latch-up phenomenon is to control the parasitic resistance, that is, to lower the parasitic resistance by using a guard ring or the like to suppress the potential gradient. There are also two methods of suppressing the substrate current or the well current itself by increasing the parasitic resistance. In the output circuit 21 which is an embodiment of the present invention, N
By increasing the distance between the channel transistor group 1 and the P-channel transistor group 2, the parasitic substrate resistance is increased, the substrate current is suppressed, and the latch-up phenomenon is suppressed.

Furthermore, as shown in the present invention, placing the N-we 11 region on the P-type substrate 23, which has a conductivity type opposite to that of this substrate, on the terminal end side of the chip further prevents latch-up. ing. Latch-up is specific to CMO8 integrated circuits and does not occur in NMO3 or PMO8 integrated circuits. In CMO3 integrated circuits, latch-up occurs due to the creation of transistors in well regions of opposite conductivity type to the substrate. That is, the main cause of latch-up is the transistor on the well region, and if this well region were not present, latch-up would not occur.

Therefore, the distance between the well region where the transistor connected to the output terminal, which is particularly prone to latch-up, is formed and other internal circuits is further increased. If the well region in which the transistor connected to the output terminal is formed is placed at the end of the chip as in the present invention, there will be no other circuits on the end, just the end of the chip. Therefore, to prevent latch-up, it is only necessary to place other internal circuits away from the inside of the chip, that is, only one side of the well region. This has the advantage that the area can be reduced, and since other circuits are placed only on one side of the well region, latch-up is less likely to occur.

FIG. 2 shows an embodiment of the present invention in which peripheral circuits are arranged close to the output circuit 21. In FIG. N in circuit 31 of the peripheral circuit
The second group of channel transistors 3 is placed on the output circuit 21 side, and the P-channel transistor group 4 in the circuit 31 is placed on the opposite side of the output circuit 21 from the second group of N-channel transistors 3. This means that even if N-channel transistors 2 in group 1 in the output circuit connected to the outside generate substrate current due to their own operation or external noise, this is a direct cause of latch-up. The substrate current is
As shown in FIG. 2, by arranging the P-channel transistor group 4 of the internal circuit 31 with the N-channel transistor group 3 of the internal circuit 31 sandwiched between the N-channel transistor 2 group 1 of the output circuit 21, the output The substrate resistance from the N-channel transistor group 1 of the circuit 21 to the P-channel transistor group 4 of the internal circuit 31 increases, making it difficult for substrate current to flow. That is, in order to separate the N-channel transistors 2 group 1 connected to the output terminal 22 into which noise enters and the P-channel transistor group 4, the N-channel transistors 2 group 3
Place it so that it goes through. As a result, latch-up resistance can be improved without increasing the circuit area.

FIG. 3 shows an embodiment of the invention in which peripheral circuitry is placed in close proximity to a circuit 42 to which a high voltage is supplied. The second group of N-channel transistors 6 in the circuit 41 of the peripheral circuit is a high voltage circuit 42 constituted by the seventh group of N-channel transistors 5.
The P-channel transistor group 7 in the circuit 41 is arranged on the side of the high voltage circuit 42, and the N-channel transistor group 7 in the circuit 41 is
They are placed apart from each other with group 6 in between. For example, in an electrically rewritable read-only memory (EFROM), a high voltage must be applied to the gate and drain of the memory element in order to write data to the memory element. Therefore, it is necessary to arrange a circuit that generates a high voltage for writing around the memory element. The problem is field leakage due to parasitic field transistors that occur due to the use of high voltages.
Substrate currents include breakdown current due to breakdown phenomenon at the PN junction, transient current due to internal chattering caused by resistance, capacitance, and inductor attached to high voltage wiring. Therefore, as shown in FIG. 3, in contrast to the N-channel transistors 7 group 5 that use high voltage, the P-channel transistor group 7 of the circuit 41 is sandwiched between the N-channel transistors 2 group 6 in the peripheral circuit 41. By placing the circuit 41 in the
high voltage circuit 42 from the P-channel transistor region 7 of
The substrate resistance of the substrate current flowing into the N-channel transistor region 5 in the middle, which is divided by the N-channel transistor group 6 of the circuit 41 arranged between them, increases, making it difficult for the substrate current to flow. As a result, latch-up resistance can be improved. "
That is, since the N-channel transistor group 5 of the high-voltage circuit 42 may generate substrate current, the N-well forming the P-channel transistor group 7 and the high-voltage N-channel transistor group 5 are combined into an N-channel transistor group. 6 in between, the latch-up trigger current is suppressed by increasing the substrate resistance shown in FIG. 1(b) without increasing the area occupied by the pattern. FIG. 4 shows an embodiment of the present invention in which a peripheral circuit 52 is arranged close to an input circuit 51. The N-channel transistor group 9 in the peripheral circuit 52 is arranged on the side of the input protection circuit constituted by the N-channel transistor group 8, and is arranged on the side of the input protection circuit constituted by the N-channel transistor group 8.
0 is placed apart from the input protection circuit with the N-channel transistor group 9 in between. Input protection circuit, especially M
Even if the device is not formed using an OS transistor but simply utilizes the junction breakdown between the N semiconductor region and the substrate, the same effect can be obtained by arranging the N+ region in this manner. In a CMOS semiconductor integrated circuit device, high voltages due to external noise and static electricity may enter the input protection circuit and input circuit 51 connected to external input terminals. When external noise below the reference potential is supplied to the input terminal 53, or when a high voltage is applied to the input terminal and a breakdown occurs in the input protection circuit, a current flows in the board, and this current causes latch-up. This will induce the phenomenon. Therefore, by disposing an N-channel transistor region 9 between the P-channel transistor region 10 and the N-channel transistor region 8 of the input protection circuit as shown in FIG. The protection circuit and the P-channel transistor region 10 can be separated from each other, increasing the substrate resistance and making it difficult for substrate current to flow. The N-channel transistor group 8 connected to the input terminal 53 is placed apart from the P-channel transistor group 10 because there is a risk of generating substrate current due to noise. As a result, latch-up resistance can be improved.

Further, if the input protection circuit or the N-channel transistor group 8 connected to the input terminal 53 is arranged on the terminal end side of the chip with respect to the pad, latch-up becomes even less likely to occur.

FIG. 5 shows a peripheral circuit 62 adjacent to a semiconductor memory circuit 61.
This is an embodiment of the present invention in which a. The second group of N-channel transistors 12 in the peripheral circuit 62 is arranged on the side of the semiconductor memory circuit 6 constituted by the N-channel transistor group 11, and the P-channel transistor group 13 in the circuit 62 is arranged on the side of the semiconductor memory circuit 6 constituted by the N-channel transistor group 11. It is arranged on the opposite side of the semiconductor memory circuit 61. As mentioned above, when writing data to a semiconductor memory element in an EFROM, a high voltage must be applied to the gate and drain of the memory element. Due to the high integration of recent EFROMs, the memory capacity has increased, and the time required to write data to all memory cells has become increasingly long.

As a result, data has conventionally been written at the pinch-off point of memory element operation, but now data is written in the avalanche region of memory element operation in order to shorten the write time. However, at this time, a substrate current of approximately several milliamperes flows through the substrate of the semiconductor memory element. This current causes latch up. Therefore, as shown in FIG. 5, the P channel transistor region 13 and
An N-channel transistor region 12 is arranged between the N-channel transistor region 11 and the N-channel transistor region 11 . As a result, the substrate resistance increases, and from the P channel transistor region 13 to the N channel transistor group 1 in the semiconductor memory circuit 61.
The substrate current to 1 becomes difficult to flow. As a result, latch-up resistance can be improved.

FIG. 6 shows a schematic diagram of a chip 81 of a semiconductor integrated circuit device made according to the embodiment of the invention described above.

In FIG. 6, the area surrounded by a chain line 71 is the output circuit explained in FIGS. A transistor group 2 is arranged. The area surrounded by a chain line 72 is the peripheral circuit 31 that is close to the output circuit 21 described in FIG. A group of P-channel transistors 4 is placed between the two. The area surrounded by the chain line 73 is the peripheral circuit 41 which is close to the N-channel transistor group 5 to which the high voltage explained in FIG. A P-channel transistor group 7 is arranged with a transistor group 6 in between. The area surrounded by a chain line 74 is the peripheral circuit 52 which is close to the input circuit 51 described in FIG. 9, a group of P-channel transistors 10
This is an embodiment of the present invention in which

The area surrounded by the chain line 75 is the peripheral circuit 62 which is close to the semiconductor memory circuit 61 described in FIG.
A P-channel transistor group 13 is placed between the N-channel transistor group 12 of the circuit 62. 76 is a group of N-channel transistors.

Further, the area surrounded by a solid line 91 is a row decoder. In this row decoder area, circuits must be arranged at the pitch of the memory cells, so each element is made extremely close to each other. Therefore, if the method according to the present invention is used, compared to the conventional method,
Latch-up is prevented from occurring, and the decoder forming area can also be reduced.

Note that the present invention is not limited to the above-mentioned embodiments, and can be applied in various ways. For example, in the present invention, the P type and N type of the embodiment
It is also possible to have a configuration in which the mold is reversed.

[Effects of the Invention] As explained above, according to the present invention, in a semiconductor integrated circuit, a circuit that generates a substrate current is provided with a semiconductor element having the same polarity as the circuit element that generates the substrate current.
By arranging a circuit element that generates substrate current and a semiconductor element with a different polarity, the substrate resistance is increased and the substrate current is restricted, resulting in excessive current between the power supplies and latch-up that can even destroy the element. A semiconductor integrated circuit device in which the phenomenon can be easily suppressed can be obtained. Also, especially
In the output circuit, since data is output to the outside, the transistor dimensions are set large. For this reason, in the past, latch-up was prevented by not only increasing the distance between the P-channel output transistor and the N-channel output transistor, but also by increasing the distance between the output transistor and the peripheral circuitry. However, in the present invention, as shown in FIG. 1, for example, a P channel transistor forming an output circuit or an N channel transistor forming an output circuit is placed at the end of the chip. There is also the advantage that there is no need to provide a particular distance between the transistor and the peripheral circuit, and the chip size can therefore be reduced.

[Brief explanation of the drawing]

FIG. 1(a) is a pattern plan view of an embodiment of the present invention, FIG. 1(b) to FIG. 1(g) are cross-sectional views of FIG. 1(a),
2 to 6 are pattern plan views of different embodiments of the present invention. 1... first transistor group (N-channel type), 2...
...Second transistor group (P-channel type) 3...Third transistor group (N-channel type), 4...Fourth transistor group (P-channel type), 5...(Fifth transistor group) Transistor group (N-channel type), 6... Sixth transistor group (N-channel type), 7... Seventh transistor group (P-channel type), 8... Eighth transistor group (N-channel type), 8... Eighth transistor group (N-channel type), 7... Seventh transistor group (P-channel type), ), 9...'! J9 transistor group (N-channel type), 10... 10th transistor group (P-channel type), 11... 11th transistor group (N-channel type), 12 ... 12th transistor group (N-channel type), 13... 13th transistor group (P-channel type), 21... Output circuit, 22... Output terminal (bonding AfI pad), 51. ...Input circuit, 61...Semiconductor memory, 81...Semiconductor chip.

Claims (5)

[Claims] (1) A semiconductor substrate of one conductivity type, a semiconductor integrated circuit formed on this semiconductor substrate, a first transistor constituting an output circuit for outputting data to the outside of this semiconductor integrated circuit, and this first transistor. a pad region for connecting the transistor to an external output terminal, an end portion of the substrate and the first transistor;
a second transistor having a polarity different from that of the first transistor, which is disposed between the first transistor and the first transistor to form the output circuit, and is formed on a well region having a conductivity type opposite to that of the substrate.
A semiconductor integrated circuit device, characterized in that a transistor is arranged on the opposite side of the first transistor with respect to the pad region. (2) A third transistor adjacent to the output circuit including the first transistor and having the same polarity as the first transistor constituting the first circuit, and a third transistor having a different polarity from the first transistor. 2. The semiconductor integrated circuit device according to claim 1, wherein four transistors are provided, and the third transistor is arranged between the fourth transistor and the first transistor. (3) A fifth transistor to which a high voltage is supplied, an adjacent sixth transistor constituting a second circuit and having the same polarity as the fifth transistor, and a fifth transistor having the same polarity as the fifth transistor. providing a different seventh transistor;
2. The semiconductor integrated circuit device according to claim 1, wherein the sixth transistor is arranged between the fifth transistor and the seventh transistor. (4) An input protection circuit having a signal input terminal, a semiconductor region connected to the input terminal and provided on the substrate and having a conductivity type opposite to that of the substrate, and a third circuit adjacent to the input protection circuit. a ninth transistor having the same polarity as the semiconductor region and a tenth transistor having a different polarity from the semiconductor region;
2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is arranged between a transistor No. 0 and the input protection circuit. (5) An eleventh transistor constituting a semiconductor memory circuit, a twelfth transistor adjacent thereto and having at least the same polarity as the eleventh transistor, and a thirteenth transistor having a different polarity from the eleventh transistor. 2. The semiconductor integrated circuit device according to claim 1, further comprising a decoder circuit in which the twelfth transistor is arranged between the eleventh transistor and the thirteenth transistor.