JPS6271869A - Frequency detecting device - Google Patents

Frequency detecting device

Info

Publication number
JPS6271869A
JPS6271869A JP21377685A JP21377685A JPS6271869A JP S6271869 A JPS6271869 A JP S6271869A JP 21377685 A JP21377685 A JP 21377685A JP 21377685 A JP21377685 A JP 21377685A JP S6271869 A JPS6271869 A JP S6271869A
Authority
JP
Japan
Prior art keywords
frequency
channel
pulse
measurement
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21377685A
Other languages
Japanese (ja)
Inventor
Naoki Fujiyama
藤山 直樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP21377685A priority Critical patent/JPS6271869A/en
Publication of JPS6271869A publication Critical patent/JPS6271869A/en
Pending legal-status Critical Current

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  • Measuring Frequencies, Analyzing Spectra (AREA)

Abstract

PURPOSE:To improve detection precision by generating a measurement trigger by a measurement timing generating circuit at prescribed intervals of time so as to measure a varying input frequency and then detecting the current frequency. CONSTITUTION:The measurement timing generating circuit 9 generates the measurement trigger at prescribed intervals of time and supplies it to an A/D converter 3 and a channel selecting circuit 4. Then, an input pulse from an input terminal 1 is inputted from a filter bank 2 to the converter 3 and each video output level is measured at every timing of trigger. Then, the channel selecting circuit 4 compares the output level by the trigger and when its channel is higher, a peak detection signal is outputted to an output line 5. A frequency calculating circuit 7 detects the channel number and frequency of the peak detection signal and outputs them to an output line 8. Consequently, the frequency and variation of the input pulse are detected precisely.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、並列ろ波器受信機用の周波数検出装置に関
するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a frequency detection device for a parallel filter receiver.

し従来の技術〕 従来の並列ろ波器受信機における周波数検出装置の一般
的な構成を第3図に示す。図において、(1)は入力端
子、(2)はGauss型特性のフィルタで構成される
フィルタ・バンク、(3)ばA/D変換器、(4)は自
チャンネルの出力レベルと両隣のチャンネルの出力レベ
ルと比較して、自ヂャンネルの出力レベルがピークとな
るチャンネルを検出するチャンネル選択回路、(5)は
ピーク検出信号の出力線、4[ia) (tl、b)は
周波数検出に用いる両隣のチャンネル出力−レベルの出
力線、(7)は周波数算出回路であり、(8)はその算
出周波数の出力線である。
BACKGROUND ART FIG. 3 shows a general configuration of a frequency detection device in a conventional parallel filter receiver. In the figure, (1) is the input terminal, (2) is the filter bank consisting of filters with Gaussian characteristics, (3) is the A/D converter, and (4) is the output level of the own channel and the channels on both sides. (5) is the output line of the peak detection signal, and 4[ia] (tl, b) is used for frequency detection. Channel output-level output lines on both sides (7) are frequency calculation circuits, and (8) is an output line of the calculated frequency.

茫初に、周波数算出の原理を説明する。First, the principle of frequency calculation will be explained.

Gauss型特性のフィルタで構成されるフィルタ・バ
ンク(2)に周波数rのパルス1波が入力した時の出力
レベルのモデル図を第4図に示す。ここで、チャンネル
#にのフィルタ出力レベルをPAkとずろ。図において
、フィルタ出力がピークになるチャンネル (ピーク“
しベルチャンオル)(:#lである。その時、両隣のチ
ャンネルの化カニ、 、、、+ル差(PA・−r−PA
+−+)から#ムの中心周波数f、に対する相対周波数
△fが一意的に求まる。従って、入力パルスの周波数は
、 11+Δfで求めろことができる。
FIG. 4 shows a model diagram of the output level when one pulse wave of frequency r is input to the filter bank (2) composed of filters with Gaussian characteristics. Here, the filter output level for channel # is shifted from PAk. In the figure, the channel where the filter output peaks (peak “
(:#l) At that time, the difference between the channels on both sides, ,,, +le
+-+) to the center frequency f of #m, the relative frequency Δf is uniquely found. Therefore, the frequency of the input pulse can be found by 11+Δf.

次に上記の原理に基づいて、第3図で示される構成の動
作について説明する。入力端子(1)からの入力パルス
は、フィルタバンク(2)を通り、各フィルタの中心周
波数に対する相対入力周波数相当の減衰をうける。フィ
ルタ・パンク(2)の各チャンネル対応のA/D変換器
(3)では、名フィルタを通過した出力ビデオの出力レ
ベルを測定する。各チャンネル対応のチャンネル選択回
路(4)は、自チャンネルのパルス立上がりを検出し、
パルス立上がりの一定時間後に、自チャンネルの出力レ
ベルと両隣のチャンネルの出力レベルとを比較し、自チ
ャンネルの出力レベルが、両隣のチャンネルの出力レベ
ルよりも高い場合に、ピーク検出信号+ b=力線(5
1ヘ1;力する。同時に、出力線(6a) 、 (6b
) ヘ、両隣のチャンネルの出力レベルPA、−,,P
AI+□を出力′9−る。周波数算出回路(7)は、ピ
ーク検出信号が存在するチャンネル番号と、出力レベル
PA+−+、P、〜t+Iから入力パルスの周波数を検
出し、周波数値を出力線(8)へ出力する。
Next, the operation of the configuration shown in FIG. 3 will be explained based on the above principle. The input pulse from the input terminal (1) passes through the filter bank (2) and is attenuated by the relative input frequency with respect to the center frequency of each filter. The A/D converter (3) corresponding to each channel of the filter puncture (2) measures the output level of the output video that has passed through the filter. A channel selection circuit (4) corresponding to each channel detects the pulse rising edge of its own channel,
After a certain period of time after the pulse rises, the output level of the own channel is compared with the output level of the channels on both sides, and if the output level of the own channel is higher than the output level of the channels on both sides, the peak detection signal + b = power Line (5
1 to 1; force. At the same time, output lines (6a), (6b
) F, Output levels of adjacent channels PA, -,,P
Output AI+□'9-. The frequency calculation circuit (7) detects the frequency of the input pulse from the channel number where the peak detection signal exists and the output levels PA+-+, P, ~t+I, and outputs the frequency value to the output line (8).

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来の周波数検出装置では、入力パルスの立上がりを基
準とし、それから一定時間後の周波数を検出しているた
め、パルス内の周波数が一定である場合は有効であるが
、パルス圧縮(周波数チャープ)レーダ・パルスの様に
、パルス内で周波数が変F!(変化)する場合には、パ
ルス内の周波数変化が検出できない問題点があった。
Conventional frequency detection devices use the rising edge of the input pulse as a reference and detect the frequency after a certain period of time, which is effective when the frequency within the pulse is constant, but pulse compression (frequency chirp) radar・Like a pulse, the frequency changes within the pulse F! (change), there was a problem that the frequency change within the pulse could not be detected.

この発明は、上記の問題点を解消するためになされたも
ので、パルス内の周波数変化を検出することができる周
波数検出装置を得ることを目的とする。
The present invention was made to solve the above problems, and an object of the present invention is to obtain a frequency detection device that can detect frequency changes within a pulse.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係わる周波数検出装置は、所定周期のタイミ
ングパルスを発生するタイミング発生回路を設け、この
タイミングパルスを測定トリがパルスとして、A/D変
換器及びチャンネル選択回路に供給したものである。
The frequency detection device according to the present invention is provided with a timing generation circuit that generates a timing pulse of a predetermined period, and a measurement device supplies this timing pulse as a pulse to an A/D converter and a channel selection circuit.

〔作 用〕[For production]

この発明における測定タイミング発生回路は、変化する
入力周波数を測定するために、規定時間間隔ごとに、各
チャンネル対応のA/D変換器と、チャンネル選択回路
へ周波数測定トリガを出力し、そのl−リガタイミング
毎にその時点における周波数を検lJ1する。
The measurement timing generation circuit according to the present invention outputs a frequency measurement trigger to the A/D converter corresponding to each channel and the channel selection circuit at specified time intervals in order to measure the changing input frequency. At each trigger timing, the frequency at that point in time is detected lJ1.

〔発明の実施例〕[Embodiments of the invention]

以下、この発明の一実施例を図にっ1ハて説明する。第
二図において、(1)〜(8)まで【;【従来の第2図
と同様である。(9)は規定時間ごと(所定周期)の制
定トリガを発生させろ測定タイミング発生回路で、その
測定トリガタイミングパノ【スは、A/Ll変換器(3
)及びチャンネル選択化回路(4)にそれぞれ供給され
ている。
An embodiment of the present invention will be described below with reference to the drawings. In FIG. 2, (1) to (8) are similar to the conventional FIG. (9) is a measurement timing generation circuit that generates an established trigger every specified time (predetermined period), and the measurement trigger timing panorama is determined by the A/Ll converter (3
) and a channel selection circuit (4), respectively.

第2図;よ、パルス圧縮(周波数チャー−1°)レーダ
パルスに関するフィルタバンク(2)の各チャンネルご
との出力ビデオの例を示すものである。この図からも分
かるように規定時間間隔で、各チャンネルの出力レベル
を測定し、規定時間間隔ごとの周波数を求めることによ
り、パルス内の周波数変化を検出することができる。
FIG. 2 shows an example of the output video for each channel of filter bank (2) for a pulse compressed (frequency chart -1°) radar pulse. As can be seen from this figure, by measuring the output level of each channel at specified time intervals and finding the frequency at each specified time interval, it is possible to detect frequency changes within the pulse.

第1図において、入力端子(1)からの入力パルスは、
フィルタバンク(2)を通り、各フィルタの中心周波数
に対する相対入力周波数相当の減衰をうける。測定タイ
ミング発生回路(9)は、規定時間間隔で測定トリガを
発生する。フィルタバンクの各チャンネル対応のA/D
変換器(3)では測定トリガによって、各フィルタを通
過した出力ビデオの出力レベルを、測定する。そして、
各チャンネル対応のチャンネル選択口#1f41は、測
定l・リガよって、自チャンネルの出力レベルと両隣の
チャンネルの出力レベルとを比較し、自チャンネルの出
力レベルが両隣のチャンネルの出力レベルよりも高い場
合に、ピーク検出信号を出力線(5)へ出力する。同時
に、出力線(6aL (6b)は、両隣のチャンネルの
出力レベルを出力する。周波数算出回路(7)は、ピー
ク検出信号が存在するチャンネル番号と両隣チャンネル
の出方レベルとを用いて周波数を検出し、周波数値を出
力線(8)へ出方する。
In Figure 1, the input pulse from input terminal (1) is
The signal passes through the filter bank (2) and is attenuated by the relative input frequency with respect to the center frequency of each filter. The measurement timing generation circuit (9) generates measurement triggers at regular time intervals. A/D for each channel of filter bank
The converter (3) uses a measurement trigger to measure the output level of the output video that has passed through each filter. and,
Channel selection port #1f41 corresponding to each channel compares the output level of its own channel with the output level of the channels on both sides using the measurement latch, and if the output level of its own channel is higher than the output level of the channels on both sides. Then, the peak detection signal is output to the output line (5). At the same time, the output line (6aL (6b)) outputs the output level of the channels on both sides.The frequency calculation circuit (7) calculates the frequency using the channel number where the peak detection signal exists and the output level of the channels on both sides. and output the frequency value to the output line (8).

以上の動作を規定時間間隔ごとに繰り返して行うことに
より、入力パルスの周波数およびその周波数変化を精度
よく測定)”ることができろ。
By repeating the above operations at regular time intervals, it is possible to accurately measure the frequency of the input pulse and its frequency change.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば規定時間間隔で、濯波
数を算出するための測定トリガを発生する測定タイミン
グ発生回路を設けたので、従来、検出が出来なかったパ
ルス圧縮(周波数チャープ)レーダ等のパルス内周波数
変化を精度よく検出できるという効果がある。
As described above, according to the present invention, since a measurement timing generation circuit is provided that generates a measurement trigger for calculating the number of waves at specified time intervals, pulse compression (frequency chirp) radar, which could not be detected conventionally, can be used. This has the effect of being able to accurately detect intra-pulse frequency changes such as.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、この発明による周波数検出装置の一実施例を
示すブロック構成図、第2図は、第1図の動作を説明す
るために用いたパルス圧縮レーダの動作説明図、第3図
は従来の並列ろ波器受信機用の周波数検出装置のブロッ
ク構成図、第4図ば並列ろ波器受信機用1波入力時の動
作原理を示すモデル図である。 図1こおいて、(2)はフィルタバンク、(3)はA/
D変換器、(4)はチャンネル選択回路、(7)は周波
数算出回路、]9)iよ測定タイミング発生回路である
。 なお、図中同一符号は同一またLよ相当部分を示す。
FIG. 1 is a block diagram showing an embodiment of the frequency detection device according to the present invention, FIG. 2 is an explanatory diagram of the operation of a pulse compression radar used to explain the operation of FIG. 1, and FIG. FIG. 4 is a block configuration diagram of a conventional frequency detection device for a parallel filter receiver, and a model diagram showing the operating principle when one wave is input to the parallel filter receiver. In Figure 1, (2) is a filter bank, (3) is an A/
D converter, (4) is a channel selection circuit, (7) is a frequency calculation circuit, ]9) i is a measurement timing generation circuit. Note that the same reference numerals in the drawings indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] 周波数分割された各チャンネルに対応して並設された帯
域フィルタ群を有するフィルタバンクと、このフィルタ
バンク各チャンネルの出力信号をそれぞれA/D変換す
るA/D変換器と、このA/D変換器各チャンネルの出
力レベルを用いて、ピークレベルチャンネルを検出する
チャンネル選択回路と、ピークレベルチャンネルの両隣
のチャンネルの出力レベルから上記フィルタバンクに入
力される入力信号の周波数を検出する周波数算出回路を
有する周波数検出装置において、所定周期の測定トリガ
タイミングパルスを発生し、このパルスを上記A/D変
換器及びチャンネル選択回路に供給する測定タイミング
発生回路を備え、上記測定トリガタイミングパルス毎に
周波数の検出を行うようにしたことを特徴とする周波数
検出装置。
A filter bank having a group of bandpass filters arranged in parallel corresponding to each frequency-divided channel, an A/D converter that A/D converts the output signal of each channel of this filter bank, and this A/D conversion. a channel selection circuit that detects the peak level channel using the output level of each channel; and a frequency calculation circuit that detects the frequency of the input signal input to the filter bank from the output levels of the channels on both sides of the peak level channel. The frequency detection device includes a measurement timing generation circuit that generates a measurement trigger timing pulse of a predetermined period and supplies this pulse to the A/D converter and channel selection circuit, and detects a frequency for each measurement trigger timing pulse. A frequency detection device characterized by performing the following.
JP21377685A 1985-09-25 1985-09-25 Frequency detecting device Pending JPS6271869A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21377685A JPS6271869A (en) 1985-09-25 1985-09-25 Frequency detecting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21377685A JPS6271869A (en) 1985-09-25 1985-09-25 Frequency detecting device

Publications (1)

Publication Number Publication Date
JPS6271869A true JPS6271869A (en) 1987-04-02

Family

ID=16644841

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21377685A Pending JPS6271869A (en) 1985-09-25 1985-09-25 Frequency detecting device

Country Status (1)

Country Link
JP (1) JPS6271869A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0862263A (en) * 1994-06-13 1996-03-08 Tech Res & Dev Inst Of Japan Def Agency Signal processing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0862263A (en) * 1994-06-13 1996-03-08 Tech Res & Dev Inst Of Japan Def Agency Signal processing method

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