JPS6271442A - System stabilizer - Google Patents

System stabilizer

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Publication number
JPS6271442A
JPS6271442A JP60211630A JP21163085A JPS6271442A JP S6271442 A JPS6271442 A JP S6271442A JP 60211630 A JP60211630 A JP 60211630A JP 21163085 A JP21163085 A JP 21163085A JP S6271442 A JPS6271442 A JP S6271442A
Authority
JP
Japan
Prior art keywords
power
processing unit
information
rationality
central processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60211630A
Other languages
Japanese (ja)
Inventor
正 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP60211630A priority Critical patent/JPS6271442A/en
Publication of JPS6271442A publication Critical patent/JPS6271442A/en
Pending legal-status Critical Current

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  • Remote Monitoring And Control Of Power-Distribution Networks (AREA)
  • Supply And Distribution Of Alternating Current (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、系統安定化装置、特に電力系統動揺時に系統
の安定化を図る系統安定化装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a system stabilizing device, and particularly to a system stabilizing device that stabilizes a power system during power system fluctuations.

〔発明の技術的背景〕[Technical background of the invention]

近年、電力系統の大規模化及び複雑化に伴い、税調など
Kよる系統事故波及が大きな問題となりてきた。したが
りてその対策として、tカ系統動揺時に電源し中断、負
荷し御所などを行ない系統の安定化を図る系統安定化装
置が設置される。
In recent years, as electric power systems have become larger and more complex, the spread of grid failures due to K, such as tax regulations, has become a major problem. Therefore, as a countermeasure to this problem, a system stabilization device is installed that stabilizes the system by turning on the power, interrupting the system, and applying load to the power station when the system is in turmoil.

第8図にこのような系統安定化装置の一般的な構成図を
示す。第8図において、71は端末装置であ多系統各所
にある発電所及び変電所などに夫未設置され、系統の局
所的電圧情報、電流情報、電力情報及びCB、LS等の
0N10FF情報などの系統情報をシステムに導入する
機能を有する。72は中央演算装置であシ代表発電所又
は変電所に設°装置され、端末装置71にて導入した各
種系統情報を伝送系73を介して受信し、0所の端末装
置の情報と合せて系統の安定化に必要な処理を行ない、
その処理結果を伝送系73を用いて端末装置71へ送出
する機能を有する。また伝送系73は0所以外の各端末
装置71と共に中央演算装置72と接続され、前記各端
末装置にて導入した系統情報を中央演算装置に伝送する
機能と、前記中央演算装置の系統安定化処理結果を、各
端末装置に伝送する機能を有する。
FIG. 8 shows a general configuration diagram of such a system stabilizing device. In Fig. 8, 71 is a terminal device that is installed in power plants and substations located in various locations in multiple systems, and is used to collect information such as local voltage information, current information, power information, and 0N10FF information such as CB and LS of the system. It has the function of introducing lineage information into the system. Reference numeral 72 is a central processing unit installed at a representative power plant or substation, which receives various system information introduced at the terminal device 71 via the transmission system 73, and combines it with the information from the terminal device at 0. Perform the necessary processing to stabilize the system,
It has a function of sending the processing results to the terminal device 71 using the transmission system 73. The transmission system 73 is connected to the central processing unit 72 together with each terminal device 71 other than 0, and has a function of transmitting system information introduced at each terminal device to the central processing unit and stabilizing the system of the central processing unit. It has a function to transmit processing results to each terminal device.

以上のような系統安定化装置は、系統動揺時に確実に動
作し得るように、常時監視、点検などの自動監視機能を
有している。そして従来、この自動監視は各端末装置7
1.中央演算装置72及び伝送系73の各々に対して行
なわれ、不要発生時は各装置にて警報1表示等を行なっ
ていた。
The system stabilizing device described above has automatic monitoring functions such as constant monitoring and inspection so that it can operate reliably during system fluctuations. Conventionally, this automatic monitoring was performed on each terminal device 7.
1. This is done for each of the central processing unit 72 and the transmission system 73, and when an unnecessary occurrence occurs, alarm 1 is displayed in each device.

〔背景技術の問題点〕[Problems with background technology]

上記構成を有する従来装置では、各装置側々の不良線検
出できても、システムとしての装置不良の検出は困難で
ある。例えば端末装置の入力部に不良が生じ、所定の結
果が得られない場合、これを端末装置にて検出するため
には、大力部の2風化による監視等の構成が必要となシ
、その結果システム全体としてのハード規模が増大する
こととなる。
In the conventional device having the above configuration, even if it is possible to detect defective lines on each device side, it is difficult to detect device defects as a system. For example, if a defect occurs in the input section of a terminal device and the desired result cannot be obtained, in order to detect this on the terminal device, a configuration such as monitoring using two large power sections is required. This increases the hardware scale of the entire system.

〔発明の目的〕[Purpose of the invention]

本発明は上記問題点を解決するためになされたものであ
シ、系統安定化ンステム全体としての装置不良の検出が
可能な系統安定化装置を提供するととわ目的としている
The present invention has been made to solve the above-mentioned problems, and it is a specific object of the present invention to provide a system stabilizing device capable of detecting device failures in the system as a whole.

〔発明の概要〕[Summary of the invention]

本発明では、伝送系を介して中央演算装置に取込まれる
各端末装置からの情報と、0所の情報とを用いて、制御
所に設けた中央演算装置と被制御所に設けた端末装置と
これらの間を結ぶ伝送系の装置不良を、系統の合理性に
基づいて一括監視しようとするものである。
In the present invention, information from each terminal device that is taken into the central processing unit via the transmission system and information from the zero location are used to connect the central processing unit installed in the control center and the terminal equipment installed in the controlled station. The objective is to collectively monitor equipment failures in the transmission system that connects these systems based on the rationality of the system.

〔発明の実施例〕[Embodiments of the invention]

以下図面を参照して実施例を説明する。第1図は本発明
による系統安定化装置の一実施例のシステム構成図であ
る。なお第1図は4個所の発電所A、B、C,Dに夫々
端末装置71A、71B。
Examples will be described below with reference to the drawings. FIG. 1 is a system configuration diagram of an embodiment of a system stabilizing device according to the present invention. In addition, in FIG. 1, terminal devices 71A and 71B are installed at four power stations A, B, C, and D, respectively.

71C,71Dを備え、これらと変電所Pに備えた中央
演算装置72Pとの間を伝送系73A。
71C and 71D, and a transmission system 73A is provided between these and a central processing unit 72P provided in the substation P.

73B 、73C及び73Dとで結んだ構成図として示
す。
It is shown as a configuration diagram connected by 73B, 73C, and 73D.

第1図において、11は変電所の母線、12A〜12D
は発電機、13A〜13Fa前記母線に接続される送電
線、14A−14Fは各送電線に設けた変流器、15A
−15Fは各送電線に設けた計器変成器、16A−16
Jはし中断器、17A〜17Dは各発電所の変圧器であ
る。端末装置71Aは変流器14A及び計器用変圧器1
5Aを介して、送電線13Aの電流、電圧及びし中断器
Z 6 B (1)ON10FF条件が取込まれる。同
様に他の端末製置屋2〜扁4も該当送電線からの電流、
電圧及びし中断器の0N10FF条件が取込まれる@一
方、変電所Pに設けた中央演算装置72Pでは、変流器
14)i8.14F及び計器用変圧器15E。
In Figure 1, 11 is the busbar of the substation, 12A to 12D
is a generator, 13A to 13Fa are power transmission lines connected to the busbars, 14A to 14F are current transformers installed on each power transmission line, and 15A are
-15F is the instrument transformer installed on each power transmission line, 16A-16
17A to 17D are transformers of each power plant. The terminal device 71A includes a current transformer 14A and an instrument transformer 1.
5A, the current and voltage of the power transmission line 13A and the interrupter Z 6 B (1) ON10FF condition are taken in. Similarly, other terminal manufacturing shops 2 to 4 also receive current from the corresponding power transmission line,
The voltage and interrupter 0N10FF conditions are taken in. On the other hand, in the central processing unit 72P provided in the substation P, the current transformer 14) i8.14F and the voltage transformer 15E.

15Fを介して、送電線131.13Fの電流、電圧及
び母線につながるし中断器条件が夫々取込れる。なお中
央演算装置72Pには前記各端末装置ムl−ム4からの
各情報が、伝送系73A〜73Dを介して受信される。
15F connects to the current, voltage and busbar of power lines 131 and 13F, and the interrupter conditions are captured, respectively. Note that the central processing unit 72P receives each piece of information from each of the terminal devices M1-M4 via the transmission systems 73A to 73D.

第2図は端末装置の一実施例の構成図である。FIG. 2 is a configuration diagram of an embodiment of the terminal device.

第2図において、21A、21Bは電圧用入力変換器及
び電流用入力変換器、22は電力変換器、23A〜23
Cはフィルタ、24A〜24Cはサングルホールド回路
、25はマルチプレクサ、26はル勺変換器、27 a
 P/8変換器である。そして電力系統からの電圧、電
流は入力変換器21人。
In FIG. 2, 21A and 21B are voltage input converters and current input converters, 22 is a power converter, and 23A to 23
C is a filter, 24A to 24C are sample hold circuits, 25 is a multiplexer, 26 is a linear converter, 27a
It is a P/8 converter. There are 21 input converters for voltage and current from the power grid.

21B及び電力変換器22に導入されて、適当な大きさ
の電圧信号に変換される。これらの各出力はアナログフ
ィルタ23A〜23Cにて高調波成分が除去された後、
サンプルホールド回路24A〜24Cで所定の間隔でサ
ンプリングされる0すンプルホールド回路24A〜24
Cからの出力はマルチプレクサ25を介してん1変換器
26に入力され、ディジタル値に変換された後、し中断
器条件等の0N10FF情報と共に・臂うレル/シリア
ル変換器(以下P/S変換器)27によってシリアル信
号に変換されて、伝送系に送られる。
21B and a power converter 22, where it is converted into a voltage signal of an appropriate magnitude. After harmonic components are removed from each of these outputs by analog filters 23A to 23C,
0 sample hold circuits 24A to 24 sampled at predetermined intervals by sample hold circuits 24A to 24C
The output from C is input to the N1 converter 26 via the multiplexer 25, where it is converted into a digital value and then converted to a P/S converter (hereinafter referred to as P/S converter) along with 0N10FF information such as interrupter conditions. ) 27 into a serial signal and sent to the transmission system.

第3図は中央演算装置の一実施例の構成図である。第3
図において、送電線13gと13F’との各電圧、電流
入力は、入力変換器21C,21D(21E、21F)
、電力変換器22 A (22B)を介して入力され、
アナログフィルタ230〜23F(23G〜23K)、
サンプルホールド回′Nr24D 〜24F(24G 
〜24I )、マルチプレクサ25.A/1)変換器2
6によって適当な大きさのディジタル値に変換されるこ
とは第2図で既に説明した端末装置の場合と同様である
FIG. 3 is a block diagram of an embodiment of the central processing unit. Third
In the figure, each voltage and current input to the power transmission lines 13g and 13F' are input to input converters 21C, 21D (21E, 21F).
, is input via the power converter 22A (22B),
Analog filter 230~23F (23G~23K),
Sample hold times'Nr24D ~24F (24G
~24I), multiplexer 25. A/1) Converter 2
6 into a digital value of an appropriate size is the same as in the case of the terminal device already explained with reference to FIG.

一方、41〜墓4の各端末装置71A〜71Dから各伝
送系73A〜73Dを介して送信されてきたディジタル
シリアル信号は、変電所側にある7リアル/パラレル変
換器(S/P変換器)31A〜31Dに入力され、前記
した口折のディジタル信号及びし中断器等の0N10F
F情報と共に、ダイレクト・メモリ・アクセス回路(以
下DMA ) 32 K !°、って、メモリ回路の所
定のアドレスに書込まれる◎このメモリ回路の内容は、
ROM 35に予め記憶させておいたプログ2ムにした
がって、CPU 34にて演算され、この演算結果に基
づいて制御指令、警報、表示等を出力回路36から出力
する。
On the other hand, the digital serial signals transmitted from each terminal device 71A to 71D of 41 to Tomb 4 via each transmission system 73A to 73D are sent to a 7 real/parallel converter (S/P converter) on the substation side. 31A to 31D, the above-mentioned digital signals and interrupters, etc. 0N10F
Along with the F information, a direct memory access circuit (hereinafter referred to as DMA) 32K! °, is written to a predetermined address in the memory circuit ◎The contents of this memory circuit are
Calculations are performed by the CPU 34 according to a program stored in advance in the ROM 35, and control commands, alarms, displays, etc. are outputted from the output circuit 36 based on the results of the calculations.

第4図は系統安定化演算に付加する監視9機能を説明す
る機能図である。
FIG. 4 is a functional diagram illustrating nine monitoring functions added to the system stabilization calculation.

第4図において41A〜41Fは前記メモリ回路33に
記憶されている各発電所の発電電力量(p、〜pD)と
負荷電力量(Pg t P? )とである。
In FIG. 4, 41A to 41F are the generated power amount (p, to pD) and the load power amount (Pg t P?) of each power plant stored in the memory circuit 33.

即ち、加算回路42Aでは発電電力量の総和を求め1、
加算回路42Bでは負荷電力量の総和を求めている。そ
して各加算回路の出力は演算判定回路43に加えられ、
p、−g(p2(p、+1の判定を行なう、即ち、この
判定は中ルヒホッフの法則に基づき、P、とP2とが等
しいことを用°いて装置の不良を検出するものである。
That is, the adder circuit 42A calculates the total amount of generated power and calculates 1,
The adder circuit 42B calculates the total amount of load power. The output of each adder circuit is then added to an arithmetic judgment circuit 43,
p, -g(p2 (p, +1) is determined, that is, this determination is based on Naka-Ruchhoff's law and uses the fact that P and P2 are equal to detect a defect in the device.

なお8は装置の誤差で電力変換器及び〜Φ変換器等の誤
差によって決定される。したがって、処理内容は第5図
のフローチャートのようになシ、上記判定成立時は第3
図の演算判定回路43の出力はrlJとなシ、装置正常
処理回路44にて正常時の処理を行なう。また上記判定
不成立時は演算判定回路43の出力は「0」となり、イ
ンバータ回路45を経て装置異常処理回路46にて、装
置不良として警報、表示したシ、安定化演算の出力をロ
ックした)する。
Note that 8 is an error of the device, which is determined by errors of the power converter, the ~Φ converter, etc. Therefore, the processing contents are as shown in the flowchart of Fig. 5, and when the above judgment is satisfied, the third
The output of the operation determination circuit 43 shown in the figure is rlJ, and the apparatus normal processing circuit 44 performs normal processing. When the above judgment is not satisfied, the output of the calculation judgment circuit 43 becomes "0", and via the inverter circuit 45, the device abnormality processing circuit 46 generates an alarm indicating that the device is defective, and locks the output of the stabilization calculation. .

W、6図は監視機能の他の実施例を説明するための構成
図であシ、本実施例では回路構成上の合理性を基本とし
たものである。第6図から明らかなように、発電機の出
力中は当該発電機に対応する送電線のしゃ断器CBが「
入」状態であると云う合理性に基づく。ここで監視機能
を示す61A〜61Dの演算回路は、第1図に示す各発
電機12A〜12Dが発電中であることを判定する回路
FIG. 6 is a configuration diagram for explaining another embodiment of the monitoring function, and this embodiment is based on the rationality of the circuit configuration. As is clear from Fig. 6, when the generator is outputting power, the breaker CB of the power transmission line corresponding to the generator is
It is based on the rationality of being in a state of "in". Here, the arithmetic circuits 61A to 61D indicating the monitoring function are circuits that determine whether each of the generators 12A to 12D shown in FIG. 1 is generating power.

62A〜62Dは各発電機に接続された送電線の母線側
し中断器CBが「入」状態であることを判定する回路、
63A〜63Dは発電機に接続される送電線の発電機側
し中断器CBが「入」状態であることを判定する回路で
あ″る。64A〜64Dはアンドr−)で各送電線の上
記両端しゃ断器CBが「入」状態の時、出力rlJとな
り、アンド?−)65A〜65Dは各発電機が全て発電
中で、かつアンド?−)64A〜64Dの出力がr31
の時に合理性が成立して出力rlJとなる。
62A to 62D are circuits for determining whether the interrupter CB on the busbar side of the power transmission line connected to each generator is in the "on"state;
63A to 63D are circuits that determine whether the generator-side interrupter CB of the power transmission line connected to the generator is in the "on" state. When the above-mentioned double-end breaker CB is in the "on" state, the output is rlJ, and the AND? -) For 65A to 65D, all generators are generating power and AND? -) Output of 64A to 64D is r31
When , rationality is established and the output is rlJ.

また、アンドゲート66A〜66Dは各発電機が発電中
で、アンドゲートロ4A〜64Dの出力のインヒビット
信号が「l」の時、合理性が成立せず、出力「l」とな
る。アンドグー)67はアンドゲート65A〜65Dの
出力が全てrlJの時、即ち、送電線13A−13Dの
全てに対して合理性が成立する時、出力「l」とな)、
処理回路69にて装置正常時の処理を行なう。
Further, when each of the generators in the AND gates 66A to 66D is generating power and the inhibit signal of the output of the AND gates 4A to 64D is "l", rationality does not hold and the output becomes "l". When the outputs of the AND gates 65A to 65D are all rlJ, that is, when rationality is established for all of the power transmission lines 13A to 13D, the output is "l"),
The processing circuit 69 performs processing when the device is normal.

一方、オアr−) 68はアンドゲート66A〜66D
の出力のいずれかが「l」の時、即ち、送電線13A〜
130のいずれかが合理性が成立しない時、出力rlJ
となシ、処理回路610にて装置不良処理、例えば警報
、表示したシ、安定化演算の出力をロックしたシする。
On the other hand, or r-) 68 is AND gate 66A to 66D
When any of the outputs is “l”, that is, the transmission line 13A
130, when rationality does not hold, the output rlJ
In addition, the processing circuit 610 performs device failure processing, such as warnings, displaying, and locking the output of stabilization calculations.

第7図は監視機能の更に他の実施例を説明する構成図で
あシ、本実施例では電圧、電流情報より求めた電力値が
、電力変換器の出力と等しいと云う合理性に基づいた監
視機能を示す。
FIG. 7 is a configuration diagram illustrating yet another embodiment of the monitoring function. In this embodiment, the monitoring function is based on the rationality that the power value obtained from the voltage and current information is equal to the output of the power converter. Demonstrates monitoring functionality.

第7図において、71A〜71D、72A〜72D及び
73A〜73Dは前記メモリ回路33に入力される各送
電線13A〜130の電力値。
In FIG. 7, 71A to 71D, 72A to 72D, and 73A to 73D represent power values of each power transmission line 13A to 130 input to the memory circuit 33.

電圧値、電流値である。電力値演算回路74A〜74D
は、上記各電圧値、電流値に基づいて、各送電線の電力
値P4 * Pj * P(’ * PDを算出する回
路である。演算判定回路75A〜75Dは、電圧、電流
に基づいて算出した電力値と電力変換器からの各出力P
A v Pg e Pc* PDとが等しいことと判断
する回路であ、り、P’−δ(P(P+δの判定を行な
う。
They are voltage value and current value. Power value calculation circuits 74A to 74D
is a circuit that calculates the power value P4*Pj*P('*PD) of each power transmission line based on each voltage value and current value described above.The calculation judgment circuits 75A to 75D calculate the power value P4*Pj*P('*PD) based on the voltage and current. The calculated power value and each output P from the power converter
This is a circuit that determines that A v Pge Pc* PD is equal, and determines that P'-δ(P(P+δ).

ここでδは装置の誤差である。そして上記判定成立時は
演算判定回路75A〜75Dの出力は「l」となる。ア
ンドff −) 76は演算判定回路75A〜75Dの
出力が全てrlJの時、即ち、送電線13A−130の
全てに対して合理性が成立した時、出力「1」となシ、
処理回路77にて装置正常時の処理を行なう。また上記
判定不成立時は演算判定回路75A〜75Dの出力はr
OJで、ア−ンドグート76の出力はrOJとなシ、イ
ンバータ回路78を経て、処理回路79にて装置不良処
理13例えば警報1表示した夛、安定化演算の出力をロ
ックしたシする。
Here, δ is the error of the device. When the above judgment is established, the output of the calculation judgment circuits 75A to 75D becomes "l". ANDff-) 76 is an output "1" when all the outputs of the calculation judgment circuits 75A to 75D are rlJ, that is, when rationality is established for all of the power transmission lines 13A to 130.
The processing circuit 77 performs processing when the device is normal. Further, when the above judgment is not established, the output of the calculation judgment circuits 75A to 75D is r
At OJ, the output of the Arndgut 76 becomes rOJ, and then passes through the inverter circuit 78 to the processing circuit 79 to perform device failure processing 13, such as displaying an alarm 1, or locking the output of the stabilization calculation.

なお、監視機能については上記実施例に限定されるもの
ではなく、電気回路的な合理性に基づくものであればよ
いことは明らかである。
It should be noted that the monitoring function is not limited to the above-mentioned embodiment, and it is clear that it may be any function as long as it is based on the rationality of electric circuits.

〔発明の効果〕〔Effect of the invention〕

以上説明した如く、本発明によれば制御所に設けた中央
演算装置と各被制御所に設けた各端末装置とこれらの間
を結ぶ伝送系からなる装置不良を、系、統の合理性に基
づいて監視するようにしたので、系統安定化システム全
体として幅広く、精度の高い監視が可能とな)、ハード
規模を改変することなく、信頼性の高い系統安定化装置
を提供できる。
As explained above, according to the present invention, failures in the equipment consisting of the central processing unit installed in the control center, each terminal device installed in each controlled station, and the transmission system connecting these can be corrected based on the rationality of the system and system. Since monitoring is carried out based on the system, it is possible to perform wide-ranging and highly accurate monitoring of the grid stabilization system as a whole), and a highly reliable grid stabilization device can be provided without changing the hardware scale.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明による系統安定化装置の一実施例の構成
図、第2図は端末装置の構成図、第3図は中央演算装置
の構成図、第4図は系統安定化演算に付加する監視機能
を説明する機能図、第5図線第4図の処理内容を示すフ
ローチャート、第6図は監視機能の他の実施例を説明す
る構成図、第7図は監視機能の更に他の実施例を説明す
る構成図、第8図は従来の系統安定化装置の構成図であ
る。 11・・・母線、    12AN12D・・・発電機
、13A〜13F・・・送電線、 14A〜14F・・・変流器、 15A−15F・・・計器用変成器、 16A〜16J・・・しゃ断器。 17A−17D・・・変圧器、 21A〜21F・・・入力変換器。 22.22A、22B・・・電力変換器、23A〜23
!・・・フィルタ、 24A〜24!・・・サンプルホールド回路、25・・
・マルチプレクサ、 26・・・φ変換器、 27・・・P/S変換器、31
A〜31D・・・φ変換器、 32・・・ダイレクト・メモリ・アクセス回路、33・
・・メモリ回路、  34・・・CPU 。 35・−ROM、     36・・・出力回路。
Fig. 1 is a block diagram of an embodiment of the grid stabilization device according to the present invention, Fig. 2 is a block diagram of a terminal device, Fig. 3 is a block diagram of a central processing unit, and Fig. 4 is an addition to the grid stabilization calculation. Fig. 5 is a flowchart showing the processing contents of Fig. 4; Fig. 6 is a block diagram explaining another embodiment of the monitoring function; Fig. 7 is a flowchart showing the processing contents of Fig. 4; FIG. 8 is a block diagram illustrating an embodiment of the present invention, and FIG. 8 is a block diagram of a conventional system stabilizing device. 11... Bus bar, 12AN12D... Generator, 13A-13F... Transmission line, 14A-14F... Current transformer, 15A-15F... Instrument transformer, 16A-16J... Shutoff vessel. 17A-17D...Transformer, 21A-21F...Input converter. 22.22A, 22B...Power converter, 23A-23
! ...Filter, 24A~24! ...sample hold circuit, 25...
・Multiplexer, 26... φ converter, 27... P/S converter, 31
A to 31D...φ converter, 32... Direct memory access circuit, 33.
...Memory circuit, 34...CPU. 35.-ROM, 36... Output circuit.

Claims (4)

【特許請求の範囲】[Claims] (1)電力系統の各所に設置され、電力系統の局所的系
統情報を導入する複数台の端末装置と、自所と端末装置
からの各情報を用い前記電力系統の安定化に必要な処理
を行なう中央演算装置と、自所以外の各端末装置と中央
演算装置との間を接続し情報の伝送を行なう複数の伝送
系とを備えた系統安定化装置において、前記中央演算装
置は自所情報と共に各端末装置からの情報を用いて、系
統の合理性に基づいた監視を行なうことを特徴とする系
統安定化装置。
(1) Multiple terminal devices installed at various locations in the power system that introduce local system information of the power system, and perform processing necessary for stabilizing the power system using each information from the local power system and the terminal devices. In the system stabilization device, the central processing unit is equipped with a central processing unit that transmits information about the local processing unit, and a plurality of transmission systems that connect each terminal device other than the central processing unit and the central processing unit to transmit information. A system stabilizing device characterized in that it performs monitoring based on the rationality of the system using information from each terminal device.
(2)系統の合理性は、入力電気量と出力電気量との差
が所定誤差以内であることをもって判定することを特徴
とする特許請求の範囲第1項記載の系統安定化装置。
(2) The system stabilizing device according to claim 1, wherein the rationality of the system is determined based on whether the difference between the input amount of electricity and the output amount of electricity is within a predetermined error.
(3)系統の合理性は、発電機が出力中であることと、
発電機に接続された送電線の各しゃ断器が「入」状態に
あることをもって判定することを特徴とする特許請求の
範囲第1項記載の系統安定化装置。
(3) The rationality of the system is that the generator is outputting power,
2. The system stabilizing device according to claim 1, wherein the determination is made based on whether each breaker of a power transmission line connected to the generator is in an "on" state.
(4)系統の合理性は、発電機の出力電力と変換器を介
して計測した結果との差が所定誤差以内であることをも
って判定することを特徴とする特許請求の範囲第1項記
載の系統安定化装置。
(4) The rationality of the system is determined based on whether the difference between the output power of the generator and the result measured via the converter is within a predetermined error. Grid stabilizer.
JP60211630A 1985-09-25 1985-09-25 System stabilizer Pending JPS6271442A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60211630A JPS6271442A (en) 1985-09-25 1985-09-25 System stabilizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60211630A JPS6271442A (en) 1985-09-25 1985-09-25 System stabilizer

Publications (1)

Publication Number Publication Date
JPS6271442A true JPS6271442A (en) 1987-04-02

Family

ID=16608954

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60211630A Pending JPS6271442A (en) 1985-09-25 1985-09-25 System stabilizer

Country Status (1)

Country Link
JP (1) JPS6271442A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10512599B2 (en) 2005-09-12 2019-12-24 Givaudan Sa Organic compounds

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5644355A (en) * 1979-09-18 1981-04-23 Tokyo Shibaura Electric Co Controller for load in power distribution system
JPS6077634A (en) * 1983-10-04 1985-05-02 株式会社東芝 Composite generating plant controller

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5644355A (en) * 1979-09-18 1981-04-23 Tokyo Shibaura Electric Co Controller for load in power distribution system
JPS6077634A (en) * 1983-10-04 1985-05-02 株式会社東芝 Composite generating plant controller

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10512599B2 (en) 2005-09-12 2019-12-24 Givaudan Sa Organic compounds

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