JPS6271321A - Comparator - Google Patents

Abstract

PURPOSE:To obtain a MOS comparator suitable for circuit integration with low power consumption by sampling and holding two input voltages in advance at input terminals of a clocked inverter, activating then the inverter, amplifying the difference voltage through a positive feedback loop and outputting the result of comparison. CONSTITUTION:With switches SW1, SW2 turned on, a proper bias voltage VB is impressed and high impedance nodes Q1, Q2 are biased to a voltage VB. Then switches SWX, SWY are turned on to apply input voltages VX, VY respectively, the nodes Q1, Q2 change from the voltage VB to the voltages VX, VY. Further, a clock phi is given to MOS gates 12, 13, which are turned on and the inverse of clock phi is fed to MOS gates 14, 15 to turn on them, the clocked inverters 10, 11 are activated, the positive feedback loop is operated depending on the quantity of the voltage VX, VY to confirm the latch state. When the result is VX>VY, the level of the node Q1 goes to low and the level of the node Q2 goes to high, and when VX<VY, the level of the node Q1 goes to high and that of the node Q2 goes to low. That is, the result of the comparison between the voltages VX, VY is outputted to the node Q1 or Q2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a comparator, and more particularly to a MOS comparator with low power consumption and suitable for integration.

[Background of the invention]

Conventional MOS comparators have been of differential input type or chopper type. However, the differential input type has a constant current source, and the chopper type has a through-current of the inverter (from Vno to Vss) flowing during the auto-zero period, so it cannot be said that the power consumption is low, and there is still room for improvement. was. For differential input type comparators, see, for example, the National Conference of the Telecommunications Division of the Institute of Electronics and Communication Engineers, 1981, 1-94. S
59/10. Regarding the chopper type comparator,
ISSCC79 Digest of Technical Papers, p126-127.
1979/2 etc. are cited as known examples.

[Purpose of the invention]

An object of the present invention is to provide a MOS comparator with low power consumption and suitable for integration.6 [Summary of the Invention] In order to achieve the above object, the present invention uses a clocked inverter pair to create a differential comparator. The aim is to reduce power consumption by eliminating the steady current bus. The two input voltages are sampled and held in advance at the input end of a clocked inverter, the inverter is first activated, the difference voltage between these is amplified through a positive feedback loop, and a comparison result is output.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail using Examples.

FIG. 1(a) is an example of a circuit of a comparator of the present invention constructed using a clocked inverter.

The input and output of the two clocked CMOS inverters 10 and 11 are connected together to form a latch, and the bias voltage v8 and the input voltage Vx are connected to the input of the inverter 10 by the switch S.
Wz, SWx are applied to the input of the inverter 11, and the bias voltage VB and the input voltage Vy are applied to the input of the inverter 11.
are supplied via switches SWz and SWy, respectively.

The comparator operates according to the timing chart shown in FIG. 1(b). First, switch SW1.

SWz is turned on and an appropriate bias voltage Va is applied. At this time, high impedance node Q1. QZ is the 6th switch SWx biased to 7 ports.

SWv is turned on to supply input voltages V x t Y v, respectively. At this time, nodes Qx and Qz are from VB to VY.

Changes to Vx. Furthermore, with clock φ, MOS gate 12
．． 13 is turned on, and the MOS gates 14,
When the clocked inverter 10.15 is turned on, the clocked inverter 10.11 is activated, and a positive feedback loop is activated depending on the magnitude of Vx and Vv (7), thereby determining the state of the latch. This result V
x) If V v, Qz is Low, QZ is High
If V x < V Y, QL becomes 11high and Qz becomes Low level. That is, V x .

The result of comparing the magnitude of Vv is output to Ql or Qz.

VB may be set to the same voltage as Vx or VY, or the cycle of applying VB may be omitted, and after directly inputting Vx+Vy, the clocked inverter may be driven to establish the latch. Comparison output is Pl, pz or p
It can also be obtained with H, P4. Since this comparator does not have a steady current bus and all ft currents are transient currents for charging and discharging, power consumption can be kept low.

This is suitable for applications in which a large number of comparators are arranged, such as in a parallel A/D converter.

FIG. 2(a) is an example in which the comparator of the present invention is constructed from other circuits.

The input and output of the CMOS inverters 20 and 21 are connected to each other to form a latch configuration, and the power supply terminals 22 and 23 are connected to clocks φ and φ.
A clocked MOS switch 24 controlled on and off by
．． Power supplies V ss and V no can be supplied through the terminals 25 and 25, respectively. Bias voltage VB or input voltage Vx is applied to the input of inverter 20 via switches SWz and S Wx, respectively, and bias voltage VB or input voltage Vv is applied to the input of inverter 21 via switches SW2. They are respectively applied via SWv.

The comparator operates according to the timing chart shown in FIG. 2(b). First, switch SWs.

Turn on S Wz, S Ws, and S W4 and connect the input/output terminals of the inverter 20゜21, Ql, and Qt power supply terminals 22.2.
0th order switch SWx which supplies bias voltage Va to 3
.

Turn on SWv and apply input voltages Vx and Qz to Qt, respectively.
Supply Vv. Furthermore, when the MOS switch 24.25 is turned on by the clocks φ and φ and the power supply voltage Voo+Vss is supplied to the inverter 20.21, a positive feedback loop is activated depending on the magnitude of VX and Vy, and the state of the latch is determined. do. As a result, if Vx>V Y, Ql is Lo
w, Qz is at jliHh level.

Reverse 4: If Vx<Vv, Ql is High, Ql is Lo
It becomes wL/Bell. In other words, the comparison result of VX and VY is Q
It is output to l or Ql.

Va may be the same voltage as Vx or VY. VB
SWI and SW2 for applying can be omitted. Also, the cycle of applying VB is omitted, and Vx+V
After inputting v, clocked MOS switch 24.25
The latch can also be established by turning on the inverter 20.21 and activating the inverter 20.21. Further, the Clot MOS switches 24 and 25 may be provided independently for each inverter 20 and 21. In this case, the power supply terminals of the inverters 20 and 21 will be independently connected to Vss or Voo. In either case, the power flowing through this comparator is a transient current for charging and discharging, so that low power consumption is achieved.

FIG. 3 shows an embodiment in which the comparator of the present invention is used in a parallel A/D converter.

The comparator 3o is the comparator shown in FIG. 1 or 2, and by using 2 degrees of these, the input terminal V i
n and 2n reference voltages Vri (i=1.2.2')
Compare at the same time. The comparison result of each comparator is converted into a predetermined n-bit digital value Dout by the encoder 31.
get. Since the comparator 30 has low power consumption, it can be applied to such a parallel type A/D converter, and even if 256 8-bit comparators are integrated, power consumption will not be a problem at all.

FIG. 4 shows an example of a configuration in which the comparator of the present invention is used in combination with a digital logic circuit.

The outputs of the comparator 45 of the invention, consisting of a clocked inverter 40.41, are PL+P11PxrP2, which are respectively connected to the input terminals of a D-type flip-flop 42, D, and the input terminals d, d of a digital logic circuit 43.44. Entered directly.

When the clocked inverters 40 and 41 are activated by the clock φ, positive feedback is applied to the two inverters 40 and 41, and the output P 11 P t t P xH
P2 is determined to be High or Low level. This is a sufficient level to drive normal operation. The input terminals Q and Q of the comparator 45 are connected to the digital logic circuit 4 in the subsequent stage.
Since 2, 43, and 44 are not connected as a load, load conditions are reduced in comparator design, and performance design such as accuracy and speed is facilitated.

FIG. 5 shows an embodiment in which an RS flip-flop is connected to the comparator of the present invention.

An RS flip-flop 46 consisting of a NAND gate is connected to the output ends PL and Pl of the comparator 45, and an RS flip-flop 47 consisting of a NOR gate is connected to the output ends Px and Pz. Pz.

When the inverters 40 and 41 are activated by the clocks φ and φ, Pl outputs different voltage levels, so the RS flip-flop is also determined accordingly, and Qz, Q
The primary clock φ, which provides a predetermined output at time t, is inverted and the MOS gates 50, 51, 51 of the inverter 40°41
When 52 and 53 are all turned off, either Pl and PI maintain their previous states or both become High level (Voo). In the latter case, both inputs of the NAND gate constituting the RS flip-flop 46 are high.
i g h level, but the state remains unchanged and the previous state is maintained. Therefore, the output of the RS flip-flop 46 always stably outputs the comparison result of the comparator.

Ha/ That is, there is no uncertain state in Ql,01.

Similarly, stable output can be obtained from the RS flip-flop 47 connected to Pl and Pz.

As described above, the comparator of the present invention in which the RS flip-flop is connected to the output terminal can stably output comparison results, has a simple circuit configuration, and is suitable for integration. Additionally, there is no path through which steady current flows, allowing for significantly lower power consumption than conventional differential input types or chopper types.

FIG. 6 shows an embodiment in which a MOS gate is added to the circuit configuration of the comparator 45 (FIGS. 4 and 5) of the present invention to improve the operating speed. PMO360.

61 and NMO362, 63 are connected in parallel,
The circuit is configured to perform on/off control using clocks φ and φ. When two input voltages are applied to Q and Q in advance,
φ is set to Low, and φ is set to )Light level. At this time, PMO 360 and 61 are turned on and PMO is activated.

The Px point is biased to the voltage Vt1n, and the NMO562,
63 turns on, the Px and Pl points are at the voltage Vss.
biased towards. This bias speed is PMO360.

61 and NMOs 362 and 63 can be turned on sharply by the clocks φ and φ, so the speed is sufficiently high.

Figure 7 shows the MOS gate controller 0 of the comparator circuit in Figure 6.
This is another embodiment in which the control means of 63 to 63 are changed. PMOS
As the gate voltage of the gates 60 and 61, the voltage at the point P2°22 is directly applied, and as the gate voltage of the NMOS gates 62 and 63, the voltage at the points Pi and Pt is applied.

When two input voltages are previously applied to Q, the pHPI is NHO362,63, regardless of the previous comparison result.
There is enough voltage left to turn on P2. P2
There remains sufficient voltage to turn on the PMOs 860 and 61. As a result, NHO362 and 63 are turned on and P2.
By changing the P2 point to the Vss side, PMO361
, 62 are each turned on more strongly, bringing the points Pt and Pt closer to the Voo side. This positive feedback quickly performs an initial reset operation, and initial voltages of each part are set.

FIG. 8 shows an embodiment of the comparator of the present invention configured in the comparator circuit of FIG. 6, in which an NMOS comparator 81 is connected between P1+Pz.

These are controlled on and off by the clocks φ and φ, and are turned off during the initial reset period when input voltage is applied, and turned on during the subsequent comparison period to conduct between Pi and PZ and between Pt and Pt. It serves to speed up the operation of the positive feedback loop composed of inverters 10 and 11. Also the output lol
It also plays the role of making the low level of 9W a sufficiently low voltage. Instead of NMOS gates 80 and 81, PMO
An S gate may also be used, or NHO2 and PMO5 may be used simultaneously.

The output is P z + P 2. It can also be extracted from a point.

FIG. 9 shows an embodiment of the comparator of the present invention realized by another circuit configuration. Clocked inverter 10.11 (71NMOS gate 8o) in FIG.

Omitting 81, pi, P2. NMOS gate 62.6 for initial voltage setting by short-circuiting between PI and Pz.
3 is abolished, and the vN line 9o is connected to the PMOS gate 91 and N
The MOS gate 92 can be used to switch between voltage Van (high potential) and voltage Va+vn (low potential).

During the initial reset period when input voltages vX, Vv or Q, Q are applied, clock φ0 is Low and clock φ is Low.
w, clock φ is at Hl g h level, Ps, Pt
The point and the VN line 90 are set to the power supply voltage DD.

Also, Q and Q supplied by VXIVY are φ, and φ is NMOS.
The gates 12 and 13 and the PMOS gates 14 and 15 are turned off, and the voltages of VX and VY are set while being isolated from others.

Next, in the comparison period, φ0. φ and φ are respectively High,
High, Low level, VN line 9
0 is the power supply voltage VONO! J, PMOS gate 6o.

61 Hao 7, PMOS gates 14, 15 and NM
OS gates 12 and 13 are turned on, and the input voltage difference V x
” A positive feedback loop in which V v is rapidly amplified is activated, and the comparison result is output to W, W. Although this comparator only has a transient current flowing during the initial reset period and a short period of the comparison period, , the power consumption can be made sufficiently small, and the positive feedback operation makes it possible to achieve a high-speed comparison operation.

FIG. 10 is an example of a circuit in which the comparator of the present invention shown in FIG. 9 is partially modified. From the clocks φ and φ in FIG. 9, the voltage VN90. and a voltage VM obtained by inverting VN90 using a CMOS inverter 100. During the initial reset period, vN90 is the PMOS gate 91
Since it is biased to vDD and becomes High level, PMOS gates 14 and 15 are turned off and VM is Low.
Since it is at W level, NMOS gates 12 and 13 are also turned off. During the comparison period, since Vs90 is at a low level, the PMOS gate 14.15 is turned on, and since VM is at a high level, the NMOS gate 12.13 is turned on and a positive feedback loop is activated, and the comparison operation of Vx and Vy is performed. It will be done.

Note that at this time, φ0 is at the IIhigh level, and the PMOS gates 60 and 61 for initial voltage setting are off.

FIG. 11 shows another circuit example in which the comparator of the present invention shown in FIG. 9 is partially modified. PMOS gate 60 in FIG.
．． 61 and set it to a PMOS gate instead.

This initial potential is set to the power supply voltage VOO by the four M and OS gates M1 to M4.

The on/off states of the four MOS gates M1 to M4 are determined by the levels of the input voltages Vx and Vy, but at least 2
Since the two MOS gates are normally on, the initial voltage can be set.

The comparator of the present invention has low power consumption, a simple circuit configuration, and is suitable for integration.

〔Effect of the invention〕

According to the present invention, since the power consumption of the comparator can be reduced, it is highly effective not only in terms of economy but also in improving functionality and performance, such as the ability to integrate a large number of comparators.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the circuit configuration of the comparator of the present invention and its time chart, FIG. 2 is a diagram showing another circuit configuration of the comparator of the present invention and its time chart, and FIG. 3 is a diagram showing the use of the comparator of the present invention. Figure 4 shows an example in which the comparator of the present invention is connected to a digital logic circuit, and Figure 5 shows an example in which the comparator of the present invention and a digital logic circuit are connected.
FIG. 3 is a circuit configuration diagram in an example in which flip-flops are connected. 6, 7, 8, 9, and 10. FIG. 11 is a diagram showing another example of the circuit configuration of the comparator of the present invention. 10.11...Clocked CMOS inverter, 12
゜13, x4, 1s...MOS gate, 20.21.
・・CMOS inverter, 22. 23 ・・Power supply end, 2
4゜25...Clocked MOS switch, 40.41
. . . Clocked CMOS inverter, 42 . . . D type flip-flop, 43, 44 . . . Digital logic circuit. 45... Comparator, 46.47... RS flip flop, 50, 51, 52.53-MOS gate,
60, 61, 62, 63...MOS gate, 80,
81-NMOS gate, 90-...voltage end VN, 91
・PMOS gate, 92-NMOS gate, 100 ・
...cMos゛Inverter, 101...PMOS
Gate.

Claims (1)

[Claims] 1. A first clocked inverter, a second clocked inverter, and an input of the first clocked inverter and an input of the second clocked inverter connected to each other. means for inputting at least one voltage to the output; and means for inputting at least one voltage to the output of the first clocked inverter and the input of the second clocked inverter connected to each other; A comparator featuring: 2. In the comparator according to claim 1, the first and second clocked inverters are replaced by first and second MOS transistors having the same polarity, and third and fourth MOS transistors having opposite polarity. MOS transistors are connected in series in this order, the first and fourth MOS gates are connected to each other and used as input terminals, clocks with opposite phases are supplied to the second and third MOS gates, and the second and fourth MOS gates are connected in series. 2. The connection end of the third MOS gate is used as the output end, and the connection end of the first and second MOS gates or the connection end of the third and fourth MOS gates is used as the other output end. comparator.