JPH01188121A - Automatically stabilized and latched differential comparator with single clock - Google Patents

Abstract

PURPOSE: To stabilize an operation by executing the coupling between an output of a differential amplifier and an output of a divergence circuit at the gate of a load transistor of the divergence circuit. CONSTITUTION: This device is provided with the differential amplifier which operates by an extremely high frequency and to which a signal to compare is inputted to an input terminal, and the divergence circuit existing in two arms symmetrical with respect to the output of the amplifier. The divergence circuit is provided with three serially connected transistors, namely, a feedback transistor, an insulated transistor and a voltage level translator, to individual arms. Then coupling between such a latched differential comparator, namely the output part of the differential amplifier, as obtained by the output of a comparator at the output terminal of a voltage level translator and the divergence circuit is executed at the gate of the load transistor of the divergence circuit. Thereby, operation is stabilized.

Description

DETAILED DESCRIPTION OF THE INVENTION (Background of the Invention) The present invention provides a preamplifier (preamplifier) with one clock.
-amplification) automatically stabilized and latched electronic circuits. This comparator is designed to operate at very high speeds (up to several gigahertz microwaves) and its single clock, automatically regulated quiescent voltage and architecture The comparator is such that it does not introduce measurement errors or instability and is largely unaffected by technological changes in transistor manufacturing.

This comparator is designed to be fabricated in an integrated circuit using an m-v group material such as GaAs (gallium arsenide), but of course this comparator may be implemented without departing from the scope of the present invention. Instead, it can be manufactured from silicon, but only at a slower operating speed.

A differential latched comparator uses a mechanism called positive feedback. That is, the voltage difference between the voltages appears again at the output after amplification (measurement phase). The three signals are then reinjected into the input (divergent phase). Looping the output back to human power means amplifying the voltage difference.

This type of construction with a balanced reset circuit is of great value since it allows the production of comparators with very low flip-over times.

FIG. 1 shows an example of a circuit diagram of a latched comparator with stacked differential stages according to the prior art.

The human input signals E1 and E2 addressed to the gates of transistors T6 and T7, respectively, are connected to the transistor T8.
and the output signals s1 and S input to the gate of T9
2 and the respective drains of transistors T6 and T7. In this architecture, two complementary clocks old and H2 are required whose pulses are applied to the gates of transistors T2 and T3, respectively.

This comparator has two stacked differential stages, which are internal stages T2+T4+T5+T8+T
9 and external stages T3+T6+T7+T8+T9. In this configuration, the transition from the measurement phase to the diverging phase is achieved by switching the current of the external differential stage from the internal differential stage using two clocks and transistors T2 and T3.
At this point, divergence begins. Voltage level translator (TIO, ot, D2°D3. Tl2) and (
Tll, D4. D5. D6. T13) is essential to compensate for the static level difference that exists between human power and output.

The main disadvantages associated with this configuration are:

1 non-overlapping complementary clocks I11 and H2
is necessary.

Lack of sensitivity due to charge injection during switching operations.

- There is no static level of stability to address technical deficiencies, as it is not necessarily verified as follows.

ITI ” IT4 + IT5 - Instability of the output signal due to switching of current as it flows from the external stage to the internal stage and vice versa.

The comparator according to the invention makes it possible to overcome these drawbacks by:

- Compensation of technical variations by stabilizing the voltage - Operation with a single clock - High sensitivity by eliminating the transfer of current between the internal and external bridges The invention is characterized by a differential amplifier in manual operation, a divergent circuit in the output The coupling of the differential amplifier to the divergent circuit is achieved by two voltage followers that isolate the amplifier from the divergent circuit, although using circuit elements such as a voltage level translator and a voltage level translator. The quiescent voltage at the output of the amplifier can then be applied by an automatic control loop. The coupling between the differential amplifier and the divergent circuit is achieved on the gates of the load transistors of this circuit, which are themselves mounted in series and individually operated either in resistive mode or in saturation mode. It is equipped with an isolation transistor that operates at .

ΩII for Fish More precisely, a differential amplifier operating at a very high frequency and having at its input terminals the signals to be compared, having a diverging circuit in two arms symmetrical with respect to the output of the amplifier, as described above. The divergence circuit has three series connected transistors for each arm, namely a feedback transistor, an isolation transistor and a voltage level translator, such that the output of the comparator is available at the output terminal of the voltage level translator. It concerns a differential comparator, ie a latched differential comparator, in which the coupling between the output of the differential amplifier and the divergent circuit is at the gate of the load transistor of the divergent circuit.

The differential comparator according to the present invention shown in FIG. 2 has the following element groups.

A preamplifier circuit receives input signals from single power sections El and E2. It is formed from a cascaded amplifier of known type in a group with transistors 14 to 20.

Automatic control loop T21, which allows stabilization of the quiescent voltage at the outputs Sl and S2 of the device amplifier, from old 06. T2° is formed by coupling transistors T23 and T24, isolation transistors T25 and T26 and differential feedback transistors T27, T2O and T2O.

and a voltage level translator T30°D
8. D9. T:12 and Tel, 010,
Divergent circuit complemented by Dll, T:13.

Transistors T34 and T35 for resetting the balance of the device, these are mounted in parallel with the feedback transistors T27 and T2O, respectively, and a single clock H signal is applied to the gates of these transistors T34 and T35. Ru.

- the output of the comparator is obtained at the drain of transistor 33 of the voltage level translator and is simultaneously looped to the gate of feedback transistor T27, and the output 02 obtained at the drain of transistor 32 is looped to the gate of 728;

Although the device is placed between two analog voltages VDD and VSS+, these two voltages are not both shown in FIG. 2 simply to avoid cluttering the diagram.

The number of diodes is 6 for this automatic control loop and 2 for the individual voltage level translators, but this number does not limit the scope of the invention, which uses GaAs (gallium arsenide). technology, but may vary depending on the technology implemented. Instead of these diodes, it is technically possible to use translators or resistors without diodes.

Coupling transistor and isolation transistor T
The intermediate outputs between T23 and T25, T24 and T26 are called SI8 and SIB, respectively, and the intermediate outputs applied to voltage level translators T30 and T3I are called SA and SE, respectively.

All transistors used in this assembly are of the normally-on type, ie, conductive unless a voltage is applied to their gates.

Briefly, this comparator works as follows.

The front circuit amplifies the voltage difference between the two human powers El and E2. Output part S of preamplification differential stage! The signals present at and Sl are transmitted to the divergent stage by the divergent stage's load transistors T23 and T24 using the original coupling mode. Clock H
When T27 and T2O are at a low logic level, T27 and T2O are on, T34 and Ta2 are off, and divergence is initiated, but the reason is that the output signal is connected to the human part of the divergence stage (the gates of T27 and T2O). This is because it is transmitted. When SA and SB diverge, the circuit clocks H
is brought to a high logic level to return to equilibrium, allowing the divergence cycle to begin again.

More specifically, the voltage at El must be compared to the voltage at El. The voltage difference V(El)-V(El) is then amplified by a coefficient G, which is the gain of the amplifier. Therefore, we obtain the following equation.

V(Sl) −V(52) =G−(V(El)−V(
El)) Two operating phases must then be considered.

One phase 1: Clock H is in a high logic state. Transistors r34 and Ta2 are on. Therefore 'r27
and T2O are shorted. Insulated transistor'2
5 and T2O do not saturate because their gate widths are between the width of the gate of current source T29 and the width of the gates of coupling transistors T23 and T24.

As a non-resistive example, the gate width for T23 and T24 is 5 microns, and the gate width for T25 and T2O is 7.5 microns.
Specifically, the gate width of T29 is 10 microns. This is because the intensity applied by a current source (a transistor with zero gate-source voltage) is proportional to the transistor dimensions, and 2x7.5 = 15>
6, it is not possible to saturate both T25 and T2O at the same time. Therefore T25 and T2
O operates in resistance mode.

As a result, the coupling transistor, isolation transistor and balanced reset transistor T2: ] +T
The two symmetric sets formed by 25 +T34 and T24 +T26 +T35 have two followers/
Form a shifter circuit. This is because the gate-source voltage of T34 is equal to that of Ta2, and the current in the left arm is equal to the current in the right arm.

The gate-to-source voltages of T23 and T24 are therefore equal. Therefore, the difference VSI-VS2 is SIA and SIB
The value will be between .

Since T25 and T2O are the same and one and the same current is conducting and in resistance mode, the drain-source voltages of these two transistors are equal. Therefore, we get the following formula.

V(SA) −V(SE) =V(St) −V(Sl
)=G-(V(El)-V(El)) From this equation, the preamplification is determined by the fact that the divergent phase can start.

One Phase 2: In the divergent phase, clock H is at a low logic level. T34 and Ta2 are off and therefore no longer participate in the operation of the circuit. T27 and T2O are therefore no longer shorted. Here we are dealing with a standard type latched differential circuit. Voltage difference V(SA)-V
(SO) is reinjected into the gate of T27 by two voltage level translators. Next, there is a divergence between the voltage to S and the voltage to SB. This is an extremely rapid phenomenon. In this case, one of the two transistors T25 and T2O operates in saturation mode. Simply put, a small voltage difference between El and El results in a large voltage difference between the output voltage port and 02.

The originality of this architecture is as follows.

One divergent load transistor T23 and T24
coupling mode between the preamplification stage and the divergence stage.

- the presence of isolation transistors T25 and T2O, which can sometimes operate in resistance mode and sometimes in saturation mode.

Its role is explained below.

- An automatic control loop made possible by the isolation of the preamplifier through coupling mode and further stabilizing the quiescent voltage.

One single clock, stability and single clock are the advantages generated by coupling mode.

Regarding the stabilization of all quiescent voltages, the automatic control loops T21, DI to D6. The role of T22 is T1
4 and by the coupling mode used between the preamplifier circuit and the divergent state to stabilize the quiescent voltages of St and Sl. In the measurement phase (clock in top state) elements T24, T26.

T35 as well as T23, T25 and T34 form two voltage followers, to which the quiescent voltages of SA and SD are applied. Furthermore, elements T30, D9. T
32, T31, 010°Dll, T33 also form voltage followers and the quiescent levels of old and 02 are also applied. In short, the automatic control loop described above stabilizes all of the circuit's quiescent voltages. 1 single clock H
-Although it is easier than generating two complementary clocks-
The necessity of transitioning from the measurement phase to the diverging phase ensures the presence of isolation transistors T25 and T26.

In standard latched comparators, complementary clocks are used to make it possible to alternately send the voltage to be measured (measuring phase) and the voltage obtained at the differential output (divergent phase) to the human power section. Needed.

These two phases can be achieved by a single clock. When clock H is in a low logic state, the comparator is in divergent phase. When the clock is in a high logic state, the difference V
(SA)-V(SB) is G(V(El)-V(E2
) )be equivalent to. In the divergent phase, the human forces El and 1 and 2 no longer have any influence on the direction of divergence, if the human signal can no longer force the comparator to change its decision. Not worth it. This is made possible by isolation transistors T25 and T26. This operational step will be considered below.

Step 1: Assume that V(Sl) - V(Sl) is small. Then, V(SA)-V(SB) is also small in the measurement phase.

Step 2: Divergence phase is initiated. Voltages SA and SB diverge significantly from their quiescent level.

The sign of V(El)−V(ε2) is positive, while V(S
l) >V (Sl)V(SA) >V(5B)
It is assumed that V (SA) increases while V (SB) decreases in the Sarani divergence phase.

Based on this assumption, the voltage difference between Sl and SB will increase. This tends to increase the current flowing through T23. However, this current is
Limited by T25 entering saturation mode. At that time,
Voltage S2 is applied to these two nodes (nodes).
Since is connected by a current source, it no longer has any effect on V(SO).

As for the right arm, the voltage between Sl and SA decreases and T26 goes into resistance mode.

- Step 3: When a sudden change occurs at the input terminal, there is a fact that the sign of V(Sl) −V(Sl) changes in the divergent phase (v(sl) < v(Sl)). This allows the S
l no longer affects SR and therefore, due to the differential nature of the circuit, V(Sl) - V(Sl) is no longer V(Sl) - V(Sl)
It has long been known that the sign of (SA) -V (SB) is not affected.

Simply put, once the diverging phase is initiated, the human input signal can no longer cause the system to change its decision before returning to the measuring phase.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a latched comparator according to the prior art mentioned above. FIG. 2 is a circuit diagram of an automatically stabilized and latched comparator with a single clock according to the present invention.

Claims (8)

[Claims] (1) It has a differential amplifier to which a signal to be compared is applied to the input section, and a divergence circuit that exists in two arms that are symmetrical with respect to the output section of the amplifier. Each comparator has three series-mounted transistors, namely a feedback transistor, an isolation transistor and a load transistor, and one voltage level transistor;
a latched difference obtained at the output of the translator and operating at a high frequency, characterized in that the coupling between the output of the differential amplifier and the output of the divergent circuit is made at the gate of the load transistor of the divergent circuit; Dynamic comparator. (2) In each arm of the diverging circuit, an insulating transistor whose gate width is smaller than the gate width of the transistor that is the current source of the diverging circuit but larger than the gate width of the load transistor of the diverging circuit, thus providing a resistive mode and A latched differential comparator according to claim 1, characterized in that it operates in one of the saturation modes. 3. A latched differential comparator as claimed in claim 1, characterized in that the differential amplifier is isolated from highly amplified signals present in the diverging circuit by means of an isolation transistor and a load transistor. (4) Claim characterized in that the differential amplifier is isolated from the divergent circuit and its output voltage is stabilized by an automatic control loop that applies a quiescent voltage to the gate of the transistor that is the current source of the amplifier. The latched differential comparator according to item (3). (5) One single clock signal can generate two balanced resets.
Claim 1, characterized in that the voltage is applied to the gates of the transistors, each of these two transistors being mounted in parallel with one of the feedback transistors of the divergent circuit.
1) The latched differential comparator as described. (6) A latched differential comparator as claimed in claim (1), characterized in that all transistors of the circuit are of the normally-on type. (7) Claim characterized in that the integrated circuit is produced from Group III-V, such as GaAs (gallium arsenide).
1) The latched differential comparator as described. (8) At least one produced according to claim (1)
An analog-to-digital converter comprising two latched differential comparators.