JPS6270936A - Modulo-3 residue generator - Google Patents

Abstract

PURPOSE:To reduce the hardware quantity by obtaining the new modulo-3 data from the modulo-3 data obtained with odd, even and odd bits as well as even, odd and even bits respectively. CONSTITUTION:A modules 2-5 deliver the modulo 3 residue to bits Y10 and Y12 and its logic NOT to a bit Y11 when the even power of two weight bits are applied to bits X10 and X12 with the odd power weight bit applied to the bit X11 respectively. While the modulo 3 residue is supplied to bits Y10 and Y12 with its logic NOT delivered to the bit Y11 respectively when the odd power weight bits applied to the bits X10 and X12 with the even power weight bit applied to the bit X11 respectively. Then B modules 6-8 receive the modulo residues from bits X20 and X22 and X24 and X26 and apply the logic NOT of these bits X20, X22, X4 and X26 to bits X21, X23, X25 and X27 respectively. Then the modulo residues are delivered to bits Y20 and Y22 with its logic NOT delivered to bits Y21 and Y22. In such a constitution, the hardware quantity can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a modulo 3'MJ residual generator for error detection in an information processing device.

[Conventional technology]

Generally, when processing round data in an information processing device, the unprocessed data is divided by 3, the remainder is used to generate a modulo 3 remainder, and then the modulo 3 remainder of the processed data is fully predicted. At the same time, a modulo 3 remainder is generated from the processed data, and when the predicted modulo o3 remainder is obtained and the t modulo 3 remainders do not match, it is determined that there is an error.

Conventionally, this type of modulo 3 remainder generator uses a memory, stores the modulo 3 remainder of an existing value at each memory address, and inputs data into the address of the existing memory. A method that obtains a desired modulo 3 remainder, or, as disclosed in Japanese Patent Laid-Open No. 54-75958, a data bit string with a weight of several pairs of bits whose weights are even powers of 2 and bits whose weights are odd powers of 2. divide,
After generating each modulo 33111 remainder, there is a method to generate the value modulo 3 remainder when adding them together.

[Problem that the invention seeks to solve]

The conventional modulo-3 remainder generator described above uses memory, and as the number of bits of data to be processed increases, the required memory capacity increases exponentially. is far beyond practicality, and for those that use a logic circuit, as the number of data bits increases, the hardware required to generate the modulo 3 remainder increases proportionally.
If the number of bits is large, the disadvantage is that it becomes uneconomical.

Means for Solving Problem C] In order to solve all of these drawbacks, the present invention uses modulo 3 data obtained for odd, even, and odd bits, and modulo 3 data obtained for even, odd, and even bits. , to obtain new Sojuro 3 data.

[For production] Modulo 3 data is obtained in focused values.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows a modulo 3 remainder generator according to an embodiment of the present invention. The present modulo-3 remainder generator is capable of generating a modulo-3 remainder of a 12-bit unsigned binary number. In FIG. 1, the binary number indicated by symbol 1 represents a 12-bit unsigned binary integer, and data of each bit of weights 2 to 2 is input to lines 11 to 22. In A modules 2 to 5, the weight bits of even powers of 2 are Xro, X
12 and the weight bit of an odd power is input to X11, the sum of all input data is modulo 3.
The remainders k Yso and Yxz are each output with a weight of 2.1, and the odd power bits of weight f Xlo and X are output.
When inputting lz to even power weight bit ftXu,
Modulo 3 remainder tYi of the sum of all input data
o.

Y1□ has a function that outputs each with a weight of 1.2, and Y
o and Yls each have the function of outputting the logical negation of Yr or Y1z, and B module 6.7.8 has sX2G, Xs2 and Xs.
< , Receive all modulo 3 data with weight 2.1 from Xza, Xxx + Xxs + Xxs + X
For zx, respectively, Xzo + Xzx +X*a,
-f is input by inputting the logical negation of Xs.
c, the result of the 7-modulo 3 addition of the two modulo 3 data is output to Y2O and Yet with a weight of 2.1, respectively, and the logical negation of Y20 and Y22 is output to Y21. , the A module is like the pore in Figure 2,
On the other hand, the B module can be easily configured as shown in FIG.

See the example below! I will explain all the works by l1wJ. here symbol 1
Consider the case where the binary number is rlololollooolj. Each bit of the binary number with the symbol 1 is input to the A modules 2-5 via lines 11-22.

A module 5 is binary number r1010000UUf)tl
The modulo 3 remainder of OJ is "01" which is output to 7 YH and YIO, and at the same time, its logical negation is output to Yls and Yll. Similarly, A module 3 is also a binary number r ooo.

It outputs the modulo 3 remainder r00J of 00110000 J and its logical negation y&:Ylo -Yxs. A module 4 is binary number ro000100000
"10" with modulo 3 remainder of 00J is Y2O, Y
Similarly, A module 2 also outputs the binary number r oo
ooooo.

000001 Outputs the modulo 3 remainder "01" of J and its logical negation t-Y1o-Yls. Next, the B module 7 outputs modulo 3 data and its logical negation data via lines 61-64, and lines 51-5.
4, modulo 3 data and its logical negation data rloolJ ', two modulo I: +3
The result of modulo addition of data r01J and rlOJ is
00" to Y2O, Y22, Yll, Y23
outputs ``11'', which is the logical negation. Similarly, the B module 6 also receives two modulo 3 data and its logical negation f'o101 via lines 41 to 44 and lines 31 to 34.
J, rolloJ, modulo 3 data roO
“01” is the result of modulo addition of J and roll
is output to Y2O and Y22, and its logical negation, rlOJ, is output to yit and yzs. Finally, the B module 8 passes through the lines 81-84°71-74,
Module 6, gamma engineering 92 modulo 3 data and its logical negation ro101J.

Receive rolloJ, modulo 3 data roo''
.

“Ol” modulo 3 addition result r01J’! (It is output as the modulo 3 remainder of the binary number r101010110001J to YI2, Y+o, and the line 91.92J: can be obtained as the desired value.

With the above configuration, if the number of bits is a multiple of 3, 6b-8 gates are sufficient, and the A module uses the friendly current mode logic, as shown in Figure 4(a).
If wired logic is configured in the B module as shown in FIG. 4(b), only (14b/3)-6 gates are required. On the other hand, according to the conventional method using logic circuit sounds, when the number of bits is a multiple of 2, 7a-8 gates are required.For this reason, if the number of bits is a multiple of 2, 7a-8 gates are required.
2 gates are rarely required, but 190 gates are sufficient and 1
There will be 52 fewer gates. As the number of bits increases, this difference becomes even larger.

In addition, although the above embodiment takes in data from adjacent bit strings, one of A modules 2 to 5 is input with 3 bits of odd number, even number, and odd number, and the other one is input with even number and odd number. , an even number of 3 bits is input, and these bits need not have the same weight. In addition, the input data is not only a 121-bit string represented by multiple bits, but also other multiple pits. It is also possible to obtain modulo 3 data between t and t.

〔Effect of the invention〕

As explained above, the present invention has the advantage that the modulo 3 remainder of any multi-digit binary number can be obtained by repeating a small-scale and simple circuit, and therefore requires less hardware.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a modulo-3 remainder generator according to an embodiment of the invention, FIG. 2 is a circuit diagram of an A module used in an embodiment of the invention, and FIG. 3 is an embodiment of the invention. The circuit diagram of the B module used in FIG. 4 is a circuit configuration diagram of the A module and B module (2) using a technology such as current mode logic and wire drossic. 2-5...Module A, 6-8...Module B.

Claims (1)

[Claims] In a modulo-3 remainder generator that generates a modulo-3 remainder of binary data represented by a plurality of bits, the odd, even, and odd three bits of the binary data are input, and the modulo-3 remainder of the input data and its negation data are generated. A first module that outputs, a second module that receives 3 bits of even, odd, and even numbers and outputs the modulo 3 remainder of the input data and its negation data, and output data of the first module and the second module. and a third module that outputs a new modulo-3 remainder from the modulo-3 remainder generator.