JPS6269560A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent occurrence of etching damages to a semiconductor substrate and to prevent deterioration of junction characteristics, by avoiding exposure of the semiconductor substrate, when side walls are formed on both sides of a gate electrode. CONSTITUTION:On a P-type silicon substrate 1, an element isolating field oxide film 2 and a gate oxide film 3 as a protecting film are formed. A gate electrode 4 comprising a polycrystalline silicon film is formed on the film 3. Then thermal oxidation is performed, and the gate electrode 4 is coated with an SiO2 film 5. Thereafter, an Si3N4 film 7 and an SiO2 film 8 are formed on the entire surface. The film 8 is etched back, and side walls 8' are formed on both sides of the gate electrode 4. Then, the Si3N4 film 7 on the exposed gate electrode 4 and on the silicon substrate 1 is removed. Thereafter, ions are implanted, and an N<+> diffused layer 9 is formed. Thus source and drain regions 10 comprising an N<-> diffused layer 6 and an N<+> diffused layer 9 are formed. Then Ti silicide 11 is formed only on the gate electrode 4 and the source and drain regions 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which electrode portions of MIs elements are silicided.

[Background technology]

In recent years, with the increasing integration of semiconductor devices such as ICs, LSIs, and VLSIs, the miniaturization of elements has progressed.
Source in MIS type semiconductor devices.

Impurity diffusion layers such as drain regions have become shallower and have a smaller area, and the widths of interconnections connecting elements have also been reduced. Therefore, the negative resistance in the impurity diffusion layer and wiring increases,
This is an obstacle to increasing the speed of water drop motion. For this reason, in recent semiconductor devices, attempts have been made to reduce the resistance by making the entire surface of the impurity diffusion layer, that is, the surface of the silicon substrate, metal silicide, thereby improving the device operating speed.

In this case, when forming metal silicide on the gate electrode and the source and drain regions simultaneously, sidewalls are first formed on both sides (side walls) of the gate electrode, and then the upper surface of the exposed gate electrode and the source and drain regions are formed. After increasing the distance from the substrate surface, a refractory metal film is formed over the entire surface, and then a silicidation reaction is performed to form metal silicide on the gate electrode and on the source and drain regions.

At this time, the sidewall suppresses the phenomenon of metal silicide creeping up, that is, prevents the substrate 81 from climbing up.

In this way, sidewalls are not only necessary when forming the source and drain regions of a MIS element with an offset gate structure, but also regardless of the offset gate structure. Superb and sauce.

This is necessary when forming metal silicide on the drain region.

Next game)! MI with an offset gate structure in which metal silicide is formed on the top and on the surfaces of the source and drain regions.
The S element is made as follows.

First, the surface of the P-type silicon substrate is oxidized, a polycrystalline silicon gate electrode is formed, and then a source is formed.

N-type ions are implanted into the drain formation region at a low concentration, and then a CVD method (Chemical Vapor Dep.
A SiO film is formed by reactive ion etching (T (hereinafter abbreviated as IB)).

) method to form sidewalls on the side walls of the gate electrode, and N-type ions are implanted at a high concentration into the exposed substrate surface of the source and drain forming regions, and heat-treated to form N-type ions.
- Form source and drain regions consisting of a diffusion layer and an N diffusion layer. At this time, on the gate electrode and the source,
SiO on the drain region! A film is formed, which is removed and a high melting point metal film is formed over the entire surface. Note that after forming the sidewalls, a high melting point metal film may be formed on the exposed source and drain region surfaces and the entire surface including the gate 1ftf & -hffi, and then N-type ions may be implanted through the high melting point metal into the source and drain forming regions. .

Thereafter, silicide of a high melting point metal is formed on the gate electrode and the source and drain regions by a silicidation reaction. In this way, a MIS element having an offset gate structure in which the electrode portion is silicided is manufactured.

However, when the sidewall is formed by the RIE method, the substrate surface is exposed and is struck by plasma, causing etching damage to the Si substrate.

Moreover, due to this etching damage, crystal defects are likely to occur near the roots of the sidewall, which is subject to a lot of stress, and joint leakage is therefore likely to occur. In other words, the bonding characteristics tend to deteriorate. Furthermore, there is a problem in that the substrate surface becomes rough due to etching during sidewall formation.

Note that on the gate electrode and source of the MIS element.

Even if high-melting point metal silicide is formed on the drain region, it is necessary to have a sidewall on the sidewall of the gate electrode, which is necessary when forming the source and drain region of an offset gate structure, as stated in IEEE IEDM.・
E.E.E.I.D.M.) 1982
P, 718-P721.

[Purpose of the invention]

The purpose of the present invention is to prevent the semiconductor substrate from being exposed when forming the sidewalls on both sides of the gate electrode, thereby preventing etching damage to the semiconductor substrate and preventing deterioration of bonding characteristics. An object of the present invention is to provide an entire method for manufacturing a semiconductor device that prevents the surface of a semiconductor substrate from becoming rough.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a protective film is entirely formed on a semiconductor substrate, a gate electrode is formed on this protective film, a sidewall forming member is further formed on the entire surface, and then this sidewall forming member is subjected to a total anisotropic dry etching method. A side wall is formed on the side wall of the gate electrode by etching, and then the entire protective film on the semiconductor substrate is removed by wet etching, and then high melting point metal silicide is etched on the exposed gate electrode and the source and drain regions. As a result, the semiconductor substrate is not exposed when forming the sidewall, and since the protective film is removed using a wet etching method, no etching damage is caused to the semiconductor substrate. No crystal defects occur in the semiconductor substrate near the roots, no junction leakage occurs, and deterioration of junction characteristics can be prevented. Furthermore, it is possible to prevent the surface of the semiconductor substrate from becoming rough due to etching when forming sidewalls or wet etching when removing the protective film.

〔Example〕

FIGS. 1(a) to 1(e) show an embodiment of the method for manufacturing a semiconductor device according to the present invention, in particular, an offset gate structure M
This is an example applied to an IS element.

First, as shown in the figure (a), a field oxide film (SiO2 film) 2 for element isolation and a gate oxide film (SIO! film) 3 as a protective film are formed on a P-type silicon substrate 1, and There is a gate electrode 4 made of a polycrystalline silicon film on top.
form. Next, the gate electrode 4 is covered with a SiOt film 5 by thermal oxidation. Then, N-type ions (for example, P (phosphorus) ions) are ion-implanted at a low concentration to form the N- diffusion layer 6.
form.

Next, as shown in the same figure (b), the entire surface is subjected to CVD method.
i3N, membrane 7. Then, a SiO2 film 8 is formed as a sidewall forming member, and S10! By etching back the film 8 by RIE, sidewalls 8' are formed on both sides of the gate electrode 4, as shown in FIG. 4(e).

In this case, the 51sN4 film 7 serves as a stopper against etching during the formation of the sidewall 8'.

Next, as shown in FIG. 4(d), the exposed goo (St3N4 film 7 on the electrode 4 and on the silicon substrate 1) is removed by wet etching or anisotropic dry etching. The N 2 diffusion layer 9 is formed by implanting iN type ions (for example, As (arsenic) ions) into a high concentration of gold. As a result, the impurity diffusion layer of the offset gate structure,
A source and drain region 10 consisting of a toe 9N-diffusion layer 6 and an N-diffusion layer 9 is formed as shown.

After this, as shown in FIG. 4(e), the S
The iO2 films 3 and 5 are removed by wet etching, and then a high-melting point metal film, such as a T1 film, is formed on the entire surface by sputtering, followed by a silicidation reaction to form a layer on the gate electrode 4 and on the source and drain. The T1 film on the region 10 is silicided, and the unreacted T1 film that has not been silicided is removed by wet etching.

As a result, Ti silicide 11 is left only on gate electrode 4 and source and drain regions 10.

According to the above manufacturing method, CVD-8in.

When forming the sidewall 8' consisting of a film, 813N
, by using the film 7 as an etching stopper member, the surface of the silicon substrate 1 is not exposed (here, also L
S10 if there is no S i B N4 film 7! (The film 3 is also etched and the surface of the silicon substrate 1 is exposed and is struck by the plasma.) Therefore, the surface of the silicon substrate 1 is not struck by the plasma during etching, and the silicon substrate 1 is etched. Take no damage.

Furthermore, when forming the high melting point metal silicide, the stow film 3 as a protective film is removed by wet etching, so that the surface of the silicon substrate 1 is not damaged by etching at this time as well.
No roughness occurs on the surface.

In addition, since the silicon substrate 1 is not damaged by etching, there is no risk of crystal defects occurring near the roots of the sidewall 8', which is subject to a lot of stress, as in the conventional case, and junction leakage does not occur. Nor. That is, deterioration of bonding characteristics can be prevented.

Furthermore, the manufacturing process described above is also 5tsN compared to the conventional method.

Separately in the process of forming the film 7 and after forming the sidewall 8',
3N, belly 7 and 810. The conventional offset gate structure MIS
It is almost the same as Suko's process. Therefore, a MO with a silicided electrode part can be formed by a simple process without causing etching damage or roughness on the surface of the silicon substrate 1.
Eight elements can be made.

As described above, it is possible to improve the reliability of the vice.

〔effect〕

(1) Even when the sidewall is formed by etching the sidewall forming member, the surface of the semiconductor substrate is not exposed, and the protective film is removed using a wet etching method, so the surface of the semiconductor substrate is not damaged by etching. In addition, no roughness occurs on the surface of the semiconductor substrate.

(2) Due to (1), the semiconductor substrate does not suffer from etching damage, so there is no risk of crystal defects occurring near the roots of the sidewalls, which are subject to a lot of stress, as in the conventional case, and junction leakage does not occur. In other words, deterioration of bonding characteristics can be completely prevented.

(3) Since the step of removing at least the protective film by wet etching is added, the manufacturing process is approximately the same as the manufacturing process of a conventional MIS element in which the electrode portion is silicided. Therefore, all MO8 devices with silicided electrode portions can be manufactured by a simple process without causing etching damage or roughness on the surface of the semiconductor substrate.

(4) The reliability of the device can be improved by the above.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the embodiment of FIG. 1, CVD is used as the sidewall forming member.
Although the -8in2 film 8 is used, a sputtered SiO2 film or a polycrystalline silicon film may also be used. Also, although Si3N4 is used as the etching stopper material, a polycrystalline silicon film or other material may also be used. side wall 8
The sidewall forming member and the etching stopper member may be appropriately selected so that the end point of etching can be detected during formation.

Further, although the embodiment in FIG. 1 is a case where a MIS element with an offset gate structure is formed, the present invention can be similarly applied even when the MIS element does not have an offset gate structure, and the manufacturing process in this case is shown in FIGS. 2(a) to (8). ). In this manufacturing process, in the N- diffusion layer 6 formation step, an N diffusion layer 10 that becomes a source and a drain is formed, and in FIG. 1(d), a 3N diffusion layer is not formed. This is the same, and the same can be said of FIG. 1 in terms of operation and effect. In FIG. 2, the same or equivalent parts as in FIG. 1 are denoted by the same reference numerals.

Furthermore, in the embodiment shown in FIG. 1, 810. Membrane 3 gold is used, but 81. An N4 film may also be used, in which case a MIS element with an offset gate structure will be formed as shown in FIGS. 3(a) to 3(e). In this figure, the same reference numerals are used for the same or corresponding parts as in FIG. 1. A brief explanation of the process shown in Figure 3 is as follows:
As shown in FIG. 2A, a SimN+ film 12 is formed on a silicon substrate 1, a gate electrode 4 is formed, and 3N type ions are implanted to form an N- diffusion layer 6. Thereafter, a CVD-8ift film 8'f is formed as shown in FIG. 2(b), and then a sidewall 8' is formed as shown in FIG. When 81.N is used as a protective film, the film 12 functions as an etch/guest member. Next, N-type ions are implanted to form an N+ type diffusion layer 9, thereby forming an N- diffusion layer 6 and a +N diffusion layer. A source/drain region 10 consisting of a layer 9 is formed.After this, as shown in FIG. 3(d), the Si, N, and film 12 exposed on the silicon substrate 1 are removed by wet etching, and then etched in the same manner as described above. A high melting point metal silicide, for example, TI silicide 11, is formed as shown in FIG. The first thing about the effect is
The same thing can be said as explained in the figure.

In addition, in FIG. 3, 81. is used as a protective film. Although N and film 12 are used, an oxide film (SiO2 film) and Si3N are used.

A two-layer film consisting of a oxide film (SiOx) and a Si
A three-layer film consisting of an N4 film and an oxide film (St, . . . ) may be used, and although the offset gate structure is shown in FIG. 3, it may be other than the offset gate structure as shown in FIG. 2.

[Application field]

In the above description, the invention made by the present inventor is mainly applied to the manufacturing technology of MIS elements whose electrode portions are silicided, which is the background of the invention and the next application field, but the invention is not limited thereto.

[Brief explanation of drawings]

FIGS. 1(a) to (e) are process cross-sectional views showing an embodiment of the method for manufacturing a semiconductor device according to the present invention; FIGS. 2(a) to (e) and FIGS. 3(a) to (e). These are process sectional views showing other embodiments of the present invention. l...Silicon substrate, 3...SiO2 film, 4...
Gate electrode, 5... SiO2 film, 6... N-type diffusion layer, 7... Si3N, film, 8... cvn-SiO2
Membrane, 8'...Side wall, 9...N-shaped scattering layer, 10... Source. Drain region, 11...TI silicide, 12...
・(b) Figure 1(t)

Claims (1)

[Claims] 1. MIS formed by silicided electrode portions on a semiconductor substrate
In a method of manufacturing a semiconductor device in which an element is formed, a step of forming a protective film on a semiconductor substrate, a step of forming a gate electrode on this protective film, and a step of forming a sidewall forming member on the entire surface and then etching the sidewall forming member using an anisotropic dry etching method to form a sidewall on the sidewall of the gate electrode, and then etching the protective film on the semiconductor substrate using a wet etching method. A semiconductor device comprising a step of removing the metal silicide, and a step of forming a high melting point metal silicide on the exposed gate electrode and the source and drain regions to silicide the electrode portion of the MIS element. manufacturing method. 2. A SiO_2 film is used as the protective film, and S
2. The method of manufacturing a semiconductor device according to claim 1, wherein an i_3N_4 film is formed and a CVD-SiO_2 film, a sputtered SiO_2 film, a polycrystalline silicon film, or the like is used as the sidewall forming member. 3. As the protective film, Si_3N_4 film or SiO_2
A patent in which a two-layer film of a film and a Si_3N_4 film or a three-layer film of an SiO_2 film, a Si_3N_4 film, and a SiO_2 film is used, and a CVD SiO_2 film, a sputtered SiO_2 film, a polycrystalline silicon film, etc. is used as the sidewall forming member. A method for manufacturing a semiconductor device according to claim 1.