JPS626689Y2 - - Google Patents
Info
- Publication number
- JPS626689Y2 JPS626689Y2 JP1982033835U JP3383582U JPS626689Y2 JP S626689 Y2 JPS626689 Y2 JP S626689Y2 JP 1982033835 U JP1982033835 U JP 1982033835U JP 3383582 U JP3383582 U JP 3383582U JP S626689 Y2 JPS626689 Y2 JP S626689Y2
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- support jig
- wafers
- groove portion
- wafer support
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 235000012431 wafers Nutrition 0.000 claims description 95
- 239000004065 semiconductor Substances 0.000 description 25
- 238000003780 insertion Methods 0.000 description 9
- 230000037431 insertion Effects 0.000 description 9
- 239000012808 vapor phase Substances 0.000 description 9
- 238000000034 method Methods 0.000 description 6
- 238000012545 processing Methods 0.000 description 6
- 230000002093 peripheral effect Effects 0.000 description 5
- 239000010453 quartz Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
Landscapes
- Packaging For Recording Disks (AREA)
- Packaging Frangible Articles (AREA)
Description
【考案の詳細な説明】
本考案は、半導体ウエハの気相拡散、気相成
長、気相エツチング等の気相処理工程においてウ
エハを支持するための石英等で作られたウエハ支
持治具に関する。[Detailed Description of the Invention] The present invention relates to a wafer support jig made of quartz or the like for supporting a wafer during vapor phase processing steps such as vapor phase diffusion, vapor phase growth, and vapor phase etching of semiconductor wafers.
現在、半導体製造過程において、気相拡散工
程、気相成長工程、あるいは気相エツチング工程
等の気相処理工程は必要不可欠なものとなつてい
る。このような気相処理工程においては、それぞ
れの処理に応じた気体が流入される石英チユーブ
の中に、半導体ウエハを等間隔に均一に配列する
ための石英等で作られたウエハ支持治具が用いら
れている。 Currently, in semiconductor manufacturing processes, vapor phase treatment processes such as vapor phase diffusion processes, vapor phase growth processes, and vapor phase etching processes have become indispensable. In such a gas phase processing process, a wafer support jig made of quartz or the like is used to uniformly arrange the semiconductor wafers at equal intervals in a quartz tube into which the gas corresponding to each process is flowed. It is used.
第１図ないし第３図は、このようなウエハ支持
治具１の従来例を示し、第１図は平面図、第２図
は第１図の−線断面矢視図、第３図は第１図
の−線拡大矢視図である。これらの第１図な
いし第３図において、ウエハ支持治具１は、複数
枚の半導体ウエハ２をその主面と直角の方向に、
上記主面が互いに平行となるように配列支持する
ものであり、上記主面と直角方向に互いに平行に
延設される２本の梁状腕部３，４を有している。
これらの腕部３，４の半導体ウエハ２の周縁部と
当接する位置には、第３図に示すような平行溝部
５がそれぞれ形成されている。この平行溝部５の
間隙寸法ｇは、半導体ウエハ２の厚みｔと同程度
あるいは僅かに大きい程度に形成されている。し
たがつて、半導体ウエハ２の平行溝部５に案内挿
入することにより、上記ウエハ主面の前後方向の
がたつき等を生じさせることなく、安定してウエ
ハ支持が行なえる。 1 to 3 show a conventional example of such a wafer support jig 1, in which FIG. 1 is a plan view, FIG. 2 is a cross-sectional view taken along the line - in FIG. 1, and FIG. FIG. 1 is an enlarged view taken along the - line in FIG. 1; In FIGS. 1 to 3, a wafer support jig 1 holds a plurality of semiconductor wafers 2 in a direction perpendicular to their main surfaces.
It is arranged and supported so that the main surfaces are parallel to each other, and has two beam-like arm portions 3 and 4 extending parallel to each other in a direction perpendicular to the main surfaces.
Parallel groove portions 5 as shown in FIG. 3 are formed in positions where these arm portions 3 and 4 come into contact with the peripheral edge of the semiconductor wafer 2, respectively. The gap dimension g of this parallel groove portion 5 is formed to be approximately the same as or slightly larger than the thickness t of the semiconductor wafer 2. Therefore, by guiding and inserting the semiconductor wafer into the parallel groove portion 5 of the semiconductor wafer 2, the wafer can be stably supported without causing any wobbling or the like in the front-rear direction of the main surface of the wafer.
しかしながら、このような平行溝部５に半導体
ウエハ２を案内挿入するためには、作業者がピン
セツト等を用いてウエハを１枚ずつ支持治具１に
セツトしなければならず、機械を用いて自動的に
複数枚のウエハを同時にセツトすることは困難で
ある。 However, in order to guide and insert the semiconductor wafer 2 into such a parallel groove 5, an operator must set the wafers one by one onto the support jig 1 using tweezers or the like, and this cannot be done automatically using a machine. It is difficult to set multiple wafers at the same time.
そこで、第４図ないし第６図に示すような３本
の梁状腕部１２，１３，１４を有するウエハ支持
治具１１を用い、これらの腕部１２，１３，１４
の各半導体ウエハ２との当接位置に、断面Ｖ字状
の溝部１５をそれぞれ形成して、上記自動セツト
時にウエハ２を支持治具１１上に載置し易くして
いる。ところで、半導体ウエハ２には、第７図に
示すように、その結晶軸方向を明示するためのカ
ツト部（フアセツト、いわゆるオリエンテーシヨ
ンフラツト）７が形成されており、このカツト部
７が上記溝部１５に位置した場合には３本の腕部
１２，１３，１４の各溝部１５による３点支持が
行なえず、ウエハ２のがたつきや倒れ等が生じて
しまう。また、半導体ウエハ２の径にも多少のば
らつきがあり、この径のばらつきによつても上記
３点支持が有効に行なえず、上記倒れ等が生じて
しまう。 Therefore, a wafer support jig 11 having three beam-like arm parts 12, 13, 14 as shown in FIGS. 4 to 6 is used, and these arm parts 12, 13, 14 are
A groove portion 15 having a V-shaped cross section is formed at the contact position with each semiconductor wafer 2, so that the wafer 2 can be easily placed on the support jig 11 during the automatic setting. Incidentally, as shown in FIG. 7, the semiconductor wafer 2 is formed with a cut portion (facet, so-called orientation flat) 7 for clearly indicating the direction of its crystal axis. If the wafer 2 is located in the groove 15, the three arms 12, 13, and 14 cannot be supported at three points by the grooves 15, causing the wafer 2 to wobble or fall. Furthermore, there is some variation in the diameter of the semiconductor wafer 2, and due to this variation in diameter, the above-mentioned three-point support cannot be performed effectively, resulting in the above-mentioned falling.
本考案は、このような従来の実情に鑑み、複数
枚の半導体ウエハを同時に自動的にウエハ支持治
具上にセツトでき、しかも上記がたつきや倒れ等
のない安定したウエハ支持が行なえるようなウエ
ハ支持治具の提供を目的としている。 In view of these conventional circumstances, the present invention has been developed to allow multiple semiconductor wafers to be automatically set on a wafer support jig at the same time, and to support the wafers stably without wobbling or falling. The purpose of this product is to provide a wafer support jig.
すなわち、本考案に係るウエハ支持治具の特徴
は、複数枚のウエハをその主面と直角の方向に上
記主面が互いに平行となるように配列するウエハ
支持治具において、上記直角方向に互いに平行に
延設される３本の梁状腕部を有し、両外側の２本
の腕部の上記各ウエハを支持する位置にそれぞれ
断面Ｖ字状の溝部を形成し、中央の腕部の上記各
ウエハを支持する位置にそれぞれ断面Ｙ字状の溝
部を形成して成ることである。 That is, the feature of the wafer support jig according to the present invention is that in a wafer support jig that arranges a plurality of wafers in a direction perpendicular to their main surfaces so that the main surfaces are parallel to each other, It has three beam-like arms extending in parallel, and grooves each having a V-shaped cross section are formed at the positions of the two outer arms supporting each of the wafers, and the center arm has three beam-like arms extending in parallel. Grooves each having a Y-shaped cross section are formed at positions for supporting each of the wafers.
以下、本考案に係るウエハ支持治具の好ましい
実施例について、図面を参照しながら説明する。 Hereinafter, preferred embodiments of the wafer support jig according to the present invention will be described with reference to the drawings.
第８図ないし第１１図は本考案の一実施例とし
てのウエハ支持治具２１を示し、第８図は平面
図、第９図は第８図の−線断面図、第１０図
は第９図の−線拡大矢視図、第１１図は第９
図のXI−XI線拡大矢視図である。 8 to 11 show a wafer support jig 21 as an embodiment of the present invention, FIG. 8 is a plan view, FIG. 9 is a sectional view taken along the line -- in FIG. 8, and FIG. Figure 11 is an enlarged view taken along the - line arrow direction.
It is an enlarged view taken along the line XI-XI in the figure.
これらの第８図ないし第１１図において、ウエ
ハ支持治具２１は、たとえば石英等で作られてお
り、複数枚の半導体ウエハ２をその主面と直角の
方向に該主面が互いに平行となるように配列する
ものである。このウエハ支持治具２１は、上記配
列されるウエハの主面と平行に対向配置される２
枚の逆台形状の側板２２，２３間に、上記ウエハ
主面と直角方向に対して互いに平行に延設される
３本の梁状腕部２４，２５，２６を設けて成り、
両外側の２本の腕部２４，２６における上記各ウ
エハ２の周縁と接する位置に、第１０図に示すよ
うな断面Ｖ字状の溝部２７をそれぞれ形成し、中
央の腕部２５における上記各ウエハ２の周縁と接
する位置に、第１１図に示すような断面Ｙ字状の
溝部２８をそれぞれ形成している。この断面Ｙ字
状の溝部２８は、上記Ｖ字状溝部２７よりもやや
広い角度で開口しているＶ字状溝部分２８ａの底
部に平行溝部分２８ｂを連続して成る形状を有し
ている。なお、この平行溝部分２８ｂの間隙寸法
ｇは、半導体ウエハ２の厚みｔとほぼ同程度か僅
かに大きめとし、ウエハ案内挿入時にがたつき等
が発生しないように設定することが望ましい。 In FIGS. 8 to 11, the wafer support jig 21 is made of, for example, quartz, and holds a plurality of semiconductor wafers 2 in a direction perpendicular to their main surfaces so that the main surfaces are parallel to each other. It is arranged like this. This wafer support jig 21 has two
Three beam-like arms 24, 25, 26 are provided between the inverted trapezoidal side plates 22, 23, extending parallel to each other in a direction perpendicular to the main surface of the wafer,
Grooves 27 having a V-shaped cross section as shown in FIG. Grooves 28 each having a Y-shaped cross section as shown in FIG. 11 are formed at positions in contact with the peripheral edge of the wafer 2. As shown in FIG. This groove portion 28 having a Y-shaped cross section has a shape in which a parallel groove portion 28b is continuous to the bottom of a V-shaped groove portion 28a that opens at a slightly wider angle than the V-shaped groove portion 27. . Note that the gap g between the parallel groove portions 28b is desirably set to be approximately the same as or slightly larger than the thickness t of the semiconductor wafer 2 so as to prevent rattling or the like when the wafer is guided and inserted.
このような構造を有するウエハ支持治具２１に
より半導体ウエハ２を支持する場合に、前述した
結晶軸方向を指示するカツト部７の位置やウエハ
径のばらつき等によつて、上記中央の梁状腕部２
５のＹ字状溝部２８へのウエハ挿入深さが異なつ
てくる。本考案においては、最も浅く挿入された
ときのウエハ先端がＹ字状溝部２８のＶ字状溝部
分２８ａの底部近傍に位置するように、また、最
も深く挿入されたときのウエハ先端がＹ字状溝部
２８の平行溝部分２８ｂの底部近傍に位置するよ
うに、３本の梁状腕部２４，２５，２６によるウ
エハ支持位置関係や各溝部２７，２８の深さ等を
設定している。 When the semiconductor wafer 2 is supported by the wafer support jig 21 having such a structure, the center beam-like arm may be Part 2
The depth of insertion of the wafer into the Y-shaped groove 28 of No. 5 differs. In the present invention, the tip of the wafer when inserted at the shallowest depth is located near the bottom of the V-shaped groove portion 28a of the Y-shaped groove portion 28, and the tip of the wafer when inserted at the deepest point is positioned in the Y-shape. The wafer support positional relationship by the three beam-like arms 24, 25, and 26 and the depth of each groove 27 and 28 are set so that the wafer is located near the bottom of the parallel groove portion 28b of the groove 28.
ここで、第１２図ないし第１４図は、主として
半導体ウエハ２の上記カツト部７の位置によつて
上記挿入深さが異なることを示しており、各図の
Ａに半導体ウエハ２の支持状態を、Ｂに上記Ｙ字
状溝部２８に対するウエハ先端の挿入深さをそれ
ぞれ示している。 Here, FIGS. 12 to 14 show that the insertion depth differs mainly depending on the position of the cut portion 7 of the semiconductor wafer 2, and A in each figure shows the supporting state of the semiconductor wafer 2. , B show the insertion depth of the wafer tip into the Y-shaped groove 28, respectively.
まず、第１２図Ａは、半導体ウエハ２の上記カ
ツト部７が、ウエハ支持治具２１の中央の腕部２
５と対向する位置に配される場合を示し、このと
き上記挿入深さは最も浅くなり、第１２図Ｂに示
すように、ウエハ先端はＹ字状溝部２８のＶ字状
溝部分２８ａの底部近傍に達する。この第１２図
の場合には、半導体ウエハ２の外周縁部は、ウエ
ハ支持治具２１の両外側の梁状腕部２４，２６の
各Ｖ字状溝部２７の底部と、中央の梁状腕部２５
のＹ字状溝部２８のＶ字状溝部分２８ａの底部と
によつて、ほぼ３点支持されることになり、がた
つきや倒れ等のない安定な支持が行なわれる。 First, FIG. 12A shows that the cut portion 7 of the semiconductor wafer 2 is connected to the central arm portion 2 of the wafer support jig 21.
In this case, the insertion depth is the shallowest, and as shown in FIG. Reach the neighborhood. In the case of FIG. 12, the outer peripheral edge of the semiconductor wafer 2 is connected to the bottom of each V-shaped groove 27 of the beam-like arms 24 and 26 on both outer sides of the wafer support jig 21, and to the center beam-like arm. Part 25
The Y-shaped groove 28 and the bottom of the V-shaped groove portion 28a provide support at approximately three points, providing stable support without wobbling or falling.
次に、第１３図Ａは、半導体ウエハ２の上記カ
ツト部が、３本の腕部２４，２５，２６のいずれ
の溝部にも位置しない状態を示し、上記挿入深さ
は、第１３図Ｂに示すように、ウエハ先端がＹ字
状溝部２８の平行溝部分２８ｂの途中位置に達す
る。 Next, FIG. 13A shows a state in which the cut portion of the semiconductor wafer 2 is not located in any of the grooves of the three arm portions 24, 25, and 26, and the insertion depth is as shown in FIG. 13B. As shown in FIG. 2, the leading edge of the wafer reaches the middle of the parallel groove portion 28b of the Y-shaped groove portion 28.
また、第１４図Ａは、ウエハの上記カツト部７
が、上記両外側の２本の梁状腕部２４，２６のい
ずれか一方、たとえば腕部２４のＶ字状溝部２７
により支持される場合を示しており、上記挿入深
さが最も深く、第１４図Ｂに示すように、ウエハ
先端はＹ字状溝部２８の平行溝部分２８ｂの底部
近傍にまで達する。 Further, FIG. 14A shows the cut portion 7 of the wafer.
However, one of the two outer beam-like arm portions 24 and 26, for example, the V-shaped groove portion 27 of the arm portion 24,
The insertion depth is the deepest, and the wafer tip reaches near the bottom of the parallel groove portion 28b of the Y-shaped groove portion 28, as shown in FIG. 14B.
これらの第１３図および第１４図の場合には、
両外側の２本の梁状腕部２４，２６の各Ｖ字状溝
部２７により２点支持され、前後方向（ウエハ主
面と直角方向）の倒れについては、中央の梁状腕
部２５のＹ字状溝部２８の平行溝部分２８ｂによ
り防止され、がたつきや倒れ等のない極めて安定
なウエハ支持が行なわれる。 In the case of these figures 13 and 14,
The two outer beam-like arms 24 and 26 are supported at two points by the V-shaped grooves 27, and the center beam-like arm 25 is supported by the This is prevented by the parallel groove portion 28b of the letter-shaped groove portion 28, and extremely stable wafer support is performed without wobbling or falling.
このようなウエハ支持治具２１に対して、半導
体ウエハ２をセツトする際には、ウエハ外周縁部
が各梁状腕部２４，２５，２６の溝部２７，２８
のＶ字状部分の広い開口部内に容易に案内され、
このＶ字状部分の底部位置にて位置決めされるた
め、ウエハを載置し易く、また等間隔に均一に配
列される。しかも、中央の梁状腕部２５のウエハ
外周縁部支持位置には、上述のようなＹ字状溝部
２８を形成しているため、ウエハ先端の挿入深さ
が異なつてもがたつきや倒れ等を有効に防止でき
る。 When setting the semiconductor wafer 2 on such a wafer support jig 21, the outer peripheral edge of the wafer should be aligned with the grooves 27, 28 of the beam-like arms 24, 25, 26.
easily guided into the wide opening of the V-shaped portion of the
Since the wafers are positioned at the bottom of this V-shaped portion, it is easy to place the wafers, and the wafers are evenly arranged at equal intervals. Furthermore, since the Y-shaped groove 28 as described above is formed at the supporting position of the wafer outer peripheral edge of the central beam-like arm 25, the wafer tip may wobble or fall even if the insertion depth of the wafer tip is different. etc. can be effectively prevented.
したがつて、機械等を用いて複数枚の半導体ウ
エハ２を同時にウエハ支持治具２１上にセツトで
き、ウエハのカツト部７の位置やウエハ径のばら
つき等に左右されることなく、全ウエハを安定に
支持することができ、気相処理工程前のウエハの
セツト作業の自動化を容易に実現可能とし、量産
効率を高めるものである。 Therefore, a plurality of semiconductor wafers 2 can be set on the wafer support jig 21 at the same time using a machine or the like, and all wafers can be set on the wafer support jig 21 at the same time without being affected by the position of the cut portion 7 of the wafers or variations in wafer diameter. It can be stably supported, easily automating the wafer setting work before the vapor phase processing process, and increasing mass production efficiency.
さらに、従来の第１図ないし第３図に示したよ
うなウエハ支持治具１は、２本の腕部３，４の平
行溝５による２点支持であるため、洗浄等を繰り
返すことにより溝が広がつてウエハが倒れ易くな
る欠点があつたが、本考案のように３点支持とす
ることにより、溝の広がりによる影響が極めて少
なくなり、長期的に使用可能となり、長寿命化が
実現できるため、いわゆるランニングコストの低
価格化が図れる。 Furthermore, since the conventional wafer support jig 1 as shown in FIGS. 1 to 3 is supported at two points by the parallel grooves 5 of the two arms 3 and 4, the grooves can be removed by repeated cleaning etc. However, by supporting the wafer at three points as in the present invention, the influence of the widening of the grooves is extremely reduced, making it possible to use the groove for a long period of time, resulting in a longer service life. As a result, so-called running costs can be reduced.
なお、このようなウエハ支持治具２１は、気相
拡散処理工程や、減圧CVD、ドライアツシヤー
（ドライエツチング）処理工程等の種々の気相処
理工程に適用し得ることは勿論である。 It goes without saying that such a wafer support jig 21 can be applied to various vapor phase processing steps such as vapor phase diffusion processing, low pressure CVD, and dry etching processing.
第１図ないし第３図は従来のウエハ支持治具の
一例を示し、第１図は平面図、第２図は第１図の
−線断面矢視図、第３図は第１図および第２
図の−線拡大矢視図である。第４図ないし第
６図はウエハ支持治具の他の従来例を示し、第４
図は平面図、第５図は第４図の−線断面矢視
図、第６図は第５図の−線拡大矢視図であ
る。第７図は半導体ウエハの外形形状を示す正面
図である。第８図ないし第１４図は本考案に係る
ウエハ支持治具の一実施例を示し、第８図は平面
図、第９図は第８図の−線断面矢視図、第１
０図および第１１図は第９図のそれぞれ−線
拡大矢視図およびXI−XI線拡大矢視図、第１２図
ないし第１４図はそれぞれ異なる支持状態におけ
るウエハ先端の挿入深さを説明するための図であ
り、各図のＡはウエハ支持状態を示す概略正面
図、各図のＢはウエハ先端の挿入深さを示す概略
断面図である。
２……半導体ウエハ、７……カツト部、２１…
…ウエハ支持治具、２４，２５，２６……梁状腕
部、２７……Ｖ字状溝部、２８……Ｙ字状溝部、
２８ａ……Ｖ字状溝部分、２８ｂ……平行溝部
分。
1 to 3 show an example of a conventional wafer support jig, in which FIG. 1 is a plan view, FIG. 2 is a cross-sectional view taken along the - line in FIG. 1, and FIG. 2
It is a - line enlarged arrow direction view of a figure. 4 to 6 show other conventional examples of wafer support jigs.
The figure is a plan view, FIG. 5 is a sectional view taken along the line - in FIG. 4, and FIG. 6 is an enlarged view taken along the line - in FIG. FIG. 7 is a front view showing the external shape of the semiconductor wafer. 8 to 14 show an embodiment of the wafer support jig according to the present invention, in which FIG. 8 is a plan view, FIG. 9 is a sectional view taken along the line - in FIG.
FIGS. 0 and 11 are enlarged views along the line - and XI-XI of FIG. 9, respectively, and FIGS. 12 to 14 illustrate the insertion depth of the wafer tip in different support states, respectively. A in each figure is a schematic front view showing the wafer support state, and B in each figure is a schematic sectional view showing the insertion depth of the wafer tip. 2... Semiconductor wafer, 7... Cut portion, 21...
...Wafer support jig, 24, 25, 26... Beam-shaped arm portion, 27... V-shaped groove portion, 28... Y-shaped groove portion,
28a...V-shaped groove portion, 28b...Parallel groove portion.
Claims (1)
主面が互いに平行となるように配列するウエハ支
持治具において、 上記直角方向に互いに平行に延設され、上記ウ
エハの下部とその両側の側周部で当接する３本の
梁状腕部を有し、 両外側の２本の腕部の上記各ウエハを支持する
位置にそれぞれ断面Ｖ字状の溝部を形成し、中央
の腕部の上記各ウエハを支持する位置にそれぞれ
断面Ｙ字状の溝部を形成して成るウエハ支持治
具。[Claims for Utility Model Registration] A wafer support jig for arranging a plurality of wafers in a direction perpendicular to their main surfaces so that the main surfaces are parallel to each other, which extend parallel to each other in the perpendicular direction, It has three beam-like arms that come into contact with the lower part of the wafer and the side circumferences on both sides thereof, and grooves each having a V-shaped cross section are provided at the positions of the two outer arms that support each of the wafers. A wafer support jig comprising grooves each having a Y-shaped cross section at the positions of the central arm at which the wafers are supported.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3383582U JPS58138337U (en) | 1982-03-12 | 1982-03-12 | Wafer support jig |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3383582U JPS58138337U (en) | 1982-03-12 | 1982-03-12 | Wafer support jig |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58138337U JPS58138337U (en) | 1983-09-17 |
| JPS626689Y2 true JPS626689Y2 (en) | 1987-02-16 |
Family
ID=30045361
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3383582U Granted JPS58138337U (en) | 1982-03-12 | 1982-03-12 | Wafer support jig |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58138337U (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2528108Y2 (en) * | 1991-08-28 | 1997-03-05 | 大日本スクリーン製造株式会社 | Wafer holding holder |
| JP2528111Y2 (en) * | 1991-12-04 | 1997-03-05 | 大日本スクリーン製造株式会社 | Wafer holding holder |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54124969A (en) * | 1978-03-22 | 1979-09-28 | Daicel Ltd | Semiconductor wafer container |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52139758U (en) * | 1976-04-16 | 1977-10-22 |
-
1982
- 1982-03-12 JP JP3383582U patent/JPS58138337U/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54124969A (en) * | 1978-03-22 | 1979-09-28 | Daicel Ltd | Semiconductor wafer container |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58138337U (en) | 1983-09-17 |
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