JPS6266658A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS6266658A JPS6266658A JP60206971A JP20697185A JPS6266658A JP S6266658 A JPS6266658 A JP S6266658A JP 60206971 A JP60206971 A JP 60206971A JP 20697185 A JP20697185 A JP 20697185A JP S6266658 A JPS6266658 A JP S6266658A
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- transistor
- collector
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000010410 layer Substances 0.000 abstract 2
- 239000002344 surface layer Substances 0.000 abstract 1
- 238000002955 isolation Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000003292 glue Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 210000003127 knee Anatomy 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
- H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
- H01L27/0233—Integrated injection logic structures [I2L]
- H01L27/0244—I2L structures integrated in combination with analog structures
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は通常のバイポーラリニアトランジスタとＩ Ｉ
Ｌ （Ｉｎｔｅｇｒａｔｅｄ Ｉｎｊｅｃｔｉｏｎ
Ｌｏｇｉｃ）とを共存させた半導体集積回路装置に関す
る。DETAILED DESCRIPTION OF THE INVENTION (a) Industrial application field The present invention is applicable to ordinary bipolar linear transistors and I
L (Integrated Injection)
Logic).
（ロ）従来の技術
ＩＩＬは例えば特公昭５５−３２０２５号公報に記載さ
れているように素子間分離を要としない点で高密度化が
可能で、且つ低消費電力動作をする論理素子として注目
され、さらには通常のバイポーラリニアトランジスタと
共に同一チップ上に集積できるという利点を有する。(b) Conventional technology IIL, as described in Japanese Patent Publication No. 55-32025, is attracting attention as a logic element that can achieve high densification because it does not require isolation between elements, and operates with low power consumption. Furthermore, it has the advantage that it can be integrated on the same chip with ordinary bipolar linear transistors.
第４図は通常のバイポーラリニアトランジスタとＩＩＬ
とを共存させた一例を示し、（１）はＰ型半導体基板、
（２）はＮ−型エピタキシャル層、（３）は基板（１）
とエピタキシャル層（２）との間に埋込まれたＮ“型埋
込層、（４）はエピタキシャル□
１ 層（２）を貫通したＰ＋型分離領域、（
５ａ）及び（５ｂ）１ ９．□１□、９．よ、あつ４
１１１１Ｒ’ｔｌＪ、［１□第２の島領域である。第１
の島領域（５ａ）表面には１ Ｐ型ベース領
域（６）、Ｎ゛型エミッタ領域（７）及び１
Ｎ１フレクタコンタクト領域（８）とが形成き１、、
、．１．．１ｏあｆ［Ｍ（５ａ７１゜、７ケ２５．オ。Figure 4 shows a normal bipolar linear transistor and IIL
(1) is a P-type semiconductor substrate,
(2) is the N-type epitaxial layer, (3) is the substrate (1)
and the epitaxial layer (2), (4) is the P+ type isolation region that penetrates the epitaxial □ 1 layer (2), (
5a) and (5b) 19. □1□, 9. Yo, hot 4
1111R'tlJ, [1□Second island region. 1st
On the surface of the island region (5a) are a 1 P type base region (6), an N' type emitter region (7) and 1
N1 flexor contact region (8) is formed 1,...
,．． 1. ．． 1oaf[M(5a71°, 7ke25.o.
、□
ｉ ′間Ａ″′ｔニー５’）−７）５’ｔ’；：Ｌ
″７′９″ｌｌ′ｇｈ：、′″°゛６・１°ｒｉ ２
（７）ｌｈｆｔ４Ｆ４．＜°゛ゝ４０°゛９”″“１＊
−？１Ｊ−７“５＞’）；ｌ’１（７）’−一“＃（６
） 、：。, □ i' between A'''t knee 5')-7) 5't'; :L
``7'9''ll'gh:,'''°゛6・1°ri 2
(7) lhft4F4. <°゛ゝ40°゛9””“1*
−? 1J-7"5>');l'1(7)'-1"#(6
), :.
時に形成したＰ型インジェクタ領域（９）及びＰ型ベー
ス領域（１０）、バイポーラリニアトランジスター
のエミッタ領域（７）と同時に形成したＮ゛型
コレクタ領域（１１）及びＮ０型エミツタコンタクト領
域（１２）とが形成され、インジェクタ領域（９）をエ
ミッタ、第２の島領域（５ｂ）をベース、ベース領域（
１０）をコレクタとするラテラルＰＮＰ型トランジス゛
タと、第２の島領域（５ｂ）をエミッタ、
ベース領域（１０）をベース、コレクタ領域（１１）を
コレクタとす゛ る逆方向バーチカルＮＰＮ
型トランジスタとでＩ□
ＩＬを構成している。P-type injector region (9) and P-type base region (10) formed at the same time, bipolar linear transistor
An N-type collector region (11) and an N0-type emitter contact region (12) are formed at the same time as the emitter region (7), and the injector region (9) is used as an emitter, and the second island region (5b) is formed as an emitter region. base, base area (
10) as a collector, a second island region (5b) as an emitter,
Reverse vertical NPN with base region (10) as base and collector region (11) as collector
The I□ IL is constructed with the type transistor.
ところで、斯る装置においてはリニアトランジスタのベ
ース領域（６）とＩＩＬのベース領域（１０）、リニア
トランジスタのエミッタ領域（７）とＩＩＬのコレクタ
領域（１１）とを同時に形成するので、リニアトランジ
スタのｈＦＥとＩＩＬの逆βとは同時に制御されること
になる。また、ＩＩＬは、コレクタ領域（１１）の拡散
深さを浅くして逆βを高めるとその耐圧逆ＶＣＫＯ７％
損なわれるという相反する特性を有する。従ってこれら
双方の値が満足し得る範囲を求めると、リニアトランジ
スタのｈＦＥが取り得る範囲がおのずと決定される。By the way, in such a device, the base region (6) of the linear transistor, the base region (10) of the IIL, the emitter region (7) of the linear transistor, and the collector region (11) of the IIL are formed at the same time. The inverse β of hFE and IIL will be controlled simultaneously. Moreover, when the diffusion depth of the collector region (11) is made shallow and the inverse β is increased, IIL has a breakdown voltage of inverse VCKO of 7%.
It has the contradictory properties of being damaged. Therefore, by finding a range in which both of these values can be satisfied, the range in which the hFE of the linear transistor can take is automatically determined.
第５図はり、をコントロールすべき範囲を求めるための
特性図で−ある。同図から明らかな如く、リニアトラン
ジスタのｈＦＥを高くすればＩＩＬの逆Ｖ。、０は低下
し、逆βは高くなるという特性を有する。ここでＩＩＬ
の逆ｖｃｔｏが満足する範囲を図示ＡＢの範囲、同じく
逆βが満足する範囲を図示ＣＤの範囲とすると、逆Ｖ
ｃ ＊ ｏを満足し且つ逆βを満足するリニアトランジ
スタのｈｙｇは図示１ ＸＹの範囲に限定き
れる。従って製造工程におい゛。FIG. 5 is a characteristic diagram for determining the range in which the beam should be controlled. As is clear from the figure, if the hFE of the linear transistor is increased, the reverse V of IIL will be obtained. , 0 decreases, and inverse β increases. Here IIL
If the range where the inverse vcto of is satisfied is the range shown AB, and the range where the inverse β is satisfied is the range shown CD,
The hyg of a linear transistor that satisfies c*o and inverse β can be limited to the range of 1XY shown in the figure. Therefore, in the manufacturing process.
、 ては、リニアトランジスタのり。を測定
しながら□。, Linear transistor glue. While measuring □.
その値を図示ＸＹの範囲に収めるようにして製造□ きれる。 。Manufactured so that the value falls within the range of XY shown in the diagram □ I can do it. .
□
′［
５，１（ハ）発明が解決しようとする問題点□１
、 しかしながら、従来の装置ではりニア
トランジ・１゛□
・・ スタのｈＦＥとＩＩＬの逆βとを同時
に制御していミ
□ るので、ｈＦＥの変化がそのまま逆βの
変化として、 表れてしまう。そのため第５図
から限定されるｈ、、１ ・・０°″８°−″
範囲”“非常９゛狭＜′？″″′も０゛・１
になり、工程変動等のばらつきに敏感で歩留りが、′１
・□ 安定しないという欠点があった。□ ′[ 5.1 (c) Problems to be solved by the invention □1 However, in the conventional device, the hFE of the near transistor 1゛□... star and the inverse β of IIL are controlled simultaneously. Therefore, changes in hFE appear directly as changes in inverse β. Therefore, h, which is limited from Fig. 5, is 1...0°''8°-''
Range” “Very 9゛ narrow <’? ″″′ is also 0゛・1
It has the disadvantage that it is sensitive to variations such as process fluctuations and the yield is unstable.
□
′、１
．１ （ニ）問題点を解決するための手段□
１ 本発明は斯上した欠点に鑑みてなされ、
ｈＦ−、・ｉ
、１ コントロール範囲を広くして工程の安定
化が図れり ６□イ。□［ｉｌｉ］ｉｌ□□９う、
８゜４５、−・）
、１ 導電型半導体基板と該基板上に形成した
逆導電型： のエピタキシャル層と前記基板表
面に埋込まれた：： 逆導電型の埋込層と前
記エピタキシャル層を分離用
（して形成した第１及び第２の島領域と前記第１の島領
域に形成したベース、エミッタ、コレクタより成る通常
のバイポーラトランジスタと前記第２の島領域に形成し
たラテラルトランジスタと逆方向バーチカルトランジス
タより成るＩＩＬとを具備した半導体集積回路装置にお
いて、前記ＩＩＬは前記バイポーラトランジスタのエミ
ッタと同時に形成した逆導電型のコレクタ領域と前記バ
イポーラトランジスタのベースと同時に形成した一導電
型のインジェクタ領域及び前記コレクタ領域を取り囲む
ように形成したベースコンタクト領域と該ベースコンタ
クト領域より低濃度で少なくとも前記コレクタ領域直下
に形成した前記ベースコンタクト領域より深く且つ前記
埋込層には達しない一導電型のウェル領域とを備え、前
記ＩＩＬの逆βと前記バイポーラトランジスタのｈＦＩ
Ｉとは独立して制御したことを特徴とする。□ ′, 1. 1 (d) Means for solving the problem□ 1 The present invention has been made in view of the above-mentioned drawbacks,
hF-, ・i, 1 The control range can be widened to stabilize the process. 6□B. □［ili］il□□9U,
8゜45,-・) , 1 A conductivity type semiconductor substrate, an epitaxial layer of the opposite conductivity type formed on the substrate, a buried layer of the opposite conductivity type buried in the surface of the substrate, and the epitaxial layer of the opposite conductivity type formed on the substrate. A normal bipolar transistor consisting of first and second island regions formed for isolation, a base, emitter, and collector formed in the first island region, and a lateral transistor formed in the second island region, and a reverse transistor. In a semiconductor integrated circuit device, the IIL includes a collector region of opposite conductivity type formed simultaneously with the emitter of the bipolar transistor and an injector region of one conductivity type formed simultaneously with the base of the bipolar transistor. and a base contact region formed to surround the collector region, and a well of one conductivity type that is lower in concentration than the base contact region, is deeper than the base contact region and does not reach the buried layer, and is formed immediately below the collector region. an inverse β of the IIL and an hFI of the bipolar transistor.
It is characterized by being controlled independently of I.
（ネ）作用
本発明によれば、ｈＦＥはベース領域（６）とエミッタ
領域（７）とで制御し、逆βはＰ−型ウェル領域（１４
）とコレクタ領域（１１）とで制御するので、逆βはｈ
ｏの制約を受けずに設定することができ、しかもＰ−型
ウェル領域（１４）は低濃度であるのでベース幅が犬で
も所望の逆βが得られる。ここでエミッタ領域（７）と
コレクタ領域（１１）とを同時に形成するのでｈＦ！を
コントロールすべくエミッタ領域（７）の拡散深さを増
減させるとコレクタ領域（１１）の拡散深さも変化する
が、実質的なベースであるＰ−型ウェル領域（１４）が
低濃度であることとベース幅が大であるので逆βはほと
んど変化しない。(f) Function According to the present invention, hFE is controlled by the base region (6) and emitter region (7), and the inverse β is controlled by the P-type well region (14).
) and the collector region (11), so the inverse β is h
It can be set without being subject to the restrictions of o, and since the P-type well region (14) has a low concentration, the desired inverse β can be obtained even if the base width is narrow. Since the emitter region (7) and collector region (11) are formed at the same time, hF! If the diffusion depth of the emitter region (7) is increased or decreased in order to control Since the base width is large, the inverse β hardly changes.
（へ）実施例
以下本発明による一実施例を図面を参照しながら詳細に
説明する。(F) Embodiment Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.
第１図は本発明による半導体集積回路を示し、（１）は
Ｐ型半導体基板、（２）はＮ−型エピタキシャル層、（
３）は基板（１）とエピタキシャル層（２）との間に埋
込まれたＮ＋＋埋込層、（４）はエピタキシャル層（２
）を貫通したＰ＋型分離領域、（５ａ）及び（５ｂ）は
分離領域（４）により島状に分離された第１及び第２の
島領域である。第１の島領域（５ａ）表面にはＰ型ベー
ス領域（６〉、Ｎ＋＋エミッタ領域（７）及びＮＩ型コ
レクタコンタクト領域（８）とが形成され、第１の島領
域（５ａ）をコレクタとし工通常ノＮ Ｐ Ｎ型バイポ
ーラトランジスタが構成されている。−実弟２の島領域
（５ｂ）表面には、Ｐ型インジェクタ領域（９）、Ｎ３
型コレクタ領域（１１〉、Ｎ＋型型底ミッタコンタクト
領域１２）、コレクタ領域（１１）を取り囲むように形
成したＰ型ベースコンタクト領域（１３）、少なくとも
コレクタ領域（１１）直下に形成したＰ−型ウェル領域
（１４〉とが形成され、インジェクタ領域（９）をエミ
ッタ、第２の島領域〈５ｂ）ヲベース、ベースコンタク
トｍ域（１３）及ヒＰ −型ウェル領域（１４）をコレ
クタとするラテラルＰＮＰ型トランジスタと、第５の島
領域（５ｂ）をエミッタ、Ｐ−型ウェル領域（１４）を
ベース、コレクタ領域（１１）をコレクタとする逆方向
のＮＰＮ型バーチカルトランジスタとでＩＩＬを構成し
ている。Ｐ−型ウェル領域（１４）はベースコンタクト
領域（１３）よりやや深く形成し、且つバイポーラトラ
ンジスタの耐圧（Ｖｃｘｏ）を維持するためにエピタキ
シャル層（２〉の厚さを比較的厚くしてＰ−型ウェル領
域（１４）が埋込層（３）に到達しない構造としである
。さらにＰ−型ウェル領域（１４）が実質的に逆方向バ
ーチカルトランジスタのベースとして動作するのでベー
ス幅が犬でも所望の逆βが得られるようにその不純物濃
度を十分に小としである。FIG. 1 shows a semiconductor integrated circuit according to the present invention, in which (1) is a P-type semiconductor substrate, (2) is an N-type epitaxial layer, (
3) is an N++ buried layer buried between the substrate (1) and the epitaxial layer (2), and (4) is the epitaxial layer (2).
), the P+ type isolation regions (5a) and (5b) are first and second island regions separated into islands by the isolation region (4). A P-type base region (6), an N++ emitter region (7), and an NI-type collector contact region (8) are formed on the surface of the first island region (5a), and the first island region (5a) is used as a collector. A normal N P N-type bipolar transistor is constructed. - On the surface of the island region (5b) of the younger brother 2, there is a P-type injector region (9), an N3
type collector region (11), N+ type bottom contact region 12), P type base contact region (13) formed to surround the collector region (11), P− type formed at least directly below the collector region (11). A well region (14) is formed, the injector region (9) is the emitter, the second island region (5b) is the base, the base contact m region (13) and the P-type well region (14) are the collectors. An IIL is constructed by a PNP type transistor and a reverse NPN type vertical transistor having the fifth island region (5b) as an emitter, the P-type well region (14) as a base, and the collector region (11) as a collector. There is. The P-type well region (14) is formed slightly deeper than the base contact region (13), and the epitaxial layer (2>) is made relatively thick to maintain the withstand voltage (Vcxo) of the bipolar transistor. The structure is such that the P-type well region (14) does not reach the buried layer (3).Furthermore, since the P-type well region (14) essentially operates as the base of the reverse vertical transistor, even if the base width is narrow, it can be used as desired. The impurity concentration is made sufficiently small to obtain the inverse β of .
次に本発明による半導体集積回路装置の製造方法を説明
する。先ず第２図（イ）に示す如く、予め埋込層（３）
となるべき領域にＮ型不純物をドープしたＮ１型ドープ
領域け５）を形成した半導体基板（１〉に気相成長法：
こよりＮ−型エピタキシャル層（２）を形成し、その表
面のＰ−型ウェル領域（１４）となるべき領域にＰ型不
純物、例えばボロン（Ｂ＋）をイオン注入してＰ−型ド
ープ領域（１６）を形成しておく。そしてさらに、エピ
タキシャル層（２）表面の分離領域（４）となるべき領
域にＰ型不純物をドープしてＰ＋型ドープ領域（１７）
を形成する。続いて第２図（ロ）に示す如く、Ｐ−型ド
ープ領域（１６）とＰ１型ドープ領域（１７）を同時に
熱拡散し、Ｐ＋型分離領域（４）とＰ−型ウェル領域（
１４）とを形成する。この時ドープしておいた不純物濃
度が異なるので拡散深許に差が生じ、分離領域（４）が
基板（１）に達するまで深く拡散してもＰ−型ウェル領
域（１４）はそれより浅く拡散される。また同時にＮｏ
ドープ領域（１４）も上下方向に拡散され、埋込層（
３）が形成される。そして第２図（ハ）に示す如く、選
択拡散にてＰ型のベース領域り６）、インジェクタ領域
（９）及びベースコンタクト領域（１２）を形成した後
、再び選択拡散にてリニアトランジスタのＮ＋＋エミッ
タ領域（７）、Ｎ＋＋コレクタコンタクト領域（８）、
ＩＩＬのＮ＋＋コレクタ領域（１１）、Ｎ＋型型底ミッ
タコンタクト領域１２）を形成し、各領域上に電極（図
示せず）を配設して終了する。Next, a method for manufacturing a semiconductor integrated circuit device according to the present invention will be explained. First, as shown in Figure 2 (a), the buried layer (3) is prepared in advance.
By vapor phase growth method:
From this, an N-type epitaxial layer (2) is formed, and a P-type impurity, such as boron (B+), is ion-implanted into the region on its surface that is to become a P-type well region (14) to form a P-type doped region (16). ). Furthermore, a region on the surface of the epitaxial layer (2) that is to become an isolation region (4) is doped with a P type impurity to form a P+ type doped region (17).
form. Next, as shown in FIG. 2(b), the P- type doped region (16) and the P1 type doped region (17) are simultaneously thermally diffused to form the P+ type isolation region (4) and the P- type well region (
14). Since the impurity concentration doped at this time is different, there is a difference in the diffusion depth, and even if the isolation region (4) is diffused deeply until it reaches the substrate (1), the P-type well region (14) is shallower than that. It will be spread. At the same time, No
The doped region (14) is also diffused in the vertical direction, forming a buried layer (
3) is formed. Then, as shown in FIG. 2(c), after forming the P-type base region 6), injector region (9) and base contact region (12) by selective diffusion, the linear transistor N++ is again selectively diffused. Emitter region (7), N++ collector contact region (8),
The IIL N++ collector region (11), N+ type bottom emitter contact region 12) are formed, and electrodes (not shown) are disposed on each region.
本発明の最も特徴とする点は、Ｐ−型ウェル領域（１４
）を設けることによりリニアトランジスタのｈｖｔとＩ
ＩＬの逆βとを独立して制御した点にある。すなわち、
リニアトランジスタのｈＦＥはベース領域（６）とエミ
ッタ領域（７〉とで制御され、ＩＩＬの逆βはＰ−型ウ
ェル領域（１４）とコレクタ領域（１１）により制御さ
れることになる。リニアトランジスタのエミッタ領域（
７）とｔＩＬのコレクタ領域（１１）とは同時に拡散形
成するが、この時Ｐ−型ウエル領域（１４）はリニアト
ランジスタのベース領域（６）より充分深いのでＩＩＬ
の逆βの変化はきわめて少ない。従ってＩＩＬの逆βは
リニアトランジスタのｈｌの制約を受けずに設定するこ
とができる。しかもＰ−型ウェル領域（１４）は低濃度
であるのでベース幅が大でも高い逆βが得られる。The most distinctive feature of the present invention is the P-type well region (14
), hvt and I of the linear transistor are
The point is that the inverse β of IL is controlled independently. That is,
The hFE of the linear transistor is controlled by the base region (6) and the emitter region (7), and the inverse β of IIL is controlled by the P-type well region (14) and collector region (11).Linear transistor The emitter area of (
7) and the collector region (11) of tIL are simultaneously formed by diffusion, but at this time, since the P-type well region (14) is sufficiently deeper than the base region (6) of the linear transistor, IIL
The change in the inverse β of is extremely small. Therefore, the inverse β of IIL can be set without being restricted by hl of the linear transistor. Moreover, since the P-type well region (14) has a low concentration, a high inverse β can be obtained even if the base width is large.
第３図は本発明による装置におけるリニアトランジスタ
のｈｒｍコントロール範囲を求めるための特性図である
。同図から明らかな如く、本発明ではリニアトランジス
タのｈＦＥとＩＩＬの逆βとを独立して制御しているの
で、ｈＦＥの変化に対してほぼ一定の逆βが得られ、且
つＩＩＬの逆ＶＣＩＩ。FIG. 3 is a characteristic diagram for determining the hrm control range of the linear transistor in the device according to the present invention. As is clear from the figure, in the present invention, since the hFE of the linear transistor and the inverse β of IIL are controlled independently, an almost constant inverse β can be obtained with respect to changes in hFE, and the inverse VCII of IIL is controlled independently. .
もｈＦＥの変化に対してほぼ一定の値を保っている。従
って従来と同様に逆ＶＣ１゜が満足する範囲を図示ＡＢ
、逆βが満足する範囲を図示ＣＤとすると、逆ｖ ｃｔ
ｏを満足し且つ逆βを満足する範囲は図示ＸＹの範囲と
従来より極めて広くなる。also maintains a nearly constant value with respect to changes in hFE. Therefore, as in the past, the range where the inverse VC1° is satisfied is shown in the diagram AB.
, if the range that satisfies the inverse β is the CD shown in the figure, then the inverse v ct
The range that satisfies o and satisfies the inverse β is the range of XY shown in the figure, which is much wider than the conventional range.
具体的には、従来のり、２コシトロール範囲が１５０〜
４００であったのに対し、本発明によれば６０〜８００
前後まで使用可能である。Specifically, the conventional glue has a 2-cositrol range of 150~
According to the present invention, it was 60 to 800.
Can be used before and after.
（ト）発明の詳細
な説明した如く、本発明によればＩＩＬの特性（逆β、
逆ＶＣｔ。）を満足するリニアトランジスタのｈＦＥの
範囲が非常に広くなるので、工程変動等によるばらつき
に強く、製造が容易になり、工程が安定するという利点
を有する。(g) As described in detail, according to the present invention, the characteristics of IIL (inverse β,
Reverse VCt. ), the range of hFE of the linear transistor that satisfies () becomes very wide, which has the advantage of being resistant to variations due to process fluctuations, facilitating manufacturing, and stabilizing the process.
第１図及び第２図は本発明を説明するための断面図、第
３図は本発明を説明するための特性図、第４図及び第５
図はそれ−ぞれ従来の装置を説明するための断面図、特
性図である。
主な図番の説明
（１）はＰ型半導体基板、（３）はＮ１型埋込層、（５
ａ）及び（５ｂ）は第１及び第２の島領域、（１１）は
Ｎ１型コレクタ領域、（１３）はＰ型ベースコンタクト
領域、（１４）はＰ−型ウェル領域である。
ス 琺
第３７
Ｏ
第５図
日1 and 2 are cross-sectional views for explaining the present invention, FIG. 3 is a characteristic diagram for explaining the present invention, and FIGS. 4 and 5.
The figures are a sectional view and a characteristic diagram, respectively, for explaining a conventional device. Explanation of main figure numbers (1) is P-type semiconductor substrate, (3) is N1-type buried layer, (5
a) and (5b) are first and second island regions, (11) is an N1 type collector region, (13) is a P type base contact region, and (14) is a P- type well region. 37th O Figure 5
Claims (1)
型のエピタキシャル層と前記基板表面に埋込まれた逆導
電型の埋込層と前記エピタキシャル層を分離して形成し
た第１及び第２の島領域と前記第１の島領域に形成した
ベース、エミッタ、コレクタより成る通常のバイポーラ
トランジスタと前記第２の島領域に形成したラテラルト
ランジスタと逆方向バーチカルトランジスタより成るＩ
ＩＬとを具備した半導体集積回路装置において、前記Ｉ
ＩＬは前記バイポーラトランジスタのエミッタと同時に
形成した逆導電型のコレクタ領域と前記バイポーラトラ
ンジスタのベースと同時に形成した一導電型のインジェ
クタ領域及び前記コレクタ領域を取り囲むように形成し
たベースコンタクト領域と該ベースコンタクト領域より
低濃度で少なくとも前記コレクタ領域直下に形成した前
記ベースコンタクト領域より深く且つ前記埋込層には達
しない一導電型のウェル領域とを備え、前記バイポーラ
トランジスタのｈ＿Ｆ＿Ｅと前記ＩＩＬの逆βとを独立
して制御したことを特徴とする半導体集積回路装置。(1) A semiconductor substrate of one conductivity type, an epitaxial layer of an opposite conductivity type formed on the substrate, a buried layer of an opposite conductivity type buried in the surface of the substrate, and a first semiconductor substrate formed by separating the epitaxial layer. A normal bipolar transistor consisting of a base, an emitter, and a collector formed in a second island region and the first island region, and an I consisting of a lateral transistor and a reverse vertical transistor formed in the second island region.
In a semiconductor integrated circuit device comprising an IL, the I
IL includes a collector region of opposite conductivity type formed simultaneously with the emitter of the bipolar transistor, an injector region of one conductivity type formed simultaneously with the base of the bipolar transistor, a base contact region formed so as to surround the collector region, and the base contact. a well region of one conductivity type formed at least at a lower concentration than the base contact region formed immediately below the collector region and not reaching the buried layer; A semiconductor integrated circuit device characterized in that independently controlled.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60206971A JPS6266658A (en) | 1985-09-19 | 1985-09-19 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60206971A JPS6266658A (en) | 1985-09-19 | 1985-09-19 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6266658A true JPS6266658A (en) | 1987-03-26 |
Family
ID=16532033
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60206971A Pending JPS6266658A (en) | 1985-09-19 | 1985-09-19 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6266658A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57128953A (en) * | 1981-02-02 | 1982-08-10 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor integrated circuit |
| JPS59141261A (en) * | 1983-01-31 | 1984-08-13 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit device |
-
1985
- 1985-09-19 JP JP60206971A patent/JPS6266658A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57128953A (en) * | 1981-02-02 | 1982-08-10 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor integrated circuit |
| JPS59141261A (en) * | 1983-01-31 | 1984-08-13 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4047217A (en) | High-gain, high-voltage transistor for linear integrated circuits | |
| US4038680A (en) | Semiconductor integrated circuit device | |
| US3445734A (en) | Single diffused surface transistor and method of making same | |
| US4272307A (en) | Integrated circuit with I2 L and power transistors and method for making | |
| US3595713A (en) | Method of manufacturing a semiconductor device comprising complementary transistors | |
| US5939769A (en) | Bipolar power transistor with high collector breakdown voltage and related manufacturing process | |
| US4319257A (en) | Low thermal coefficient semiconductor device | |
| US4564855A (en) | High current PNP transistor forming part of an integrated monolithic circuit | |
| US5481132A (en) | Transistor with a predetermined current gain in a bipolar integrated circuit | |
| US20040248389A1 (en) | Method of making semiconductor device | |
| US3510736A (en) | Integrated circuit planar transistor | |
| KR920010434B1 (en) | Semiconductor device having a bipolar transistor and iil | |
| JPS6266658A (en) | Semiconductor integrated circuit device | |
| JPS61113270A (en) | Based coupled transistor logic | |
| US5316964A (en) | Method of forming integrated circuits with diffused resistors in isolation regions | |
| JPS5917544B2 (en) | semiconductor integrated circuit | |
| JPS6133261B2 (en) | ||
| US4337475A (en) | High power transistor with highly doped buried base layer | |
| US4054900A (en) | I.I.L. with region connecting base of double diffused injector to substrate/emitter of switching transistor | |
| JPS6267853A (en) | Manufacture of semiconductor integrated circuit | |
| JP2587424B2 (en) | Method for manufacturing semiconductor integrated circuit device | |
| JP2716152B2 (en) | Lateral transistor | |
| JPH03116774A (en) | Manufacture of semiconductor device | |
| JPS60152062A (en) | Semiconductor device | |
| JPS5914670A (en) | Transistor |