JPS626642B2 - - Google Patents
Info
- Publication number
- JPS626642B2 JPS626642B2 JP52133693A JP13369377A JPS626642B2 JP S626642 B2 JPS626642 B2 JP S626642B2 JP 52133693 A JP52133693 A JP 52133693A JP 13369377 A JP13369377 A JP 13369377A JP S626642 B2 JPS626642 B2 JP S626642B2
- Authority
- JP
- Japan
- Prior art keywords
- epitaxial layer
- silicon epitaxial
- sapphire substrate
- silicon
- sapphire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 29
- 229910052710 silicon Inorganic materials 0.000 claims description 29
- 239000010703 silicon Substances 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 27
- 150000002500 ions Chemical class 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 238000001816 cooling Methods 0.000 claims description 2
- 239000012212 insulator Substances 0.000 claims 1
- 229910052594 sapphire Inorganic materials 0.000 description 23
- 239000010980 sapphire Substances 0.000 description 23
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 10
- 229910052786 argon Inorganic materials 0.000 description 5
- 239000012808 vapor phase Substances 0.000 description 3
- 230000005465 channeling Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052596 spinel Inorganic materials 0.000 description 2
- 239000011029 spinel Substances 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000007781 pre-processing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
Landscapes
- Recrystallisation Techniques (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Description
【発明の詳細な説明】
本発明は、サフアイアあるいはスピネル上にシ
リコン単結晶をエピタキシヤル成長したSOS構造
の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing an SOS structure in which silicon single crystal is epitaxially grown on sapphire or spinel.
SOSへテロエピタキシヤル成長は、たとえばモ
ノシラン（SiH4）を1000〔℃〕近傍の温度で熱分
解させて得られるシリコン（Si）を、たとえば面
指数（１012）のサフアイア基板上に積層させる
気相エピタキシヤル法によるのが一般的である。 SOS heteroepitaxial growth is a vapor phase method in which silicon (Si) obtained by thermally decomposing monosilane (SiH 4 ) at a temperature around 1000 [°C] is deposited on, for example, a sapphire substrate with a surface index of (1012). The epitaxial method is generally used.
ところで、シリコンの熱膨張率は2.5×10-6／
℃であり、サフアイアはＣ軸に平行で9.3×
10-6／℃、Ａ軸に平行で8.8×10-6／℃であり、
シリコンとサフアイアの熱膨張率が相違する。こ
のため、1000〔℃〕でサフアイア上にシリコンを
エピタキシヤル成長させたものを常温まで冷却さ
せると、上記熱膨張率の差のため、シリコンエピ
タキシヤル層に圧縮歪がかかり、その大きさは
10-3程度である。これを圧縮応力になおすと、
109〔dyne／cm2〕のオーダでかなり大きなもので
ある。このため、サフアイア上に成長させたシリ
コンエピタキシヤル層中の電子移動度（electron
mobility）が低下したり、移動度の異方性があら
われたり、該エピタキシヤル層上に形成した半導
体素子の性能低下をもたらす。 By the way, the coefficient of thermal expansion of silicon is 2.5×10 -6 /
℃, and the sapphire is parallel to the C axis and 9.3×
10 -6 /℃, parallel to the A axis is 8.8×10 -6 /℃,
Silicon and sapphire have different coefficients of thermal expansion. Therefore, when silicon is epitaxially grown on sapphire at 1000 [℃] and cooled to room temperature, compressive strain is applied to the silicon epitaxial layer due to the difference in thermal expansion coefficient, and the magnitude of the strain is
It is about 10 -3 . Converting this into compressive stress, we get
It is quite large, on the order of 10 9 [dyne/cm 2 ]. Therefore, the electron mobility (electron mobility) in the silicon epitaxial layer grown on sapphire is
This results in a decrease in mobility, an anisotropy in mobility, and a deterioration in the performance of the semiconductor device formed on the epitaxial layer.
本発明は、上述の如き従来の欠点を改善する新
規な発明であり、その目的はサフアイア等の絶縁
物基板上に成長させたシリコンエピタキシヤル層
の移動度を向上せしめることができるような方法
を提供することにある。 The present invention is a novel invention that improves the above-mentioned conventional drawbacks, and its purpose is to provide a method that can improve the mobility of a silicon epitaxial layer grown on an insulating substrate such as sapphire. It is about providing.
その目的のために、本発明のSOS構造の製法は
絶縁物基板上に高温下でシリコンエピタキシヤル
層を成長させて冷却した後、シリコンエピタキシ
ヤル層の上からイオンを注入し、絶縁物基板にダ
メツジ層を形成してシリコンエピタキシヤル層と
絶縁物基板間に生じた圧縮応力を解消せしめるこ
とを特徴とするもので、以下本発明をさらに詳細
に説明する。 To that end, the method for manufacturing the SOS structure of the present invention involves growing a silicon epitaxial layer on an insulating substrate at high temperatures, cooling it, and then implanting ions from above the silicon epitaxial layer into the insulating substrate. The present invention is characterized in that a damage layer is formed to eliminate compressive stress generated between a silicon epitaxial layer and an insulating substrate.The present invention will be described in more detail below.
所定の表面指数たとえば（１012）に切り出さ
れたサフアイア基板の表面を機械的研磨と化学的
研磨により平滑面とする。 The surface of a sapphire substrate cut to a predetermined surface index, for example (1012), is made smooth by mechanical polishing and chemical polishing.
表面を十分に平滑に研磨されたサフアイア基板
を気相エピタキシヤル装置のサセプタ上に載置し
た後、該装置に水素を満たす。次いで、100
〔℃／min〕の温度上昇率でサセプタの温度を
1300〔℃〕まで上昇させ、サフアイア基板を加熱
する。サフアイア基板を1300〔℃〕に15分間保持
してサフアイア基板の前処理を行なつた後、100
〔℃／min〕の率で温度を上げ、サフアイア基板
が1000〔℃〕に達したとき、その温度を保持した
ままSiH4の熱分解によるエピタキシヤル反応を
開始する。このエピタキシイにより、サフアイア
基板の上に（001）の面指数を持つたシリコンエ
ピタキシヤル層が成長する。 After a sapphire substrate whose surface has been polished sufficiently smooth is placed on a susceptor of a vapor phase epitaxial apparatus, the apparatus is filled with hydrogen. Then 100
The temperature of the susceptor is controlled at a temperature rise rate of [℃/min].
The temperature is raised to 1300 [℃] and the sapphire substrate is heated. After pre-processing the sapphire substrate by holding it at 1300 [℃] for 15 minutes,
The temperature is raised at a rate of [°C/min], and when the temperature of the sapphire substrate reaches 1000 [°C], the epitaxial reaction by thermal decomposition of SiH 4 is started while maintaining that temperature. Through this epitaxy, a silicon epitaxial layer having a plane index of (001) is grown on the sapphire substrate.
サフアイア基板上に所定の厚さだけシリコンエ
ピタキシヤル層を成長させたならば、エピタキシ
ヤル反応を中止し、100〔℃／min〕程度でサフ
アイア基板を徐冷して常温にまで冷却する。 After a silicon epitaxial layer has been grown to a predetermined thickness on the sapphire substrate, the epitaxial reaction is stopped and the sapphire substrate is slowly cooled at about 100 [° C./min] to room temperature.
次いで、気相エピタキシヤル装置からサフアイ
ア基板を取り出した後、図に示す如く、シリコン
エピタキシヤル層１上からこのシリコンエピタキ
シヤル層１に向つてほぼ垂直に例えばアルゴン
（Ar）イオンを打ち込む。 Next, after taking out the sapphire substrate from the vapor phase epitaxial apparatus, argon (Ar) ions, for example, are implanted almost vertically from above the silicon epitaxial layer 1 toward the silicon epitaxial layer 1, as shown in the figure.
シリコンエピタキシヤル層１に打ち込まれたア
ルゴン（Ar）イオンは、チヤンネリング効果に
よりその大部分がサフアイア基板２に達し、シリ
コンエピタキシヤル層１と接しているサフアイア
基板２表面直下にダメツジ層３が形成される。 Most of the argon (Ar) ions implanted into the silicon epitaxial layer 1 reach the sapphire substrate 2 due to the channeling effect, and a damage layer 3 is formed directly below the surface of the sapphire substrate 2 that is in contact with the silicon epitaxial layer 1. Ru.
ダメツジ層３は、アルゴン（Ar）イオンの注
入によりデイスロケーシヨンが発生する。そし
て、そのスベリによりシリコンエピタキシヤル層
１とサフアイア基板２との間に生じている圧縮応
力が解消される。 Dislocation occurs in the damage layer 3 due to implantation of argon (Ar) ions. Then, due to the sliding, the compressive stress occurring between the silicon epitaxial layer 1 and the sapphire substrate 2 is eliminated.
実施例
面指数（１012）を持つたサフアイア基板を前
処理した後、エピタキシイを行なつて0.6〔μ
ｍ〕の厚さを持つたシリコンエピタキシヤル層を
形成した後、アルゴン（Ar）イオンを100
（KeV）のエネルギーで２×1016cm-2だけシリコ
ンエピタキシヤル層に対して垂直に注入する。そ
してシリコンエピタキシヤル層を完全にチヤンネ
ルしたアルゴン（Ar）イオンにより、サフアイ
ア基板にダメツジ層を形成せしめて圧縮応力を解
消せしめた。前述の如き処理を行なつた後のシリ
コンエピタキシヤル層の移動度（mobility）は電
子で600cm2／v.secであつた。Example: After pretreatment of a sapphire substrate with a surface index (1012), epitaxy was performed to obtain a surface index of 0.6 [μ
After forming a silicon epitaxial layer with a thickness of 100 m], argon (Ar) ions were
A dose of 2×10 16 cm -2 is implanted perpendicularly to the silicon epitaxial layer at an energy of (KeV). Using argon (Ar) ions that completely channeled the silicon epitaxial layer, a damage layer was formed on the sapphire substrate to eliminate compressive stress. The mobility of the silicon epitaxial layer after the above-described treatment was 600 cm 2 /v.sec for electrons.
なお、本発明は、サフアイア基板の代わりに、
スピネル基板を用いたSOS構造にも適用できるこ
とはいうまでもないことである。 In addition, in the present invention, instead of the sapphire substrate,
Needless to say, this method can also be applied to an SOS structure using a spinel substrate.
以上詳細に説明したように、本発明は、常温に
保持したSOS構造の絶縁基板とシリコンエピタキ
シヤル層間に生じている圧縮応力を、チヤンネリ
ング効果を利用した絶縁基板へのイオン注入によ
り解消せしめることができるので、従来のSOS構
造に比べて移動度の大きいシリコンエピタキシヤ
ル層を得ることができ、このため、特性のよい半
導体素子をSOS構造の上に作ることができるよう
になつた。 As explained in detail above, the present invention can eliminate the compressive stress occurring between the insulating substrate of the SOS structure kept at room temperature and the silicon epitaxial layer by implanting ions into the insulating substrate using the channeling effect. As a result, it is possible to obtain a silicon epitaxial layer with higher mobility than in the conventional SOS structure, and as a result, it has become possible to fabricate semiconductor devices with good characteristics on the SOS structure.
なお、本発明において、イオン注入の際、シリ
コンエピタキシヤル層内でデチヤンネルしたイオ
ンによるダメツジが生じるが、このダメツジは非
常に少さなものであつて、イオン注入した後の軽
いアニーリングにより完全に修復できるものであ
る。 In the present invention, during ion implantation, damage occurs due to dechanneled ions in the silicon epitaxial layer, but this damage is very small and can be completely repaired by light annealing after ion implantation. It is possible.
図は本発明に係るSOS構造の断面図である。図
中、１はシリコンエピタキシヤル層、２はサフア
イア基板、３はダメツジ層である。
The figure is a cross-sectional view of an SOS structure according to the present invention. In the figure, 1 is a silicon epitaxial layer, 2 is a sapphire substrate, and 3 is a damage layer.
Claims (1)
ヤル層を成長させて冷却した後、シリコンエピタ
キシヤル層の上からイオンを注入し、絶縁基板内
にダメツジ層を形成してシリコンエピタキシヤル
層と絶縁物基板間に生じた圧縮応力を解消せしめ
ることを特徴とするSOS構造の製造方法。1 After growing a silicon epitaxial layer on an insulating substrate at high temperature and cooling it, ions are implanted from above the silicon epitaxial layer to form a damage layer in the insulating substrate, and the silicon epitaxial layer and insulator are bonded together. A method for manufacturing an SOS structure characterized by eliminating compressive stress generated between substrates.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13369377A JPS5466767A (en) | 1977-11-08 | 1977-11-08 | Manufacture for sos construction |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13369377A JPS5466767A (en) | 1977-11-08 | 1977-11-08 | Manufacture for sos construction |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5466767A JPS5466767A (en) | 1979-05-29 |
| JPS626642B2 true JPS626642B2 (en) | 1987-02-12 |
Family
ID=15110659
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13369377A Granted JPS5466767A (en) | 1977-11-08 | 1977-11-08 | Manufacture for sos construction |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5466767A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6376872A (en) * | 1986-09-18 | 1988-04-07 | Agency Of Ind Science & Technol | Method for relieving internal stress of film |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5038838A (en) * | 1973-08-02 | 1975-04-10 | ||
| JPS5056184A (en) * | 1973-09-03 | 1975-05-16 | ||
| JPS518869A (en) * | 1974-07-09 | 1976-01-24 | Mitsubishi Electric Corp | HANDOTAIEPITAKI SHARUEHANO SEIZOHOHO |
-
1977
- 1977-11-08 JP JP13369377A patent/JPS5466767A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5038838A (en) * | 1973-08-02 | 1975-04-10 | ||
| JPS5056184A (en) * | 1973-09-03 | 1975-05-16 | ||
| JPS518869A (en) * | 1974-07-09 | 1976-01-24 | Mitsubishi Electric Corp | HANDOTAIEPITAKI SHARUEHANO SEIZOHOHO |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5466767A (en) | 1979-05-29 |
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