JPS6266293A - Digital effect apparatus - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a digital effect device in which at least a major part thereof is configured using a digital circuit.

[Background of the invention]

A variety of so-called effectors have been developed in the past that add various effects to musical instrument sounds to produce sounds that are quite different from the original sound.
Many use elements such as BD,! It had drawbacks such as a poor 13/N ratio. In addition, in recent years, devices have been developed that have a digital memory called a digital delay device, into which a waveform signal is written and read out after a delay time, but the output signal is monotonous, so this is not desirable. It wasn't.

[Purpose of the invention]

The present invention has been made in view of the above points, and it is an object of the present invention to provide a digital effect device that can add various effects to input original sound.

[Key points of the invention]

This invention was made to achieve the above-mentioned object, and it converts an input waveform signal into a digital signal,
Feedback means is provided to once write the digital signal into the waveform memory means, read out the written digital signal, combine it with a digital signal obtained by converting the input waveform signal, and write the synthesized signal into the waveform memory means, The key point is that the output digital signal of this waveform memory means is converted into an analog signal to produce an acoustic output.

〔Example〕

Hereinafter, the present invention will be described using an external sound signal as P CM (Pulse
An example will be described using an electronic musical instrument having a so-called sampling function that can perform modulation such as CodedModulation, digitally record it, and use it as a sound source signal for a keyboard instrument.

FIG. 1 shows the circuit configuration of this embodiment, and shows the input signal (IN
) is suitably amplified by the input amplifier 1 and then supplied to the filter 3 where unnecessary high-frequency components are suitably removed.
The signal is sampled by a sample/hold circuit (S/H) 5 at an appropriate sampling frequency and supplied to an A/D converter 6.

The A/D converter 6 converts the input analog signal into a corresponding digital signal and supplies it to the sound generation control section 8.

This sound generation control section 8 includes, for example, four waveform read/write channels, each of which can independently write or read waveform signals into or from the waveform memory 7.

The sound generation control section 8 operates under control from a CPU 9 consisting of a microcomputer, etc., and corresponds to the four waveform readout/convolution channels of the sound generation control section 8, the details of which will be described later. Digital signals corresponding to up to four tones are read out from the waveform memory 7 in a time-divisional manner and applied to the D/A converter 10 in a time-divisional manner, and then sent to the sample and hold circuit (S/H). 11a
~11 dK is supplied.

The sample and hold circuits 11a to 11lid perform sampling operations for each time-division processing channel time in response to timing signals t, to t, and K, which will be described later.

The voltage signals held in the sample and hold circuits 11a-lid are supplied to VCFs (voltage controlled filters) 128-12d in a corresponding manner. Each of the VCFs 12a to 12d has a voltage signal FC, which will be described later.
VI~FCV4 is supplied, and this voltage signal FCVI~F
Filtering processing is performed independently according to CV4.

The VCFs 12a to 12d send filtered analog waveform signals to VCAs (voltage controlled amplifiers) 13a to 13d.

The amplification factors of the VCAs 13a to 13d are independently controlled by the supplied control voltage signals ACV1 to ACV4, and the output level or volume envelope of the waveform signals supplied from the VCFs 12a to 12d is determined.

The output signals of the VCAs 13a to 13d are sent out to the outside as outputs 0UT1 to 0UT4 of each channel, respectively, and after being amplified appropriately, are emitted as sound signals. Further, the outputs of the VCAs 13a to 13d are supplied to an analog adder circuit 14, mixed, and can be outputted to the outside as a mixed output OUTMIX.

Reference numeral 4 in the figure denotes a keyboard/display unit which also includes a keyboard with performance keys and various control switches, a liquid crystal display panel, etc. that displays various statuses, and the CPU 9 and this keyboard/display unit 4 are used to display data. Give and receive.

Further, this CPU 9 performs the above-mentioned 1. through software processing.
f, -Each mJ M number FCV1-FCV4. ACV1~A
supplying a digital signal to the D/A converter 17 to generate CV4 (hereinafter collectively referred to as control signal Cv);
It is converted into respective voltage signals.

This D/A converter group 17 may have a number of D/A converters corresponding to the number of control signals C, or one D/A converter may be used in a time-sharing manner. , in combination with a sample-and-hold circuit, the required number of control signals C■
You may obtain .

Next, the detailed circuit configuration of the sound generation control section 8 will be explained using FIG. 2.

The digital signal supplied from the A/D converter 6 is supplied to the gate 81 via the adder 93, and then supplied to the waveform memory 7 as well as to the D/A converter 10 via the gate 82. Sent out. The output of gate 82 is also supplied via a latch 94 to an adder 93 through a feedback loop.

A read/write signal R/W generated from a control circuit (not shown) inside the sound generation control unit 8 is supplied to the gate 81 based on a control command generated by the CPU 9.
Opening/closing control is performed.

That is, when writing the waveform memo IJ7K waveform signal, this gate 81 is opened, and when reading the waveform signal from the waveform memory 7, this gate 81 is closed.

The gate 82 also receives a gate signal G◆te from an opening/closing signal generator 83 based on a control signal from a control circuit.
is given, and this gate 82 is opened only when outputting the digital signal supplied via the gate 81 or when outputting the digital signal read out from the waveform memory 7. In other cases, this gate 82 is opened. Gate 82 is closed and its output is set to zero level.

A shift operation is performed using a master clock φ, which will be described later. This address register 84 operates in a time-sharing manner as a four-channel address register, and the contents of the final stage are stored in the waveform memory 7.
The read/write signal R is a waveform signal supplied as address data to
A digital signal is written to the memory address only when /W is at a low level, and a digital signal is read from the memory address when the read/write signal R/Wb is at a high level from the waveform memory 7.

Further, the contents of the address register 84 are as follows: Gate B5
In addition to being supplied to the eight switching signal generators, the signal is also supplied to a control circuit (not shown).

The address signal via the gate 85 is supplied to an adder 86, and after addition and subtraction are performed to perform address processing as necessary, it is fed back to the address register 84.

Further, an initial address (CA) is supplied to this adder 86 from the control circuit via a gate 87.

That is, the load signal LD is directly supplied to the gate 85,
The initial address (CA) from the control circuit is inverted and applied to the gate 87 via an inverter 88, and when the load signal LD is at a LOW level, the initial address (CA) from the control circuit is supplied to the adder 86 by opening the gate 87. On the other hand, if the load signal LD is at high level, the gate 85
is opened and the contents from address register 84 are provided to adder 86.

Reference numeral 89 in FIG. 2 is a pitch register, which is composed of a four-stage shift register like the address register 84, and a shift operation is performed by a master clock φ. Then, pitch data specifying a rate corresponding to the write/read speed trap for the waveform memory 7 is input from the control circuit to this pitch register 89 via a gate 90 . It is cyclically held and output to the adder 86.

That is, when writing pitch data from the control circuit to the pitch register 89 via the gate 90, the load signal LDP
is set to Low level and inverted by the inverter 92,
The signal is applied to the gate 90, causing the gate 90 to open.

In addition, in the normal state, the gate 91 is opened to open the gate 91.
1, the load signal LDP is set to High level and supplied.

Then, the pitch data and address register 8
The address data stored in 4 has data below the decimal point, and addresses of the waveform memory 7 are specified using data above the decimal point. Therefore, if the pitch data has exactly the size of "1", the contents of the address register 84 will be subjected to child l processing every time the data of the corresponding channel is input to the adder 86, and the content will be "1". If it is above, the address sidewalk speed becomes faster, and if it is less than "1", the address sidewalk speed becomes slower. During normal performance, pitch data corresponding to the musical scale frequency is input to the pitch register 89.

Furthermore, by changing the content of the pitch data in the pitch register 89 over time, the step speed of the address data changes over time, making it possible to obtain a musical tone signal with frequency modulation, for example, a vibrato effect. .

Reference numeral 95 in FIG. 2 is a quaternary counter that counts by the master clock φ1, and the address register 8
4. Count up every channel time of the pitch register 89, that is, every shift operation time of the shift register.

Therefore, its contents specify the channel.

This quaternary counter 95 is supplied to a comparator 96 and compared with channel data (CD) stored in a latch 97. Note that the channel data is stored in the latch 97 as the load signal 5LI)! When the low level is busy, it is supplied from a control circuit (not shown) and latched.

Then, from the comparator 96, for each channel time corresponding to the channel data latched in the latch 97,
A high level signal is output, and the latch timing of the latch 94 is determined by this signal.

Therefore, among the digital signals read out from the waveform memory 7 by processing each channel, only the digital data of the designated channel is fed back and sent to the adder 93 on the input side, and the delayed signal is fed back with the original sound signal and supplied. After digitally synthesizing the signals, the waveform memory 7
and the D/A converter 1 via the 1 gate 82.
It will now be sent to 0.

FIG. 3 shows how the waveform memory 7 is divided into areas, so that, for example, N pieces of waveform information can be recorded in variable lengths.

Next, the operation of this embodiment will be explained. FIG. 4 shows the relationship between the time division processing state of multiple channels of the sound generation control section 8 and the timing signals 1.-1. supplied to the sample/hold circuits 11a to 11 (1). In this embodiment, four waveform read/write channels are realized in a time-division configuration, and each waveform read/write channel performs read processing or write processing.
In the state shown in FIG. 4, where processing can be selectively specified, the processing of channel 1 (chi) stores the filter 3, sample/hold circuit 5, and A/D converter in the waveform memory 7. It is summed to write the waveform signal obtained through channel 6, and the other channels 2 to
4 (ch2-4) can read digital waveform signals in a predetermined area from the waveform memory 7.

Further, the above-mentioned timing signals t1 to t4 take a high level at times corresponding to the respective channels (chi to 4), and D/
5, the analog waveform signal output from the A converter 10 is sampled by the sample/hold circuits 11a to 11d and thereafter held.

In addition, each waveform read/write channel of the sound generation control section 8 is
It is possible to specify the area to be read and written independently. For example, on channel 2.3.4, read tone 1.2.3 in Fig. 3,
~12d, VCA 13b ~, 13d may be used to control the processing and output sound.

Next, the operation of this embodiment when used as a digital effect device will be described with reference to FIGS. 5 and 6.

First, assuming that the area used in the waveform memory 7 for performing this operation is from addresses n to m as shown in FIG.
9, load signal LDP with a value of “1” for each channel.
input to the address register 84 shown in FIG. 2 as the initial address for channel 1 (chl).
h2), for example, n-1, channel 3 (c
h3), for example, n-3, channel, +1/4 (
ch4), input n-6, for example.

That is, as shown in FIG. 5, the load signal LD is set to Low level for one cycle of channels 1 to 4, and the initial address (CA) is n-1 for channel 1 and n-1 for channel 2. 2, n-4 for channel 3, n for channel/I/4
-7 is input, the adder 86 performs +1 processing, and the above-mentioned respective values are set as address data.

Then, for channel l, the digital signal from the A/D converter 6 is sequentially written into the waveform memory 7.
Set the above read/write signal R/W to Low level,
The other channels 2 to 4 are configured to read the read/write signal R/W from the waveform memory 7 so as to read out the digital signal written in the waveform memory 7 immediately before in the channel 1.
Set W to High level.

Further, the opening/closing signal generating device t83 generates a gate signal Gate that always opens the gate 82 at the timing of channel 1, and for other channels 2 to 4,
The gate 82 is opened only when the address register 84 specifies an address after address n shown in FIG.

As a result, due to the operation of channel 1, the waveform memory 7 has wave height values f(n), f(n+t
), f(n+2), .
The signal is converted into an acoustic signal and output as sound through the F12a and VCA13a.

In addition, in channel 2, as shown in FIG.
After T (T=4x channel time), the data is read from the waveform memory 7, and similarly, in channel 3, it is read out over a 3T delay, and in channel /I/4, it is read out over a 6T delay.

That is, each channel 2 to 4 has an initial address (CA
), the D/A converter 10 outputs a digital signal corresponding to the peak value shown in FIG.
Send to.

As a result, the waveform signals of channels 2 to 4 are VCF 1
2 b - 12 dl VCAI 3 b - 13 d are outputted, and can also be outputted as an acoustic output by performing tone and volume control different from the waveform signal of channel 1, which is the original sound.

Below, channel 1 writes the waveform signal supplied via A/D converter 6 to waveform memory 7, channel 2 shifts the time by IT, channel 3 shifts the time by 3T, and channel 4 shifts the time by IT. The time is shifted by 6T, and the four sounds are read out from the waveform memory 7, respectively, and four sounds are generated simultaneously. When the address data reaches address m of the waveform memory 7 in FIG. 6, the initial address is changed to n-1. By re-inputting the waveform signal and writing a new waveform signal from address n of the waveform memory 7 in channel 1, and reading it out in channels 2 to 4, K Become.

Then, the control circuit presets the latch 97 with channel data (CD) specifying one of channels 2 to 4.

As a result, the digital signal of the designated channel is read out from the waveform memory 7 and applied to the latch 94 for each channel time, and is applied to the adder 93.

Therefore, the digital signal representing the original sound supplied via the A/D converter 6 and the digital signal read out after adding a delay of a predetermined time to the waveform memory 7 are added by the adder 93. It becomes a digital output of channel 1 (chl), and its contents are supplied to and stored in the waveform memory 7, and used for reading other channels (ch2 to ch4).

As mentioned above, if the delay time of channel 2 (ch2) is IT, the delay time of channel 3 (ch3) is 3T, and the delay time of channel 4 (ch4) is 6T, if latch 97 Channel data (CD) specifying channel/I/2
is supplied, the waveform memory 7 records a digital signal representing the original sound and a sound obtained by delaying the original sound by 2T time, and similarly, channel data specifying channel 3 is sent to the latch 97. When a (CD) is supplied, a digital signal representing the original sound and a sound delayed by 3T time is supplied, and when channel data (CD) specifying channel 4 is supplied, a digital signal representing the original sound and a sound delayed by 6T time is supplied. The digital signal to be represented will be stored in the waveform memory 7.

In addition, in the above explanation, all 4 channels are operated,
Although generation is possible at four volumes, fewer channels may be selectively operated to output the original sound and one or more delayed sounds.

Furthermore, in the above description, the delay times of channels 2, 3, and 4 for channel 1 are set to 1T13T and 6T, but they can be specified using the keyboard/display unit 4, respectively.

As described above, in this embodiment, multiple waveform readout and
While writing the waveform signals in the waveform memory 7 using the write channel, they were read out with a delay of a predetermined time each, and one of the waveform signals was synthesized with the waveform signal that is the original sound and stored in the waveform memory 7. Since it is output after the output, a delay effect with feedback looseness can be achieved.

In addition, for each waveform read/write channel, VCF 12
Since the timbre and volume are independently and variably controlled using VCAI 3a to 13d, even more effective sound can be obtained.

In the above embodiment, the original sound signal outputted through the gate 82 is passed through the latch 9 without changing its amplitude level.
4 was latched and applied to the adder 93, but
For example, by providing a multiplier or a level shifter that multiplies a predetermined amplification factor between the gate 82 and the latch 94 and making the amplification factor of the sound obtained by feedback smaller than the original sound, a reverberation effect can be obtained, and the feedback If the amplification factor of the resulting sound is made comparable to that of the original sound, a ring-singing effect can be obtained.

Further, in the above embodiment, at least two
One of the digital signals read out by the channel is fed back and digitally synthesized with the original sound signal, but it is also possible to feed back multiple digital signals obtained using multiple channels, each with a different delay time. Alternatively, the signal may be combined with the original sound signal and written into the waveform memory 7.

Furthermore, in the embodiment described above, VCFs 12a to 12
d. Although the timbre and volume are controlled variably using VCAI 3a to 13d, it is also possible to perform variable control of the timbre and volume using digital filters, digital multipliers, etc. .Furthermore, other processing may be performed on the waveform signal.

In addition to the circuit configuration of the sound generation control unit 80, which configures a plurality of waveform read/write channels by time-sharing processing as in the above embodiment, the circuit configuration is a separate ))-ware, that is, the same circuit configuration for the number of channels. A plurality of waveform read/write channels may be provided by using a plurality of waveform read/write channels.

Furthermore, a specific channel among multiple channels,
A write-only channel may be used to write the waveform signal into the waveform memory 7, and other channels may be used as read-only channels to read the waveform signal from the waveform memory 7. In the present invention, the term "waveform read/write channel" means either a channel that performs either reading or writing, or a channel that allows both operations.

Further, although the above embodiments apply the present invention to an electronic musical instrument having a sampling function, it goes without saying that the present invention can be realized as a digital effect device having a dedicated circuit configuration.

〔Effect of the invention〕

As described above, this invention realizes a digital effect device with a simple circuit configuration, so it is inexpensive, and moreover, the input waveform signal is converted into a digital signal, and the digital signal is written once in the waveform memory means. , feedback means is provided for reading out the written digital signal, combining it with a digital signal obtained by converting the input waveform signal, and writing it into the memory means, and converting the output digital signal of the waveform memory means into an analog signal. Since the sound is converted into an audio output, it is musically preferable and allows for a variety of performance forms.

[Brief explanation of drawings]

The drawings show one embodiment of the present invention, and FIG. 1 is a diagram of its overall circuit configuration, FIG. 2 is a detailed circuit diagram of the sound generation control section 8, and FIG.
4 is an explanatory diagram of the basic operation of this embodiment. FIG. 5 is a diagram showing a time chart when operating as a digital effect device. FIG. 5 is a diagram for explaining the operating state of FIG. 5. FIG. 6... A/D converter, 7... Waveform memory, 8...
Sound generation control unit, 9...CPU, 10...D/A converter, 12a to 12d-VCF, 13a to 13d-=VCA
. 81.82, 85, 87, 90.91...gate, 8
4...Address register, 86...Adder, 89.
... Pitch register, 93 ... Adder, 94 ... Latch, 95 ... Quaternary kakuunta, 96 ... Comparator, 9
7...Latch.

Claims (8)

[Claims] (1) Convert the input waveform signal into a digital signal, write and store the digital signal in a waveform memory means, read out the digital signal written in the waveform memory means, convert it into an analog signal, and then obtain an acoustic output. In the digital effect device, the digital signal written in the waveform memory means is read out and digitally synthesized with the digital signal obtained by converting the input waveform signal,
A digital effect device characterized in that it is provided with feedback means for writing into the waveform memory means. (2) Two or more digital signals are read out with a predetermined time difference from the waveform memory means by at least two waveform read/write channels, and the feedback means is configured to read out two or more digital signals with a predetermined time difference from the waveform memory means. 2. The digital effect device according to claim 1, wherein at least one digital signal of said input waveform signal is digitally synthesized with a digital signal obtained by converting said input waveform signal. (3) A digital signal obtained by converting the input waveform signal is converted into an analog signal together with a digital signal obtained by reading from the waveform memory means, and is used as an acoustic output. The digital effect device according to item 1 or 2. (4) The feedback means includes variable setting means capable of variably setting the delay time when the digital signal is read from the waveform memory means by the at least two waveform read/write channels. A digital effect device according to claim 2. (5) Processing means for performing predetermined processing on the digital signal read from the waveform memory means for each of the plurality of waveform read/write channels to independently control variables such as timbre and volume. A digital effects device according to claim 2, characterized in that it has the following. (6) The processing means has a circuit means consisting of a voltage-controlled filter and a voltage-controlled amplifier corresponding to the plurality of waveform read/write channels, and converts the read digital signal into an analog signal. 6. The digital effects device according to claim 5, wherein after being converted, the digital effects are supplied to the circuit means for each channel so that timbre and volume can be controlled independently. (7) The readout speed at which the digital signal is read out from the waveform memory means by the at least two waveform read/write channels is changed over time, so that the output sound is frequency-modulated. A digital effect device according to claim 2, characterized in that: (8) The digital signal is read from the waveform memory means by the at least two waveform read/write channels in a different manner for each waveform read/write channel. The digital effect device according to item 2.