JPS6265375A - Semiconductor thin-film transistor and display device provided with it - Google Patents

Abstract

PURPOSE:To increase the transconductance of a thin-film transistor or a planar panel display device consisting of a thin-film transistor, a capacitor and a display element, and to enable the transistor or the display unit to have, without compromising, quickly responding capability and high packaging density, by providing grooves on the principal surface of the insulating substrate in the source to drain direction. CONSTITUTION:A thin-film transistor according to the invention includes an insulating substrate 1 of glass having grooves arranged in the source to drain direction, a semiconductor layer 2 of polysilicon for providing a channel region, and a source electrode 3, a gate electrode 4 and a drain electrode 5 of the thin-film transistor. The thin-film transistor further includes a gate insulation film 6 of silicon dioxide, the principal surface of the insulating substrate or regions parallel to the principal surface 13 and inclined face regions 14 of the grooves in the substrate. According to such construction, the channel region defined by the inclined faces 14 can be utilized more effectively in comparison with a conventional semiconductor thin-film transistor having the same planar dimensions, and the effective width of the channel is increased. Consequently, the transconductance can be increased.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a high-performance semiconductor thin film transistor and a display device using the same. [Prior Art] The structure of a conventional thin film transistor on a transparent glass substrate is It is shown in μ diagram to FIG. 6. Figure μ is a plan view, and Figure 3 is A. A
0/ direction, and FIG. 6 is a sectional view in the B, B,' directions. In the figure, l is a transparent glass substrate, λ is a semiconductor layer typified by a silicon thin film forming a channel region, 3 is a source electrode, ≠ is a gate electrode, j is a drain electrode, and 6 is a gate insulating film.

As described above, a conventional thin film transistor is formed on the flat main surface of a transparent glass substrate, and the effective channel width matches the width (W) of the semiconductor thin film. Therefore, in order to increase the mutual conductance (fm) of the transistor, it is necessary to increase the channel width (W), and in this case, the planar dimension increases, making it unsuitable for high density.

On the other hand, the main application of semiconductor thin film transistors is the second
This is an application as a flat display panel device in which a display element and a transistor are integrated on the same transparent substrate to drive a display element (for example, a liquid crystal cell) as shown in the figure.

Figure 2 is an equivalent circuit diagram of a flat display panel device, Figure 1O is a plan view showing the specific configuration of one pixel of the display panel device, and 20 is a thin film transistor 1.23 for driving a liquid crystal display element. A liquid crystal display element, 21I- is a scanning line, 2j is a signal line, and 27 is a reference line. One electrode of the liquid crystal display element 23 is connected to either the drain or the source of the thin film transistor 20, and the other electrode is connected to the reference line core.

In the above configuration, the thin film transistor 2 is connected to the scanning line 2≠.
When a voltage that turns on the thin film transistor λO is applied, the thin film transistor λO turns on, and a pressure of Kt is applied to the liquid crystal display element 27. Note that FIG. 70 shows a specific plan configuration diagram of pixels of the flat display panel shown in FIG. 2. However, the reference line 27 and the like are omitted.

In such conventional flat display panel devices, the various performances required of the thin film transistors used therein were not strict; for example, for mutual conductance, a low value determined by the packaging density was sufficient. . The reason for this is that it is sufficient that the display element to be driven by the transistor is a liquid crystal element with a low field mutual conductance (fm).

Furthermore, in the case of liquid crystal elements, there is a kind of memory effect in which the molecular orientation is maintained for a long time even when the power is turned off.
Unlike the case of a flat display panel device using a BL element shown in FIGS. 1 and 72, which will be described later, as shown in FIG.
Since one pixel was configured, the planar dimensions of the thin film transistor had little effect on the mounting density of the display device. From this point of view, conventional materials have a high mutual conductance value,
There is little need for semiconductor thin film transistors that can be mounted at high density, and therefore no one has been proposed.

[Problem that the invention seeks to solve]

However, flat display panel devices using the above-mentioned liquid crystal elements have low response speed and low trust because they use liquid crystals, and require an external light source, making them unsuitable for high-performance display panel devices. There has been an increasing demand for luminescent elements (EL* elements) to be round when used as display elements. Here, when driving a liquid crystal element and an EL element with a thin film semiconductor transistor, the conditions required for the transistor are compared in typical cases in Table 7.
become that way.

As mentioned above, when driving the RL element,
The transconductance (pm) needs to be about 7 orders of magnitude higher. K, which increases mutual conductance, can be obtained by changing the material of the semiconductor layer from amorphous silicon to polysilicon (polycrystalline silicon), which has high carrier mobility, but it is not possible to increase mutual conductance by an order of magnitude by selecting the material alone. First, it is necessary to increase mutual conductance from a structural standpoint. However, in order to increase mutual conductance while maintaining the conventional structure, it was necessary to increase the channel width at the expense of packaging density (planar dimensions).

SUMMARY OF THE INVENTION In view of these conventional drawbacks, it is an object of the present invention to provide a semiconductor thin film transistor with increased mutual conductance while reducing packaging density.

[Means for solving problems]

The present invention provides a semiconductor thin film transistor formed on an insulating substrate, in which a groove is provided in the main surface on the channel side of the insulating substrate in one source/drain direction, and a side surface of the groove is also provided.
The method is characterized by forming a gate insulating film and a gate electrode.

Furthermore, the present invention is characterized in that the semiconductor thin film transistor having the above structure is used as a driving transistor for an electroluminescent (EL) element that requires high mutual conductance (pm). The main difference from conventional semiconductor thin film transistors is that the main surface of the insulating substrate has grooves extending in one source/drain direction.

[For production]

In the present invention, a groove is provided in the source/drain direction on the main surface of the insulating substrate, and a gate insulating film and a gate electrode are also formed on the side surfaces of the groove. Because it is tilted or upright, the width of the cross section perpendicular to the direction connecting the source and drain directions, that is, the effective channel width, can be increased compared to the conventional structure parallel to the main surface. Since the planar dimension increases only by the projection of the side surface onto the main surface, the mounting tightness hardly decreases.

That is, the effective channel width can be increased without reducing the packaging density, and therefore the transconductance value (Pm) can be increased.

〔Example〕

FIG. 1 is a diagram for explaining the planar structure of the thin film transistor of the present invention, and FIG.
'), and FIG. 3 is a sectional view taken in the BB direction of FIG. 1. However, the angle between the slope indicated by /4L in FIG. 2 and the main surface may be any angle including a vertical angle. For this reason, the first
In the plan view of the figure, the projected area of the slope onto the main surface is not shown.

In these drawings, / is an insulating substrate typified by glass having grooves in the source/drain direction, λ is a semiconductor layer typified by polysilicon (polycrystalline silicon) K forming a channel region, and 3 is a thin film transistor. The source electrode, Hiroshi is the gate electrode, Y is the drain electrode, B is the gate insulating film represented by silicon dioxide, 13 is the main surface of the insulating substrate or a part parallel to the main surface, /≠ is the groove of the insulating substrate Shows the slope of the area. Further, W indicates the width of the groove, and D indicates the depth of the groove.

Because of this structure, compared to a semiconductor thin film transistor having the same planar dimensions, the channel portion formed on the sloped surface can be used more effectively, so the effective channel width can be increased, and therefore the mutual conductance can be increased.

Here, the mutual conductance of the thin film transistor due to the main surface of the substrate or a portion parallel to this is defined as (Pm)1,
If the mutual conductance of the groove slope is (Pm)1,
The mutual conductance of the seven grooves is ('m)=(fmh+2(rm)B).

In addition, when n grooves are formed, (fm)1 = n(Pm)1 + 2n(Pm)s. If the slope of the groove is perpendicular to the main surface, the above equation, 2n(Pm)1 is the increase in mutual conductance compared to the conventional structure without grooves.

On the other hand, as shown in Figure 2, when the slope is not perpendicular to the main surface, the conventional structure (Pm) to be compared is calculated by adding the conductance value based on the dimension of the slope projected onto the main surface. There is a need. In this case, the gentler the inclination angle of the slope, the smaller the difference from the conventional structure. In this way, in the present invention, the dimensions and cross-sectional shape of the grooves are arbitrary, but K
It is preferable that the width (W) and the depth D) are approximately the same, or the depth D) is larger than @(W).

Next, a method for manufacturing a semiconductor thin film transistor having such a structure will be described.

First, a resist pattern is formed on an insulating substrate, typically a glass substrate, using known photolithography technology, and then wet or dry etching is performed using this as a mask to etch the glass substrate and form tiles. do. Typical dimensions of the groove are width (W) from submicron to /
, about 0 μm, depth D) is submicron ~ O1! μm
It is.

Next, polysilicon (polycrystalline silicon) is formed as a semiconductor layer (2) which will become one channel region by the same photolithography technique and thin film formation technique.

As a thin film forming technique, any of low pressure OVD, atmospheric pressure CVD, or vapor deposition using an electron beam or sputtering can be used. Note that the film thickness is 0. /~/, about 0 μm.

Next, a gate insulating film (6) is formed in the same way.◎The material of the gate insulating film is Ss', +81BN4+T
It is an absolute R film such as a205. The manufacturing method may be box oxidation of the semiconductor layer (2), low pressure OVD, normal pressure OVD, or sputter deposition. In addition, the membrane pressure is j00~3ooo
It is about 'h.

Finally, the source, drain, and gate electrode patterns are formed using photolithography and vapor deposition techniques. Aluminum is generally used as the material for the electrodes, and is formed by electron beam evaporation or sputter evaporation.

FIG. 7 compares the mutual conductance value (fm) of the thin film transistor of the present invention produced in this way and the thin film transistor of the conventional structure. In addition, in these transistors, the planar dimension of the channel is 70
0 μm + channel length is 702 m, gate voltage V
. is 2~3V + source/drain voltage■. , is 60V. Also, the semiconductor layer is polysilicon (polycrystalline silicon)
was used, and its thermal oxide film (Sin) was used. The width of the groove is 0.7 μm.

Also, the depth of the groove is 0.3 μm and 0.3 μm. Considering J-μm 2 and Oshi, the number of grooves is 20. ≠QI
I experimented with 6Q book. As is clear from the experimental results shown in FIG. 7, it is possible to increase the mutual conductance value (1 m) by increasing the number of grooves. In addition, as shown in the same figure, by applying microfabrication technology on the order of submicron, 7
It can be seen that by forming 00 or more grooves, it is possible to easily increase the Pm value to more than three times that of the conventional structure.

Further, as a result of examining other parameters required for a transistor for driving a display element, the element withstand voltage VBD was approximately 1 tzv as shown in FIG. Also, experiments were conducted with the gate length being j/mm and 30 μm, but the results were almost the same as the conventional structure.

Furthermore, as a result of measuring the leakage current when the transistor is OFF, the leakage current density is almost the same as that of the conventional structure (approximately / 0
According to the above results, the structure of the present invention can increase the mutual conductance of semiconductor thin film transistors without impairing other performances or increasing the mounting area. It is clear that it can be done.

Next, with reference to FIGS. 1) to 13), an embodiment of a flat display panel device using an EL element using the thin film transistor of the present invention as a display element will be described.

FIG. 1 is a general equivalent circuit diagram of a flat display panel device using BL cables. Here, 20 is a thin film transistor for switching, 2/ is a thin film transistor for driving a display element, 22 is a capacitor for holding a signal voltage, and 23 is an E
It is an L display element. 2≠ is a scanning line, C is a signal line, 2 is a power line, and 27 is a reference line.

In addition, FIG. 73 is a plan view showing the configuration of one pixel of the flat display panel shown in FIG. 1, and FIG.
A typical plan view when using the element is shown. Further, FIG. 12 shows a typical plan view in the case where an electroluminescent (EL) element is used as a display element, a thin film transistor of a conventional structure is used, and K is adjusted to increase mutual conductance. Further, FIG. 13 is a plan view of a flat display panel device for an EL element using the thin film transistor of the present invention which can achieve a mutual conductance value equal to that of FIG. 12.

The operation will be explained using an equivalent circuit diagram of a flat display panel device using EL elements shown in FIG. 1. Here, KO is a thin film transistor for switching, 2/ is a thin film transistor for driving a BL element, 22 is a capacitor for holding a signal voltage, and 2 is a thin film transistor for driving a BL element.
3 is an EL element, 21I is a scanning line, Cj is a signal line, Ct is a power supply line, and λ7 is a reference line. One electrode of the EL element 23 is connected to either the drain/source of the thin film transistor 21, and the other electrode of the EL element 3 is connected to the power line 2B. A reference line 27 is connected to either the drain or the source of the thin film transistor 2/, and is connected to the thin film transistor 2 through the capacitor 22.
The signal line 2 is connected to the gate of the thin film transistor,
Thin film transistor 2 is connected between the drain and source of 20.
/ is connected to the gate of scanning line 24! is connected to the gate of thin film transistor 〇.

In the above configuration, when a voltage that turns on the thin film transistor O is applied to the -scanning line 2, the thin film transistor O turns on, the capacitor -λ is charged, and the terminal voltage of the signal line λ! When the voltage is equal to the voltage, the thin film transistor 2/ is also turned on, and the alternating current voltage of the power line -B is applied to the EL element 3, causing the BL element 23 to emit light.

FIG. 7λ shows a planar configuration for one pixel, and the /Jj channel width is about 1)00p. In addition, the aperture ratio of one pixel is approximately!
OJ-20
Therefore, the display density was φ~j pieces/basket. On the other hand, with the technology disclosed by the present invention, K, a thin film transistor, a capacitor, and a BL as a display element can be formed on the main surface of the same substrate.
In a flat panel display device in which elements are integrated,
By providing a groove in the insulating substrate directly below the channel of the thin film transistor, the mutual conductance of the thin film transistor can be increased without increasing the planar dimensions of the transistor. This is effective in increasing the packaging density of devices.

FIG. 73 shows an example in which a value equal to the mutual conductance (about /μs) of the thin film transistor in the first λ diagram can be achieved with a channel width of about 30 μm. In the case of FIG. 13, the size of one pixel is approximately 100 .mu.m.times.02 m0, and therefore the display density is 7.times.10.times.02 m0. As a result of measuring the performance of the EL display device prototyped in this way,
Packaging density: Approximately 70 pieces/ *I contrast) 100
: / or more, response speed: 2 to 3 μs, drive voltage: approx.
OVrms - consumption per pixel is about 2x/QW and has high performance.

The performance of the high-density L display device was confirmed, and the effects of the present invention were verified.

〔Effect of the invention〕

As explained above, according to the present invention, grooves in the source-drain direction are provided in the main surface of the insulating substrate of a flat display panel device consisting of a thin film transistor or a thin film transistor, a capacitor, and a display element. ), the mutual conductance of transistors can be increased without reducing packaging density. As a result, since it is a current-driven element, it is difficult to apply it to a flat display panel device using an electroluminescence (EL) element, which requires high mutual conductance for driving. A high-performance display device that can achieve both high packaging density can be realized.

[Brief explanation of drawings]

FIG. 1 is a plan view of a semiconductor thin film transistor according to the present invention, FIG. 2 is a partially enlarged cross-sectional view (aa') in the AA' direction of FIG. 7, and FIG. cross section,
Fig. μ is a plan view of a conventional semiconductor thin film transistor, Fig. 2 is a partially enlarged sectional view (between bb') in the AoAo direction of Fig. Fig. 7 is a diagram comparing the mutual conductance of a conventional example and a semiconductor thin film transistor of the present invention, Fig. 7 is a diagram showing the device breakdown voltage measurement results of a semiconductor thin film transistor of the present invention, and Fig. 2 is a flat display panel using liquid crystal. The equivalent circuit diagram of the device, Figure 1O is a representative example of a plan view of one pixel of the display device shown in Figure 1. Figure 1) is an equivalent circuit diagram of a flat display panel device using gL, Figure 12 73 is a plan view of one pixel of the display device shown in FIG. 1, which is a typical example in which a BL element is used as a display element and a conventional structure is used as a transistor. 1 is a plan view of one pixel of a shaped display panel device, and is a typical example when an EL element is used as a display element. l...Insulating substrate, Co...Semiconductor layer, 3...Source electrode, ≠...Gate electrode, j...Drain electrode,
6... Gate insulating film, /3... Area parallel to main surface of insulating substrate, /4... Side surface of groove provided in insulating substrate, 20°2/, /20. /,2/,,2.20.22/
...Semiconductor thin film transistor, 22. /22,222
...Capacity, 23...Liquid crystal display element, /koj, 2.
23...EI, display element, 2≠ν/, 2 hats 22 Hiro...
・Scanning line, Ko! , /coj, cocoj...signal line, 26.
/JA, 22 Otsu...Power line, 27. / 27p co27
...Reference line.

Claims (4)

[Claims] (1) A semiconductor thin film transistor in which a semiconductor layer, a gate insulating film, and a gate electrode are stacked on the main surface of a substrate made of an insulator, and a source electrode and a drain electrode are provided connected to both ends of the semiconductor layer, 1. A semiconductor thin film transistor comprising: an insulating substrate; at least one groove is formed below a gate electrode in a direction connecting the source electrode and the drain electrode. (2) The semiconductor thin film transistor according to claim 1, wherein the insulating substrate is transparent. (3) In a display device in which a display element, a capacitor, a first thin film transistor for switching, a second thin film transistor for driving the display element, and a wiring layer are formed in pixel units on the main surface of a substrate made of an insulator. , the first and second thin film transistors have a semiconductor layer, a gate insulating film, and a gate electrode stacked on the main surface of an insulating substrate, and have a source electrode and a drain electrode connected to both ends of the semiconductor layer. A display device characterized in that the semiconductor thin film transistor is a semiconductor thin film transistor in which at least one groove is formed under the gate electrode of the insulating substrate in a direction connecting the source electrode and the drain electrode. (4) The display device according to claim 3, wherein the insulating substrate is transparent.