JPS6265374A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To inhibit the short channel effect and to provide a highly integrated circuit in forming a layer having the same type conductivity as a substrate, by implanting first ion species which can provide a P-N junction between the substrate and a layer having the opposite type of conductivity to that of the substrate at a shallow position, and implanting second ion species which provides a peak of concentration profile at a position deeper than that of the first ion species. CONSTITUTION:A gate oxide film 14 and a field oxide film 16 are provided on an N-type substrate 10. P, As and BF2 ions are then implanted in the substrate subsequently in that order. The implantation processes are controlled such that P ions are implanted at an accelerating voltage of 200kV in a does of 5X10<12>cm<-2>. As a result of such ion implantations, the P-N junction is located at a depth of 0.08mum from the boundary between the gate oxide film and the Si substrate. Further, the maximum P concentration is found at a depth of 0.25mum and the maximum As concentration is found at a depth of 0.14mum.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention provides a method for forming a channel by using a layer having a conductivity type opposite to that of a substrate and a layer having the same conductivity type as the substrate located below the layer having the opposite conductivity type. The present invention relates to a method for manufacturing a MOS type semiconductor device in which a portion is formed, and particularly to a method suitable for forming a fine transistor.

[Technical Background of the Invention and Problems of the Background Art] A conventional manufacturing method will be explained using a PMOSI-run master as an example.

FIG. 10 is a cross-sectional view showing an MO5 type transistor,
This transistor has an N-type substrate 10, a channel portion 11, a source 17, a drain 18, a gate oxide film 14, and a gate electrode 15. In order to suppress punch-through and short channel effects between the source and drain, an N-type region 12 is formed in the channel part 11 by ion implantation of P, and the impurity concentration is higher than that of the substrate, and the threshold voltage of the transistor is adjusted. Therefore, the weak P wall region 13 formed by B ion implantation is formed vertically, and as a result, a PN junction (indicated by a broken line) is formed in the channel portion.

Conventionally, in order to form such a MOS t-run master, as shown in Fig. 11, first ions of P are implanted to form a highly doped N-type region (Fig. 1(a)), and then the threshold voltage of the transistor is adjusted. B is ion-implanted for adjustment (see figure (
b)).

On the other hand, in order to increase the integration density of integrated circuits, it is necessary to shorten the gate length of the transistor, but as the gate length of the transistor becomes shorter, the so-called short channel effect occurs, where the voltage of the transistor decreases as the gate length decreases. become noticeable. That is, for example, as shown in FIG. 12, when the gate length becomes 1.5 μm or less, the threshold voltage ■1□ decreases significantly due to the short channel effect.

In order to suppress the short channel effect, it is necessary to make the PN junction in the channel portion shallow. To this end, it is conceivable to use, for example, ion species that have a short range during ion implantation. FIG. 13 shows a MOS fabricated using As, which has a shorter range during ion implantation than P, to form the N-type region 12, and BF2, which has a shorter range than 8, to form the P wall region 13.
This is the impurity concentration distribution in the channel part of the type semiconductor device, and B
and As are impurity distributions produced by ion implantation of BF2 and A3, respectively. Furthermore, FIG. 14 shows the dependence of VlH on gate length. As shown in the figure, the short channel effect is suppressed by 2.1, but v1!1 decreases when Go1-Good becomes 1 μm or less. Also the 15th
The figure shows punch-through voltage■. is shown as a function of gate length. As shown in the figure, the punch-through voltage vp has a gate length of 1.
It gradually decreases from around 3 μm, and rapidly decreases below 1 μm, where the short channel effect becomes noticeable.

When an integrated circuit is manufactured using the conventional method, the VTH of the transistor changes greatly due to a slight deviation in the gate length, and a certain integrated circuit, which is a set of many transistors T'', may not operate properly. Also, punch-through voltage decreases and leakage current increases.

In this way, conventional methods miniaturize transistors and
It is difficult to achieve high integration of integrated circuits.

Furthermore, in a semiconductor device having a concentration distribution as shown in FIG. 13, the impurity concentration of a region containing B as an impurity is As
The impurity concentration is significantly higher than the impurity concentration in the region containing as an impurity, resulting in a decrease in the subthreshold characteristics of the transistor and an increase in leakage current. Furthermore, the junction depth of the source and drain is 0.2 to 0.3 μm in the example shown in the figure.
), the concentration in region 12 is higher than the impurity concentration in A8
This increases due to ion implantation, which increases scattering due to impurities and reduces the current driving ability of the transistor.

(Object of the Invention) An object of the present invention is to provide a manufacturing method capable of suppressing the short channel effect, which is a problem in fine semiconductor devices, and achieving higher integration of integrated circuits.

[Summary of the invention]

In forming a layer of the same conductivity type as the substrate among the layers forming the PN junction in the channel part, the present invention provides a first ion species capable of shallowing the PN junction with a layer of the opposite conductivity type to the substrate, and A second ion species in which the peak of the distribution is deeper than that of the first ion species.
It is characterized by ion implantation of ion species.

[Embodiment of the Invention] FIG. 1 shows an ion implantation process in an embodiment of the invention. As shown in the figure, in this embodiment, an N-type substrate 10, a gate oxide film 14, a field oxide film 1
After forming 6, P, A, BF2 are formed in this order (same figure (a)
), (b), (C)) Perform ion implantation. Accelerating voltage and dose m are 5 x 1, P is 200 Kv, respectively.
012ax-2, A is 160KV, 2X 10 0
1. BF2 is 45KV.

4, 5x 1012 cta-2.

FIG. 2 shows the impurity concentration distribution obtained as a result of one such ion. In the same figure, B (BF2 >, A,
P indicates the concentration distribution of B, A8, and P produced by ion implantation of BF2 and AsP, respectively.

The broken line represents a concentration distribution curve that would occur if only A5 (as an impurity forming a conductive type layer of the substrate) was ion-implanted without P ion-implanting.

As shown in the figure, the PN junction position is located at a depth of 0.08 μm from the boundary between the gate oxide film and the Si substrate.

Moreover, the PI3 degree reaches its maximum at a depth of 0.25 μm, and the Asaa degree reaches its maximum at a depth of 0.14 μm.

FIG. 6 shows the threshold voltage v1 of PMO3 formed according to this example.
11. Figure 7 shows the dependence of punch-through voltage V on gate length. As is clear from this figure, according to the present invention, no drop in punch-through voltage occurs down to 0.5 μm, and no decrease in ■Tl+ due to the short channel effect occurs.

Further, as is clear from FIG. 2, 815 degrees and As11 degrees are made almost equal, and as a result, the subthreshold characteristics of the transistor are improved compared to the conventional example, and leakage current can also be suppressed to a low level.

Furthermore, the peak value of the AS concentration in FIG. 2 is 0.3 μm1. :As a result of making the concentration of TA lower than the concentration of P, the driving force of the transistor increases.

Note that even if the ion species are the same, the concentration distribution, and therefore the PN junction, can be changed by changing the accelerating voltage.

Figure 3 shows the method shown in Figure 1, with an acceleration voltage of Δ8 of 12
The concentration distribution is shown when the voltage is 0 KV and other conditions are the same. In the same figure, B (BF2), A8, and P are each BF.
,,,A5. 8, A8. caused by P ion implantation. P
shows the concentration distribution of As shown, the PN junction is shallower and steeper than in the case of FIG. As a result, the subthreshold characteristics of the transistor can be further improved.

The present invention also provides a method for forming an N-type channel in a P-type substrate.
It can also be applied to 1 go. For example, FIG. 4 shows a P-type substrate 2
An NMOS transistor is formed by forming an N+ type source, drain 27° 28, and channel part 21 on the transistor 0, and further includes a field oxide film 26, a gate oxide film 24, and a gate electrode 25. The present invention can also be applied to this case. That is, in this case as well, the channel portion 21 is formed of a layer 22 of the same conductivity type as the substrate and a layer 23 of the opposite 891 type, and the gate'! P-type polycrystalline silicon is used as the 1K25 material. In forming the channel portion, for example, ions of B, BF2, and AS are implanted in this order. The acceleration voltage and dose ring are B = 50V and V, respectively.
3, OX 1012cm', BF 100Kv, 1
,0X-1012as-2,A is 50v,1,
5x 1012as-2. In this embodiment, A is ion-implanted to adjust the threshold voltage of the transistor. As a result of such ion implantation, a concentration distribution as shown in FIG. 5 was obtained.

In the same figure, As, B (BF2), and B (B) are △5 and △5 caused by ion implantation of A, BF2, and B, respectively.
The concentration distribution of B and B is shown. Moreover, the broken line is the concentration distribution of 8 assuming that B ion implantation is not performed.

Further, FIGS. 8 and 9 are diagrams showing the gate length dependence of the threshold voltage "TH" and the punch-through voltage V of NMO3 in the above embodiment.As shown in the figures, according to the present invention, NMO3
In No. 3 as well, the decrease in punch-through voltage and the decrease in threshold voltage are suppressed to 0.5 μm.

Furthermore, in the above embodiment, by using ion species A3 and BF2, both of which have short ranges, in the channel portion of NMOS, the junction in the channel portion of NMO3 can be made shallow, resulting in subthreshold characteristics. , it becomes possible to improve the current driving force.

In each of the above embodiments, polycrystalline silicon was used as the gate electrode material, but metals such as MO and W or silicides thereof may also be used. Further, in the above embodiment, BF2 is used as the ion species of B, but B with low acceleration energy, G, I, etc. may be used instead. Furthermore, the order of ion implantation in each embodiment is not limited to this embodiment, and the order can be changed. By including a thermal process or the like to increase the activation rate of the I4 compound, the retran master characteristics can be further improved.

(Effects of the Invention) As described above, according to the present invention, the gate length is 0.5 μm.
Even with the following transistors, it is possible to manufacture a transistor in which the punch-through voltage does not decrease and the short channel effect is suppressed.

Therefore, by applying the present invention to the manufacture of integrated circuits, it is possible to manufacture 0M08 circuits with gate lengths of 0.5 μm or less, and the degree of integration of integrated circuits can be dramatically increased.

[Brief explanation of drawings]

FIGS. 1(a) to (C) are process diagrams showing a manufacturing method according to an embodiment of the present invention, FIGS. 2 and 3 are diagrams showing impurity concentration distribution according to an embodiment of the present invention, and FIG. 5 is a schematic cross-sectional view showing an NMOS transistor manufactured according to the present invention, FIG. 5 is a diagram showing the impurity concentration distribution in the channel part of the NMOS transistor of FIG. 4, and FIGS. 8 and 9 are graphs showing the gate length dependence of the threshold voltage V1- and the punch-through voltage V of the PMOS transistor manufactured according to the embodiment of the present invention. A diagram showing the gate length dependence of the threshold voltage VTH and the punch-through voltage ■, FIG. 10 is a schematic cross-sectional view showing a PMOS transistor,
FIGS. 11(a) and (b) are process diagrams showing the conventional manufacturing method, and FIG. 12 is a l.
Diagram showing gate length dependence of threshold voltage of run master, 1st
Figure 3 is a diagram showing the impurity concentration distribution by other conventional manufacturing methods, and Figures 14 and 15 show the gate length dependence of the threshold voltage and punch-through voltage of transistors manufactured by the other methods mentioned above. It is a line diagram. 10.20...Substrate, 11.21...Channel part,
12.22...Substrate and conductivity type layer, 13.23...
Layer of conductivity type opposite to substrate, 14.24... Gate oxide film, 15.25... Gate electrode, 16.26... Field oxide film, 17.27... Source, 18.28...
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Claims (1)

[Claims] 1. A MOS type semiconductor in which a channel portion is constituted by a layer having a conductivity type opposite to that of the substrate and a layer having the same conductivity type as the substrate and located below the layer having the opposite conductivity type. In the device manufacturing method, when forming a layer of the same conductivity type as the substrate, a first ion species capable of shallowing a PN junction with the layer of the opposite conductivity type is implanted, and the peak of the concentration distribution is 1st
1. A method of manufacturing a semiconductor device, comprising implanting a second ion species deeper than impurities. 2. The method according to claim 1, wherein the layer of opposite conductivity type is formed by ion implantation. 3. The method according to claim 2, wherein the substrate is of N type, and the ion species for forming the layer of the same conductivity type as the substrate are As and P. 4. The method according to claim 3, wherein the ion species for forming the layer of opposite conductivity type is B. 5. The method according to claim 4, wherein the ion species for forming the layer of opposite conductivity type is BF_2. 6. The method according to claim 2, wherein the substrate is of N type, and the ion species for forming a layer of the same conductivity type as the substrate are BF_2 and B. 7. The method according to claim 6, wherein the ion species for forming the layer of opposite conductivity type is As. 8. The method according to claim 7, wherein the ion species for forming the layer of opposite conductivity type is P.