JPS6265117A - Method for processing abnormality of power supply of information processor - Google Patents

Abstract

PURPOSE:To restart easily the normal processing when a power supply is recovered even in case the abnormality of the power supply is detected owing to a service interruption or the distortions of an AC waveform, by securing the information of a storage. CONSTITUTION:A check circuit 2 detects a service interruption and delivers a power supply abnormality signal 9. While a voltage checking circuit 4 detects the drop of the DC voltage level and delivers a reset signal 11. An interruption is applied by the signal 9 and a program of a ROM601 is run for processing the abnormality of the power supply. When the abnormality of the power supply is processed after output of the signal 9, a retry point, the important data, etc. are saved in a battery back-up area 603 before the DC voltage has a drop, that is, before the signal 11 is delivered. In this case, an initial program is stored in the ROM601 and therefore never broken by the drop of the DC voltage. Thus, no initial program loading action is needed after the power supply is recovered.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for handling a power supply abnormality such as a power outage in an information processing apparatus such as a terminal device having a battery-backed storage device.

[Background of the invention]

Conventionally, countermeasures against power failures such as power outages in information processing equipment have been taken, for example, by Nidward, M., Howell, William, author of "A New Dawn of Checkout Management".
E. Kinslow (commercial industry) and HITAC program product 1-V033/SP system generation 80
As described in Japanese Patent Application No. 90-3-614-10, it is common practice to provide an auxiliary power source such as a generator or battery, and automatically switch to the auxiliary power source in the event of a power outage to survive an emergency. In other words, this is all about backing up the entire device with an auxiliary power source so that it can withstand not only instantaneous power outages but also long-term power outages.

Although this method is most suitable for large-scale computing systems whose downtime due to power outages is widespread, it is not suitable for application to terminal devices such as PoS because it increases costs.

FIG. 3 shows the hardware configuration of a terminal device, etc., which does not have an auxiliary power source for the entire device.

In Fig. 3, 1 is a general commercial power source (AC),
The input AC voltage 8 is converted into a DC voltage IO via a power supply device 13 such as a switching regulator. This DC voltage lO is a logic device! ! 5 and the storage device 6 as power. Storage device i! 6 includes read-only memory (ROM) 601, random access memory (RAM) 602, and battery memory 64.
There is a RAM 603 backed up by . Reference numeral 2 denotes a check circuit for checking the AC voltage 8 from the commercial power supply 1, which monitors whether or not a peak voltage is occurring at the cycle of the power supply frequency, and outputs a power supply abnormality signal 9 when it no longer occurs. Power supply abnormality signal 9 is.

This becomes an interrupt signal for the logic device t5, and interrupts and interrupts the process currently being executed. 4 is a check circuit that checks the voltage level of the DC voltage lO, and the DC voltage lO is a logic circuit! i! 5, the reset signal 11 is sent to the logic device 5.
Output.

FIG. 4 is a time chart showing the relationship between the AC voltage 8, the DC voltage 10, the power supply abnormality signal 9, and the reset signal 11.

When the supply of AC voltage 8 from commercial electricity g1 is stopped due to a power outage, one periodic peak voltage is no longer output, and time T,
After the time has elapsed, the check circuit 2 detects this and outputs a power supply abnormality signal 9.

At this time, the DC voltage 10 is held up by the container of the power supply 3, so the voltage level does not drop immediately. ! After a time T2 elapses after the power supply abnormality signal is output, the voltage level of the DC voltage 10 decreases, the check circuit 4 detects this, and the reset signal 11 is output. The reset signal 11 is also output when the power is normally turned on. The logic unit [5 is reset by the reset signal 11, and thereafter, if the DC voltage 10 is determined, the normal processing routine is executed from the beginning.

In the above process, the time T2 from when the power supply abnormality signal 9 is output to when the reset signal 11 is output is generally guaranteed to be at least 20 to 301 seconds. Within that time, it is necessary to save the try point after the power is restored and the necessary data therefor in a non-volatile memory (RAM 603 in FIG. 3) by program within that time. The setting of retry points, retry methods, and the like are well-known techniques, especially in large-scale computer systems.

However, i! In terminal equipment such as PoS, which does not have a dedicated power source equipment but is shared with other electrical equipment and is fed with general commercial power, instantaneous power outages may occur due to alternating current waveform distortion due to momentary overload. Despite the high frequency of equipment failures due to power outages caused by lightning strikes, etc., there is a strong demand for the timeliness and reliability of the information handled, and short-term recovery in the event of a failure is essential. Therefore,
Information processing devices having large capacity battery-backed storage devices including a program area are emerging. This storage device uses a large-capacity semiconductor memory.

However, in conventional information processing apparatuses, if a power outage occurs during the execution of a process and the DC voltage drops, the stored information in the program storage area in which the process is being executed is not guaranteed. This is a characteristic of semiconductor memory, and even if the DC voltage is backed up by a battery, a series of memory access operations, whether reading or writing, is interrupted and the information in the semiconductor memory is extensively destroyed. By being done. This illegal memory access operation occurs because a logic device that is not backed up by a battery is reset during memory access by a reset signal caused by an unexpected drop in DC voltage. However, complicated and expensive hardware is required to output five reset signals in synchronization with memory access operations. Further, if a drop in DC voltage is predicted when a power supply abnormality is detected and the logic device is held (stopped) in advance, operator intervention will be required even when recovering from a momentary power failure.

[Purpose of the invention]

An object of the present invention is to guarantee the information in the storage device in an information processing device such as a terminal device that has a battery-backed storage device even if a power supply abnormality is detected due to a power outage or AC waveform distortion. An object of the present invention is to provide a power supply abnormality handling method that allows normal processing to be easily restarted when power is restored.

[Summary of the invention]

In conventional information processing devices, it is difficult to guarantee the information stored in the storage device in the event of a power failure such as a power outage. This is due to the fact that the memory access signal from the logic device to the storage device interrupts a series of prescribed operations due to a drop in DC voltage. Therefore, information cannot be guaranteed even in a storage device made of a battery-backed semiconductor memory. As a countermeasure to this problem, it is possible to hold (stop) the logical device as soon as a power failure is detected, but it is necessary to stop the logical device including direct memory access transfer, and the timing to hold it is difficult, and it is difficult to hold the logical device when the power is restored. Sometimes, operator intervention is required to get it running again. Therefore, in the present invention, memory access after a power abnormality is detected is limited to the non-battery backup area, thereby guaranteeing storage information in the battery backup area without holding the logical device.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. FIG. 1 is a flowchart of power supply abnormality processing according to the present invention, and FIG. 2 shows area allocation of a storage device.

When the power is turned on, the initial program load (IP
L) is executed in the ROM 601, which is a non-battery backup area of the storage device 6, and at this time, the power supply abnormality processing program is also loaded. Next, the logical device 5 is initialized (INIT) L and normal processing is started. During normal processing, all areas of the storage device 6 are freely accessed. Note that direct memory access (
Since it is difficult for DMA) to stop memory access by hardware or software, the RAM 602, which is a non-battery backup area, is used as the access area.

When a power outage occurs, the check circuit 2 detects this and outputs a power abnormality signal 9, and after a predetermined period of time, the voltage check circuit 4 detects a drop in the DC voltage level and outputs a reset signal 1.
1 (see Figure 4).

An interrupt is triggered by the power supply abnormality signal 9, and the power supply abnormality processing program in the ROM 601 runs. In the power supply abnormality processing after the power supply abnormality signal 9 is output, retry points, important data, etc. are backed up by the battery of the storage device 6 before the DC voltage drops, that is, before the reset signal 11 is output. Save in area 603.

Thereafter, the ROM 601 in the non-battery backup area executes time monitoring and the like to determine whether it is an instantaneous power outage or a power outage.

Note that this may be executed in the RAM 602 instead of the ROM 601.

If the reset signal 11 does not arrive even after a predetermined period of time has elapsed, it is determined that there is an instantaneous power outage, and the process returns to normal processing. When the reset signal 11 arrives, the logic device 5 is reset and waits for the power to be restored. When the power is restored, the logical device 5 is initialized to the state before the power outage and processing is restarted. The initial program is in ROM6 of storage device a6.
01, it will not be destroyed by a drop in DC voltage, and an IPL operation is not required after the power is restored.

As described above, according to this embodiment, the storage information destruction area caused by a power supply abnormality can be limited to a narrow range.

If the use of this destroyed area is limited to, for example, only the DMA buffer area, the recovery process after the power is restored can be easily completed by re-executing the DMA process that was being executed at the time of the power failure.

〔Effect of the invention〕

According to the present invention, since the storage information in the battery backup area can be guaranteed, there is no need for data saving processing for backup, initialization program loading (IPL) after power restoration, loading backup data, etc. In addition, since the point of return to normal processing can be set immediately before the occurrence of a power failure, it is possible to minimize the need for manual intervention for recovery, and to complete the recovery process in a short time. I can do it.

[Brief explanation of the drawing]

FIG. 1 is a flowchart explaining one embodiment of the present invention;
FIG. 2 is a diagram illustrating memory area allocation according to the present invention, FIG. 3 is a diagram illustrating a configuration example of an information processing device targeted by the present invention, and FIG. 4 is a time chart illustrating power failure processing according to the prior art. It is. l...AC power supply, 2...check circuit. 3...Power supply device, 4...Check circuit, 5...
-Logic device, 6...Storage device, 601...Read-only memory, 602...Random access memory, 603...Random access memory, 604...Battery, 7
...Memory access signal, 8...AC voltage,
9... Power supply abnormality detection signal, 10... DC voltage,
11...Reset signal. (To-゛) Representative Patent Attorney Katsuo Ogawa, Yan 17i

Claims (1)

[Claims] (1) A storage device consisting of a power supply device that inputs AC voltage and outputs DC voltage, a logic device that operates in response to the DC voltage, a storage area that operates in response to the DC voltage, and a battery-backed storage area. a first check circuit that detects an abnormality in the AC voltage and outputs a power supply abnormality signal to the logic device; and a second check circuit that detects an abnormality in the DC voltage and outputs a reset signal to the logic device. In the information processing device that interrupts normal processing in response to a power abnormality signal and executes power abnormality processing before the arrival of a reset signal, the logical device executes the power abnormality processing on a non-battery backup area and performs the reset. 1. A power supply abnormality processing method for an information processing device, characterized in that the storage information of the backup backup is guaranteed without giving unauthorized memory access from the logic device by a signal to the battery backup area.