JPS6264143A - Signal insulating device - Google Patents

Abstract

PURPOSE:To obtain a signal insulating device selecting both functions of an input and an output circuit by providing a pulse transformer having a primary coil and a secondary coil having a center tap so as to select the circuit by a switch operation. CONSTITUTION:In the input circuit mode, an H level signal is given to the input terminal of a driver DR1 to turn on a transistor (TR) Q1 and to apply a clock to a driver DR. The circuit shown in figure B is obtained in this state, terminals 11, 12 are input terminals to which a status signal is applied, the state is read at one end of the primary coil n1 as an impedance change via a pulse transformer PT, a resistor R5 and a diode D3 and an insulated status signal is obtained from the FF. In the output circuit mode, when the status signal fed to the driver DR1 is at an L level, the TR Q1 is turned off and a circuit shown in figure C is obtained, the energy stored in the transformer PT is discharged in the secondary winding and then a TR Q2 is turned on. Thus, the status signal is obtained from the terminals 11, 12 while being insulated from the primary side of the transformer PT.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a signal isolating device for electrically insulating and coupling two electrical devices. More specifically, the present invention isolates a status signal, and uses one pulse transformer to generate a signal that allows selection of the functions of both a status signal input circuit and a status (FI) output circuit. It relates to insulation devices.

(Prior Art) Fig. 4 is a connection diagram of a conventional status signal input circuit, and Fig. 5 is a connection diagram of a conventional status signal output circuit. 2(1
981), P22.

The first input path shown in Fig. 4 reads the state of the non-voltage contact S1 or the voltage signal as a change in impedance via a pulse transformer FT whose center tap is applied with a clock signal, and is isolated from the field. be.

In the output circuit shown in FIG. 5, the status signal to be output is isolated from the circuit side via a pulse transformer PT, and an open collector type transistor Q is used.

This is what is output by. Diode D0 is for circuit protection against reverse connection of the external power supply.

(Problems to be Solved by the Invention) In a signal isolation circuit having such a configuration, in order to realize an input circuit and an output circuit, each of the circuits shown in FIGS. 4 and 5 must be provided in advance. There was a problem that two pulse transformers were required and the configuration became complicated.

The present invention was made in view of these problems, and
The purpose is to realize a No. δ insulation device d with a simple configuration, using one pulse transformer and allowing selection of the functions of both the input circuit and the output circuit.

(Means for Solving the Problems) The present invention, which solves the above-mentioned problems, includes a pulse transformer having a negative side coil and a secondary side coil having a center tap, and a pulse transformer having a secondary side coil having a center tap. circuit means for driving the pulse transformer with a clock; a series circuit of a switch and a diode connected to the secondary coil of the pulse transformer; and a series circuit connected to the center tap of the secondary coil of the pulse transformer. A common line, an open collector type transistor whose emitter is connected to the common line and which is turned on and off by a voltage obtained by rectifying a signal generated in one secondary coil with this common line as a reference, and this transistor. A pair of terminals respectively connected to the emitter and collector of the coil rectify the signal generated in the other secondary coil with reference to the common line.

and a circuit that smooths the signal and applies it to one of the pair of terminals, and turns on the switch in the input circuit mode and applies a clock to the secondary coil.

The status signal applied to the pair of terminals is read at one end of the secondary coil, and in the output circuit mode, the switch is turned off, and the status signal applied to the secondary coil is obtained from the pair of terminals. .

(Example) FIG. 1 is a connection diagram showing an example of a device according to the present invention. In FIG. It has a secondary coil n2*13. For convenience, here, the left side of the pulse transformer I'T is assumed to be the secondary coil, and the right side is assumed to be the secondary coil. The connected diode serves to absorb backlash. OR+ is resistance R
A driver connected to the base of transistor Q+ through 1, and its input terminal has a terminal (
A high ("H") level signal is applied to the input circuit mode (input circuit mode), and an output status signal is applied when functioning as an output circuit (output circuit mode). OR
A driver 2 is connected to one end of the secondary coil n1 via a resistor R2, and a clock CL for driving the pulse transformer is applied to the input end of the driver.
FF is a flip-flop that reads and holds a status signal generated at one end of the negative side coil n1 in the input circuit mode.

On the secondary side of the pulse transformer PT, Q is a common line connected to the center tap 10, D2. Ds is a diode, and C, , C, are capacitors. The diode D and the capacitor C1 are connected in series to both ends of the secondary coil n2 via a common line l, and the diode D and capacitor C2 are connected to each other in series across the secondary coil n2 via a common line g. are connected in series to each other at both ends. R,
, R, are resistors that divide the voltage obtained across the capacitor C2, and Q is an open collector transistor that is turned on and off depending on the divided voltage, and its emitter is connected to the common line Q. I! , +2 are a pair of terminals respectively connected to the collector and emitter of the transistor Q2, and R3 is a resistor connected between the pair of terminals 11 and the common connection point of the diode 03 + capacitor C2.

The operation of the device configured as described above will be explained separately in the input circuit mode and the output circuit mode.

(Input circuit mode) A high (“H”) level signal is applied to the input terminal of the driver OR+ to turn on the transistor Q+.

Further, a clock CLK is applied to the input terminal of the driver DR2.

FIG. 2 is an equivalent circuit of FIG. 1 in this state.

Here, terminals I+ and +2 are input terminals,
An input status signal such as a contact signal is applied here. The state of this status signal can be read at one end of the primary coil n1 as a change in impedance via the resistor R5 + diode D and pulse transformer PT, and is isolated from the flip-flop FF and terminals 11 and 12. Status signals can be obtained.

Note that the pulse transformer PT due to the clock pulse CLK
The drive current flows as shown by solid lines and broken lines in FIG. Therefore, the energy stored in the pulse transformer PT is released via the diode D, and does not affect the secondary side.

(Output circuit mode) A status signal to be output is applied to the input terminal of the driver OR+, and a clock CLK is applied to the input terminal of the driver OR2.

In this state, a pair of terminals! 1°12 is the output terminal.

When the status signal applied to the driver D is at the "H" level, the transistor Q1 is on, and the result is the same as the equivalent circuit in FIG. 2, with no energy being released to the diode D1 and capacitor C1, and the secondary transistor Q2 It turns off. On the other hand, when the status signal is at the 'L' level, the transistor Q1 is off, resulting in the equivalent circuit shown in FIG.

Therefore, the energy absorbed by the pulse transformer PT is released to the secondary side through the path of diode D2 + transistor Q2, as shown by the broken line, and transistor Q is thereby turned on. Therefore, terminal I+, 12
, the status signal can be obtained insulated from the primary side of the pulse transformer PT.

Note that in this output circuit mode, the status signal to be output can be read back via the flip-flop FF.

(Effect of J! Ming) As explained above, the present invention can realize a signal isolation device with a simple configuration in which the functions of both the input circuit and the output circuit can be selected using one pulse transformer.

[Brief explanation of drawings]

Fig. 1 is a connection diagram showing an example of the device of the present invention, Fig. 2 is an equivalent circuit in input circuit mode, Fig. 3 is an equivalent circuit diagram when the status signal to be output is at 'H' level, Figs. Fifth
The figure is a connection diagram of a conventional input circuit and output circuit. PT...pulse transformer, nl...-blown coil, n
2+ n)...Secondary coil, ll...Common line,
ORI, DR2...driver, Q, (h...transistor, C,, C2...capacitor, DIl 0
2. Ds...diode, I+, +2...terminal. Figure 1 FF Figure 2 Figure 3

Claims (1)

[Claims] A pulse transformer having a primary coil and a secondary coil having a center tap; circuit means provided on the primary side of the pulse transformer for driving the pulse transformer with a clock; A series circuit of a switch and a diode connected to the primary coil of the transformer,
The emitter is turned on and off by a common line connected to the center tap of the secondary coil of the pulse transformer and a voltage obtained by rectifying a signal generated in one of the secondary coils with this common line as a reference. An open collector type transistor connected to a common line, a pair of terminals connected to the emitter and collector of this transistor, and a signal generated in the other secondary coil based on the common line is rectified and smoothed. a circuit that is applied to one of the pair of terminals, turns on the switch in the input circuit mode, applies a clock to the primary coil, reads a status signal applied to the pair of terminals at one end of the primary coil, A signal isolating device in which the switch is turned off in an output circuit mode so that a status signal applied to the primary coil is obtained from the pair of terminals.