JPS626379A - Control system for graphic display device - Google Patents

Abstract

PURPOSE:To shorten the updating time of screens and to improve the access efficiency of a screen memory by writing data directly on the picture memory from a main processor when the amount of screens to be updated is small. CONSTITUTION:When the amount of screens to be updated is small, a main processor 1 delivers data to the 2nd screen memory 4 serving as a screen memory exclusive for display in response to the writing address and the data structure of a bank memory of the screen memory. The bank memory starts a writing action and sends a busy signal back to a video signal forming part 5. The part 5 receives the busy signal from the memory 4 and holds the ACK signal to be delivered to the processor 1 for monitor of the busy signal. Then the part 5 delivers immediately the ACK signal for the end of the writing action to the processor 1 when the busy signal sent from the memory 4 is released.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] 0 This invention relates to a control method for a graphic display device having two or more screen memories.

[Conventional technology]

FIG. 2 is a diagram showing the configuration of a conventional high-speed processing graph ink display device having two or more screen memories; in the figure, 1 is a main processor that controls and manages the entire device;
2 is an image processing processor that converts graphic processing data from the main processor 1 into screen memory data, and 3 is an input port for inputting screen memory data output from the image processing processor 2 and an output port for display data, each independently. a first bank memory having a plurality of banks;
, 4 is a second screen memory having the same function as the first screen memory 3, and 5 converts display data output from the first screen memory 3 or the second screen memory 4 into a video signal. The video signal generating section 6 is a monitor that displays an image based on the video signal output from the video signal generating section 5.

Next, a method of controlling the conventional graphic display device configured as described above will be explained.

The main processor 1 outputs a function selection command to the video signal generation unit 5 to select the first screen memory 3 or the second screen memory 4 as a write-only function or a display-only function, respectively.

When the video signal generation section 5 receives a function selection command from the main processor 1, it outputs a function switching signal to the first screen memory 3 and the second screen memory 4. As a result, the first screen memory 3 or the second screen memory 4 is switched to either a write-only function or a display-only function. In this case the first
When the screen memory 3 is for writing only, the second screen memory 4 is for display only, and when the first screen memory 3 is for display only, the second screen memory 4 is for writing only. It looks like this. Also, at the time when the function switching signal is output, the main processor 1 is notified of the completion of instruction execution with an ACK signal.

When the main processor 1 receives the ACK signal from the video signal generation section 5, it then outputs a screen memory clear command and a start command to the image processing processor 2. The image processing processor 2 receives the screen memory clear command and the start command,
For the first screen memory 3 or the second screen memory 4,
Clear data is output corresponding to the screen memory clear address and the data structure of the bank memory of the screen memory. Here, if the first screen memory 3 is a write-only screen memory, one bank memory of the first screen memory 3 selected by the screen memory clear address from the image processing processor 2 becomes the screen memory clear address. Each receives clear data and starts clearing operation. The bank memory that has started the clearing operation returns a BUSY signal to the image processing processor 2 until the clearing operation is completed. child(
7) Based on the BUSY signal, the image processing processor 2 determines whether the next screen memory clear address selects the bank memory in the clearing operation, and if it is the address of the bank memory in the idle IDLE state, it selects the first screen memory clear address. Outputs the screen memory clear address and clear data to the screen memory 3. Further, if the clear address is the address of the bank memory during the clearing operation, the image processing processor 2 waits until the clearing operation is completed. The image processor 2 repeatedly executes this series of operations for all addresses in the first screen memory 3. Further, the image processing processor 2
A response is sent to the main processor 1 with a processing end signal indicating that the clearing operation has been completed for all addresses in the screen memory 3.

When the main processor 1 receives a processing completion signal from the image processing processor 2, it also outputs graphic processing data and a start command to the image processing processor 2. When the image processing processor 2 receives the activation command from the main processor 1, it converts the graphic processing data into write data corresponding to the data structure of the bank memory, and stores this write data together with the screen memory write address in the first memory. are output to the screen memory 3 respectively. The bank memory selected by the screen memory write address from the image processing processor 2 receives the screen, memory write address, and write data, and starts a write operation. This write operation returns a BUSY signal to the image processing processor 2, similar to the clear operation described above. Based on this BUSY signal, the image processing processor 2 determines whether the next screen memory write address selects the bank memory in which the write operation is being performed, and similarly to the clear operation, it selects the bank memory in the idle IDLR state. If it is an address, the screen memory write address and write data are output to the first screen memory 3. If the bank memory is in the process of writing, the image processing processor 2 waits until the writing operation is completed.The image processing processor 2 repeats this series of operations until there is no more data to write. Further, the image processing processor 2 replies to the main processor 1 with a processing completion signal that the writing operation to the first screen memory 3 has been completed.

On the other hand, the video signal generation unit 5 sequentially outputs screen memory display addresses to the second screen memory 4, which is a display-only screen memory, in synchronization with the display cycle of the monitor 6.

The second screen memory 4 outputs display data corresponding to the screen memory display address from the video signal generator 5 to the video signal generator 5. The video signal generation unit 5 converts the display data from the second screen memory 4 into a video signal, and outputs it to the monitor 6 for display.

In this way, the main processor 1 uses the first screen memory 3 as a write-only screen memory and the second screen memory 4 as a display-only screen memory, and operates them independently. Further, upon receiving a processing end signal from the image processing processor 2 indicating the end of writing to the first screen memory 3, the main processor 1 immediately outputs a function selection command to the video signal generation section 5. , the first screen memory 3 is switched from write-only to display-only screen memory, the second screen memory 4 is switched from display-only to write-only screen memory, and the display screen of monitor 6 is updated.

[Problem that the invention seeks to solve]

Conventionally, the screen memory in a graphic display device is usually a large capacity memory of IM to several + Mbit. In addition, when updating the display screen on a graphic display device that has two or more screen memories, a clear operation is performed on all screen memory addresses, a write operation corresponding to the screen update contents, and the updated contents are displayed. The time required to clear the screen memory at that time increases in proportion to the capacity of the screen memory. For this reason, when attempting to partially change the display screen (for example, by moving the cursor), the screen memory clearing time takes up a much larger proportion of the screen update time than the screen update writing time. Affects screen refresh time. Additionally, this has the problem of affecting the performance of the device itself.

This invention was made in order to solve the above-mentioned problems, and it allows the screen memory to be accessed independently for the main processor and the image processing processor, and also shortens the screen update time and reduces the screen memory. The purpose of this invention is to obtain a control method for a graphic display device that can improve the accessibility of vehicles.

[Means for solving problems]

Therefore, the control system of the graphic display device according to the present invention allows the main processor and the image processing processor to independently write screen memory data to the screen memory, and when the amount of screen updates is small, the main processor writes the screen memory data to the screen memory. The feature is that memory data can be written directly.

[Effect]

When the amount of screen updates is large, the above processor outputs graphics processing data to the image processing processor as in the past, and the image processing processor writes screen memory data to the screen memory based on this graphics processing data, and then writes the screen memory data to the screen memory. Based on the written screen memory data, the video signal generation section displays an image on the monitor.

Also, when the amount of screen updates is small, the main processor directly writes screen memory data to the screen memory, and based on the screen memory data updated by this writing, the video signal generation unit directly outputs the updated contents to the monitor. Take a picture.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 is a main processor that controls and manages the entire device, 2 is an image processing processor that converts graphic processing data from the main processor 1 into screen memory data, and 3 is screen memory data from the main processor 1 and the image processing processor 2. a first screen memory having an input port and a display data output port, and further comprising a plurality of bank memories; 4, a second screen memory having the same function as the first screen memory 3; 5 is the first screen memory 3 or the second
6 is a monitor, which converts display data from the screen memory 4 into a video signal.

Next, a control method for the graphic display device of the present invention will be explained.

The main processor 1 outputs a function selection command to the video signal generation unit 5 to select the first screen memory 3 or the second screen memory 4 as a write-only function or a display-only function, respectively.

When the video signal generation section 5 receives a function selection command from the main processor 1, it outputs a function switching signal to the first screen memory 3 and the second screen memory 4. Thereby, the first screen memory 3 or the second screen memory 4 is switched to either write-only or display-only. Furthermore, at the time when the function switching signal is output, the main processor 1 is notified of the completion of instruction execution with an ACK signal.

When the main processor 1 receives the ACK signal from the video signal generation unit 5, it next determines the amount of update to the screen memory, and if the amount of update is large, it issues a screen memory clear command to the image processing processor 2 and starts the process. Output instructions. The image processing processor 2 receives the screen memory clear command and the start command, and clears the first screen memory 3 or the second screen memory 4 according to the screen memory clear address and the data structure of the bank memory of the screen memory. Output each data. Here, if the first screen memory 3 is a write-only screen memory, one of the first screen memories 3 selected by the screen memory clear address from the image processing processor 2
The bank memory receives the screen memory clear address and clear data and starts clearing operation. The bank memory that has started the clearing operation returns a BUSY signal to the screen processing processor 2 until the clearing operation is completed. Based on this BUSY signal, the image processing processor 2 determines whether the next image memory clear address selects the bank memory in the clearing operation, and if the bank memory is in the idle IDEL state, it selects the first screen memory 3. outputs the screen memory clear address and clear data. Further, if the clear address is in the process of clearing, it waits until the clearing operation is completed. The image processor 2 repeatedly executes this series of operations for all addresses in the first screen memory 3. Further, the image 2 processing processor 2 sends a processing completion signal to the main processor 1 in response to the completion of the clearing operation for all addresses in the first screen memory 3.

Upon receiving the processing end signal from the image processing processor 2, the main processor 1 also sends the following information to the image processing processor 2.
Outputs graphic processing data and startup instructions. When the image processing processor 2 receives the activation command from the main processor 1, it converts the graphic processing data into write data corresponding to the data structure of the bank memory, and stores this write data together with the screen memory write address in the first memory. are output to the screen memory 3 respectively. The bank memory selected by the screen memory write address from the image processing processor 2 receives the screen memory write address and write data, and starts a write operation. This write operation returns a BUSY signal to the image processing processor 2, similar to the clear operation described above.

This BUSY signal causes the image processor 2 to
It is determined whether the next screen memory write address selects the bank memory in which the write operation is in progress, and if the bank memory is in the idle IDEL state, as in the clear operation, the screen memory 3 is selected for the first screen memory 3. Outputs memory write address and write data. Furthermore, if the bank memory is in a write operation, the image processor 2 waits until the write operation is completed. The image processor 2 repeatedly executes this series of operations until there is no more write data. The image processor 2 also sends a processing completion signal to the main processor 1 in response to the completion of the write operation to the first screen memory 3.

On the other hand, the video signal generation unit 5 sequentially outputs screen memory display addresses to the second screen memory 4, which is a display-only screen memory, in synchronization with the display cycle of the monitor 6.

The second screen memory 4 outputs display data corresponding to the screen memory display address from the video signal generator 5 to the video signal generator 5. The video signal generation unit 5 converts the display data from the second screen memo IJ 4 into a video signal, and outputs the video signal to the monitor 6 for display.

In this way, the main processor 1 independently operates the first screen memory 3 as a write-only screen memory and the second screen memory 4 as a display-only screen memory. Furthermore, when the main processor 1 receives a processing end signal indicating the end of writing to the first screen memory 3 from the image processing processor 2, it immediately functions for the video signal generating section 5)! An i scale command is output, the first screen memory 3 is switched from a write-only screen memory to a display-only screen memory, the second screen memory 4 is switched from a display-only screen memory to a write-only screen memory, and the display screen of the monitor 6 is updated.

The above explanation is for a case where the amount of screen updates is large.

Conversely, if the amount of screen updates is small, main processor 1
is the second screen memory 4 which is a display-only screen memory.
A write address and data corresponding to the data structure of the bank memory of the screen memory are output. At this time, the second
If the screen memory 4 is being accessed by the video signal generation unit 5, the write operation of the main processor 1 is delayed until the access by the video signal generation unit 5 is completed. When the access by the video signal generation section 5 is completed, the bank memory selected by the write address from the main processor 1 starts a write operation. The bank memory that has started the write operation responds with a BUSY signal to the video signal generation section 5. When the video signal generator 5 receives the BUSY signal from the second screen memory 4, it suspends the ACK signal to be output to the main processor 1 and monitors the BUSY signal. Immediately after the BUSY signal from the second screen memory 4 is released, the video signal generation unit 5 outputs an ACK signal indicating completion of writing to the main processor 1. The main processor 1 uses the ACK signal from the video signal generator 5 to
It outputs the next write address and write data to and waits for an ACK signal from the video signal generation section 5. In this way, the main processor 1 repeatedly executes a series of operations until there is no more write data.

On the other hand, the first screen memory 3, which is a write-only screen memory, is not accessed by the graphics processor 2, so it retains its previous contents.

In this way, when the amount of screen updates is small, the main processor 1
can be written directly to the second screen memo I74 of the display-only screen memory. Also, although a clearing operation is required for write-only screen memory, in this case, no clearing operation is required, and the updated contents are reflected on the display screen as they are.

In the above embodiment, the case where there are two screen memories has been described, but even if there are three or more screen memories, the same effect as in the above embodiment can be achieved.

〔Effect of the invention〕

As described above, the control method of the graphic display device according to the present invention allows the main processor and the image processing processor to independently write screen memory data to the screen memory, and when the amount of screen updates is small, the main processor Since the screen memory data is directly written to the screen memory, the screen update time can be shortened when the amount of screen updates is small, and the efficiency of screen memory access can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a graphic display device showing an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional graphic display device. ■...Main processor, 2...Image processing processor, 3...First screen memory, 4...
...Second screen memory, 5.Video signal generation unit, 6.Old monitor. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Figure 2 Procedural Amendment (Voluntary Showa year, month, day)

Claims (1)

[Claims] A main processor that outputs graphic processing data, an image processing processor that converts the graphic processing data output from the main processor into screen memory data, and at least two or more screens that store the screen memory data output from the screen processing processor. In a control method for a graphic display device having a memory and a video signal generating section that accesses and retrieves screen memory data stored in the screen memory, the main processor and the image processing processor independently store the screen memory data in the screen memory. A control method for a graphic display device, characterized in that data can be written, and screen memory data is written directly from the main processor to the screen memory when the amount of screen updates is small.