JPS6263790U - - Google Patents

Info

Publication number
JPS6263790U
JPS6263790U JP9588185U JP9588185U JPS6263790U JP S6263790 U JPS6263790 U JP S6263790U JP 9588185 U JP9588185 U JP 9588185U JP 9588185 U JP9588185 U JP 9588185U JP S6263790 U JPS6263790 U JP S6263790U
Authority
JP
Japan
Prior art keywords
text
display device
text data
content
gate circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9588185U
Other languages
Japanese (ja)
Other versions
JPH0438392Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP9588185U priority Critical patent/JPH0438392Y2/ja
Publication of JPS6263790U publication Critical patent/JPS6263790U/ja
Application granted granted Critical
Publication of JPH0438392Y2 publication Critical patent/JPH0438392Y2/ja
Expired legal-status Critical Current

Links

Landscapes

  • Storing Facsimile Image Data (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1は本考案の一実施例を示すブロツク図、第
2図イ,ロ,ハは本考案の表示例を示す画面図、
第3図は従来の文章表示装置の構成を示すブロツ
ク図、第4図イ,ロ,ハは第3図の装置における
デコーダのチツプ選択の説明図。 符号の説明、1a,1b,1c……文章ROM
、2……文章制御ROM、3……RAM、4……
デコーダ、8……CPU、9……入力インターフ
エイス、10……入力ポート、11a……コント
ロールバス、11b……アドレスバス、11c…
…データバス、12……リフレツシユラム、13
……キヤラクタジエネレータ、14a……xドラ
イバー、14b……yドライバー、15……タイ
ミングカウンター、16……アドレスセレクター
、17……電源部、18a,18b,18c……
NORゲート、20……文章制御部、21……表
示制御部、22……表示部。
The first is a block diagram showing an embodiment of the present invention, and the second is a screen diagram showing a display example of the present invention.
FIG. 3 is a block diagram showing the configuration of a conventional text display device, and FIGS. 4A, 4B, and 4C are explanatory diagrams of decoder chip selection in the device shown in FIG. Explanation of codes, 1a, 1b, 1c...Text ROM
, 2...Text control ROM, 3...RAM, 4...
Decoder, 8... CPU, 9... Input interface, 10... Input port, 11a... Control bus, 11b... Address bus, 11c...
...data bus, 12...refreshment ram, 13
...Character generator, 14a...x driver, 14b...y driver, 15...timing counter, 16...address selector, 17...power supply section, 18a, 18b, 18c...
NOR gate, 20... text control section, 21... display control section, 22... display section.

補正 昭61.11.19 図面の簡単な説明を次のように補正する。 明細書第14頁第7行目の記載「第1は」を「
第1図は」と補正する。
Amendment November 19, 1981 The brief description of the drawing is amended as follows. The statement “first is” on page 14, line 7 of the specification is replaced with “
Figure 1 is corrected as ".

Claims (1)

【実用新案登録請求の範囲】 適用する機器の種々の状態の各々に対応する文
章データを同一のアドレスに同一の意味内容で記
憶すると共に各々が異なる言語を用いた複数の文
章ROMと、前記状態の内容を判断して当該判断
時点の状態に対応する文章データを前記メモリか
ら読み出し、該読み出した文章データを表示部へ
表示する制御部を備えた文章表示装置において、 前記複数の文章ROMの所望のチツプを選択す
る複数のゲート回路と、 選択された複数言語に対応する言語選択信号に
基づいて当該言語に対応する文章ROMに接続さ
れる前記ゲート回路を同時または順番に開かせる
制御手段を設けたことを特徴とする文章表示装置
[Claims for Utility Model Registration] A plurality of text ROMs that store text data corresponding to each of various states of applied equipment at the same address with the same meaning and content, each using a different language; In the text display device, the text display device includes a control unit that determines the content of the text, reads text data corresponding to the state at the time of the judgment from the memory, and displays the read text data on a display unit, a plurality of gate circuits for selecting the chips; and a control means for simultaneously or sequentially opening the gate circuits connected to the text ROM corresponding to the selected languages based on a language selection signal corresponding to the plurality of selected languages. A text display device characterized by:
JP9588185U 1985-06-25 1985-06-25 Expired JPH0438392Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9588185U JPH0438392Y2 (en) 1985-06-25 1985-06-25

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9588185U JPH0438392Y2 (en) 1985-06-25 1985-06-25

Publications (2)

Publication Number Publication Date
JPS6263790U true JPS6263790U (en) 1987-04-20
JPH0438392Y2 JPH0438392Y2 (en) 1992-09-08

Family

ID=30961011

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9588185U Expired JPH0438392Y2 (en) 1985-06-25 1985-06-25

Country Status (1)

Country Link
JP (1) JPH0438392Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04125684A (en) * 1990-09-18 1992-04-27 Totoku Electric Co Ltd Crt display device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04125684A (en) * 1990-09-18 1992-04-27 Totoku Electric Co Ltd Crt display device

Also Published As

Publication number Publication date
JPH0438392Y2 (en) 1992-09-08

Similar Documents

Publication Publication Date Title
KR860004409A (en) Semiconductor memory
JPS6263790U (en)
JPS6048073A (en) Display unit
US4570237A (en) Microprocessor
JPS56118165A (en) Processor of video information
JPS6326421B2 (en)
KR860002754A (en) Mixing Lines and Text in Cathode Ray Tube Display Systems
KR970073332A (en) A semiconductor memory device
JPS6052543U (en) Graphic input display device
KR930009529B1 (en) Word display device utilizing font rom and the method
JPH0479024B2 (en)
JPH0418048Y2 (en)
JPS6078083U (en) text display device
JPS60140104U (en) CIO/DIO automatic switching circuit
JPS61662U (en) electronic calculator
EP0228136A3 (en) Abstract operation-signalling from a raster scan video controller to a display memory
JPS6288199A (en) Digital circuit
JPS62179603U (en)
JPS6023891U (en) display device
JPS60126846U (en) Memory switching control circuit
JPS5859276U (en) teletext receiver
JPS58174739U (en) Kanji address input device
KR930008843A (en) Semiconductor memory device
JPS6439536U (en)
KR970052948A (en) Power line wiring method in semiconductor device