JPS626338A - Error information system for back end processor - Google Patents

Abstract

PURPOSE:To attain the information of a back end error to a host processor by providing an error informing circuit to an adaptor which intermediates I/O operation between a back end processor and the host processor for transfer of data and connecting the error informing circuit to a maintenance diagnosis processor SVP5. CONSTITUTION:The working of a back end processor 1 is monitored by an SVP5. An error of a system loop, etc. if produced by the abnormality of the hardware or software is detected. Then the working of the processor 1 is stopped and the error contents are analyzed. The result of this analysis is set to an error informing circuit 32 and at the same time a starting circuit 32 is started via an SVP interface 33. Thus an interruption is given to a host processor 2. Then the error contents of the circuit 32 are informed to the processor 2 via a data transfer circuit 31. Thus the processor 2 can know the error contents with proper timing.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Prior Art Problems to be Solved by the Invention Means for Solving the Problems (Fig. 1) Working Examples (AL-Description of Examples) (Fig. 2) Description of other embodiments Effects of the invention [Summary] In a back-end processor error notification method for notifying a host processor of errors in a back-end processor connected to the host processor via an adapter. , an error notification circuit is provided in the adapter, and the error notification circuit is controlled by a maintenance diagnostic processor that detects errors in the back-end processor, so that errors in the back-end processor are notified from the adapter to the host processor.

(Industrial Application Field) The present invention relates to an error notification method for back-end processors such as vector processors and high-level language processors, and in particular, the present invention relates to an error notification method for notifying a host processor of an error in a back-end processor that is connected to and operates on a host processor. Regarding the method.

The development of computer technology in recent years has been remarkable, with faster speeds,
Intelligent technology is required.

In response to such demands, a composite processor system is constructed in which a dedicated processor is connected to a host processor, and the performance of the dedicated processor is used to increase speed and intelligence.

For example, as shown in FIG. 3, a dedicated processor is connected as the back-end processor 1 to the host processor 2 connected to the terminal 4 via the adapter 3. To make vector processors intelligent, L IS
A processor dedicated to high-level languages such as P and PROLOG is used. The maintenance diagnostic processor 5 is used to detect errors in the backend processor 1.

[Conventional technology]

Such a backend processor 1 is, for example, LIS.
If it is a P processor, it will operate as an artificial intelligence dedicated processor, and by exchanging data via the host processor 2 and adapter 3, the host processor 2 can use the backend processor l as an l10 (input/output) unit. It can be treated as such.

Such an adapter 3 conventionally consists of a startup circuit 30 and a data transfer circuit 31 as shown in FIG. 4(A), and as shown in FIG. 4(B).
), the CPU of the back-end processor 1 interrupts the host processor 2 via the startup circuit 30 and notifies the host processor 2 that processing is possible, and the host processor 2 receives this and requests processing to be performed. If there is, the processing request and data are given to the memory control section of the back-end processor 1 via the data transfer circuit 31 and transferred to the built-in memory.

The back-end processor 1 executes the requested process based on the contents of this memory, and upon completion of the process, notifies the host processor 2 via the startup circuit 30, and further notifies the process result to the host processor 2 via the data transfer circuit 31. I have to.

-4. A maintenance diagnosis processor 5 is connected to the back-end processor 1 to detect the initial load of the memory and hard errors and soft errors of the processor L, and detects hard errors and soft errors due to soft loops. The backend processor 1 is made to take appropriate measures.

[Problem that the invention seeks to solve]

However, in the conventional technology, although the maintenance/diagnosis processor 5 detects an error in the back-end processor l, this only causes the connected back-end processor l to take measures such as stopping, and the host processor 2 directly When the host processor 2 requests processing via the adapter 3, the command processing times out and does not end normally, as shown in Figure 4 (B), resulting in an error in the backend processor 1. could only be recognized indirectly.

Therefore, in addition to the problem that the host processor 2 cannot immediately recognize an error in the back-end processor 1, there is also the problem that the host processor 2 cannot directly recognize the type of error. Therefore, in order to analyze the error later, it is necessary to check the status of the maintenance diagnostic processor 5, and the host processor 2 cannot directly check the status by displaying it on the terminal 4, for example.

SUMMARY OF THE INVENTION An object of the present invention is to provide an error notification method for a back-end processor that can notify a host processor of an error in the back-end processor, thereby making it possible to perform system error analysis easily and in detail.

Measures to solve problem C] FIG. 1 is a diagram explaining the principle of the present invention.

In the figure, the same parts as those shown in FIG.
P5 is commanded when detecting an error in the back-end processor 1, and notifies the host processor 2 of the error.

That is, in the present invention, the error notification circuit 32 is provided in the adapter 3 that mediates data exchange between the back-end processor 1 and the host processor 2, and the error notification circuit 32
It is configured by connecting it with 5VP5.

[Effect]

In the present invention, in order to notify the host processor 2 of an error in the backend processor 1 detected by the 5VP5,
This attempts to use the data transfer route of adapter 3.

Therefore, an error notification circuit 32 is provided in the adapter 3, and an error in the backend processor 1 detected by the 5vP5 is sent to the host processor 2 using the transfer route of the adapter 3.
The purpose is to notify the following.

This allows the host processor 2 to recognize errors in the backend processor 1 and recognize them as backend processor status signals from the adapter 3, eliminating the need for a special interface.

〔Example〕

(a) Description of an Embodiment FIG. 2 is a block diagram of an embodiment of the present invention, showing the internal blocks of the adapter 3. As shown in FIG.

In the figure, the same parts as shown in Figs. 1, 3, and 4 are indicated by the same symbols, and 33 is an SvP interface, which exchanges commands and data with the 5VP5. It is for. Therefore, adapter 3
is backend processor 1, host processor, processor 2
In addition to a startup circuit 30 and a data transfer circuit 31 for exchanging information with the 5VP5, an error notification circuit 32 controlled by the 5VP5 and connected to the data transfer circuit 31, and an SvP interface 33 for exchanging information with the 5VP5. It will be established.

To explain the operation of the configuration in FIG. 2, in normal operation, the CPU of the back-end processor 1 issues an interrupt to the activation circuit 30.
The host processor 2 sends processing requests, data, etc. to the data transfer circuit 3 by sending them to the host processor 2 via the data transfer circuit 3.
1 to the MCU (memory control unit) of the back-end processor 1 and stored in the memory.

As a result, the back-end processor l reads the processing request and data given from its own memory and executes them.For example, if it is an AI processor using the LISP language, it will perform inference processing as an artificial intelligence processor.

The operation of this back-end processor 1 is monitored by the 5vP5, which monitors the presence or absence of errors during processing execution, detects errors such as hardware abnormalities or system loops caused by software, and detects them. Stops processing and analyzes the error details.

Then, the contents of the error are sent to the error notification circuit 32, and the activation circuit 30 is activated via the SvP interface 33 to generate an interrupt to the host processor 2. Furthermore, the error contents set by the error notification circuit 32 are transmitted to the host processor 2 via the data transfer circuit 31.
Notify.

As a result, the host processor 2 is notified of the abnormality (error) and the details of the error at appropriate timing.

Therefore, the host processor 2 can recognize errors in the back-end processor 1 in detail, and can easily and precisely perform system error analysis processing.

Therefore, the detailed error judgment of the SVP 5, the timing of error notification, the distinction of the contents of the error notification, etc. can be reflected in the host processor 2.

In this example, the error notification circuit is just a register that stores the error contents, and the interrupt to the host processor 2 is 5V.
The error notification is performed by the adapter 3 under the control of P5, and the error notification can be performed without complicating the configuration of the adapter 3.

(bl Description of Other Embodiments Although the error notification circuit is simply a register in the above example, the error notification circuit may activate the activation circuit 30 to notify the host processor of an interrupt.

Further, the 5VP 5 may monitor the state inside the adapter 3 by using the SVP interface 33.

Although the present invention has been described above using examples, the present invention can be modified in various ways according to the gist of the present invention, and these are not excluded from the present invention.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to notify the host processor of errors in the back-end processor, and the host processor can easily perform detailed system error analysis processing. In addition, since error notifications are made using the adapter's transfer route, error notifications can be made without requiring a special interface with the host processor, and this does not increase the load on the host processor. Also, the functions can be realized with a minimum increase in hardware.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is a block diagram of a complex system using a back-end processor, and Fig. 4 is a diagram explaining the prior art. be. In the figure, 1--back-end processor, 2--1111 host processor, 3-- adapter, 5-- maintenance diagnosis processor, 32- error notification circuit.

Claims (1)

[Scope of Claims] A host processor, a back-end processor that executes processing at the request of the host processor, and an adapter device that connects the host processor and the back-end processor and mediates data exchange between the two processors. and a maintenance diagnostic processor that detects errors in the back-end processor, the adapter device is provided with an error notification circuit, and the maintenance diagnostic processor is configured to be able to control the error notification circuit, An error notification method for a back-end processor, characterized in that when the maintenance diagnosis processor detects an error in the back-end processor, the error notification circuit is instructed to notify the host processor of the error from the adapter device.