JPS6262468B2 - - Google Patents
Info
- Publication number
- JPS6262468B2 JPS6262468B2 JP55034463A JP3446380A JPS6262468B2 JP S6262468 B2 JPS6262468 B2 JP S6262468B2 JP 55034463 A JP55034463 A JP 55034463A JP 3446380 A JP3446380 A JP 3446380A JP S6262468 B2 JPS6262468 B2 JP S6262468B2
- Authority
- JP
- Japan
- Prior art keywords
- gate
- melting point
- film
- high melting
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910052751 metal Inorganic materials 0.000 claims description 48
- 239000002184 metal Substances 0.000 claims description 48
- 238000002844 melting Methods 0.000 claims description 29
- 230000008018 melting Effects 0.000 claims description 25
- 150000004767 nitrides Chemical class 0.000 claims description 22
- 238000005468 ion implantation Methods 0.000 claims description 19
- 239000004065 semiconductor Substances 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 239000010410 layer Substances 0.000 description 20
- 238000000034 method Methods 0.000 description 17
- 229910052581 Si3N4 Inorganic materials 0.000 description 13
- 239000012535 impurity Substances 0.000 description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 13
- 239000013078 crystal Substances 0.000 description 11
- 150000002739 metals Chemical class 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 230000000873 masking effect Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 230000035515 penetration Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 230000000149 penetrating effect Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 239000003870 refractory metal Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000005465 channeling Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
- H01L29/4958—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo with a multiple layer structure
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
本発明は低抵抗でかつ、イオン注入時の自己整
合が可能な電極配線を有する半導体装置の製造方
法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device having electrode wiring that has low resistance and allows self-alignment during ion implantation.
近年集積回路の高密度化が進むにつれて、従来
MOS型集積回路中のゲート電極配線等々の各種
半導体装置の配線もしくは電極の素材として広く
用いられて来たものに不純物添加多結晶シリコン
がある。しかし近年集積回路の高密度化が進むに
つれて、その比抵抗が約700μΩ・cmから１ｍ
Ω・cmと高く、配線抵抗が無視できない事態にな
つてきた。特に高速度の応答が困難になる点が問
題である。そのため、最近では、高融点金属をゲ
ート電極配線として用いることにより、配線抵抗
を下げ、かつ安定な半導体装置を得ようとする考
えが注目され、精力的な研究が幅広く行われつつ
ある。 In recent years, as the density of integrated circuits has increased,
Impurity-doped polycrystalline silicon has been widely used as a material for wiring or electrodes of various semiconductor devices, such as gate electrode wiring in MOS type integrated circuits. However, as the density of integrated circuits has increased in recent years, the specific resistance has increased from approximately 700 μΩ・cm to 1 m
The wiring resistance is now as high as Ω/cm and cannot be ignored. In particular, the problem is that high-speed response becomes difficult. Therefore, recently, the idea of lowering the wiring resistance and obtaining a stable semiconductor device by using a high-melting point metal as the gate electrode wiring has attracted attention, and a wide range of vigorous research is being carried out.
MoやＷ等の高融点金属は、比抵抗が７μΩ・
cmから10μΩ・cmと不純物添加多結晶シリコンに
比して約２桁も比抵抗が小さく、配線抵抗は充分
に無視できる程小さくなる。 High melting point metals such as Mo and W have a specific resistance of 7 μΩ.
The resistivity is approximately two orders of magnitude lower than that of doped polycrystalline silicon, ranging from 10 μΩ·cm to 10 μΩ·cm, and the wiring resistance is sufficiently small to be ignored.
また、結晶粒径も小さく、微細加工性に優れて
おり、高密度集積回路の配線材料として、多結晶
シリコンにとつてかわるべき優れた素材であると
考えられている。 Furthermore, it has a small crystal grain size and excellent microfabricability, and is considered to be an excellent material to replace polycrystalline silicon as a wiring material for high-density integrated circuits.
しかしながら、上記高融点金属をゲート電極と
した半導体装置たとえばMOSトランジスタは、
しきい値電圧の再現性に乏しく、これは、高融点
金属ゲートをその製造過程においてイオン注入マ
スクとして流用することがあるがその際のマスク
作用が不完全であることが一因となつている。つ
まり、一般に高融点金属ゲートのMOSトランジ
スタは、第１図ａに示すように素子分離用シリコ
ン酸化膜１を形成し、ゲート酸化膜２を成長させ
た後、高融点金属を蒸着し加工してゲート電極３
を作る。その後、第１図ｂに示すように、基板と
反対の伝導型を呈する不純物をイオン注入法によ
つて注入し、MOSトランジスタのソース及びド
レインとなる領域４を作り、窒素雰囲気中で1000
℃ぐらいに加熱し、注入層の活性化を行う、この
工程は、ゲート金属がイオン注入による不純物原
子の貫通を阻止し、MOSトランジスタのチヤネ
ル部分に不純物原子が入らず、また、その後の熱
工程にも、ゲート金属が溶融したりすることのな
い場合に極めて有効で、イオン注入時の自己整合
が可能である利点を得る。シリコンプレナー技術
に於て通常を写真蝕刻法で素子を形成して行く場
合は自己整合の利点は得られず、目合せずれによ
る余裕度を考慮する必要があるが、前記の如く自
己整合が可能である場合はその必要がなく、集積
回路の高密度化に必須である。しかしながら高融
点金属は、その結晶粒が柱状構造をとつているこ
ともあり、イオン注入された不純物原子は、一部
はその結晶粒界に沿つてまた一部は結晶粒中をチ
ヤネリングによつてゲート金属を透過し、さらに
はゲート酸化膜を突き抜けて、シリコン基板中に
到達することすらあるのである。この現象は本発
明者等が特に注目したものである。なぜならばソ
ース・ドレイン領域形成のための不純物原子は、
基板とは反対の伝導型を形式するのに寄与するた
め、チヤネル部にたとえ一部でもこのような不純
物原子が到達するとチヤネル部の基板の不純物濃
度は補償され、基板の初期の不純物濃度に比べて
薄くなり、その結果、表面反転層ができ易くな
り、MOSトランジスタのしきい値電圧は、その
絶対値が小さくなるからである。しかも、上記高
融点金属ゲートの場合に生じる不純物原子の貫通
は、結晶粒界に沿つたり、あるいは結晶粒中のチ
ヤネリング等によつて起こるため、透過する不純
物原子の量は、金属膜の形成時の微妙な条件によ
つて変化し、その結果、MOSトランジスタのし
きい値電圧のばらつきや再現性の欠如となるから
である。 However, semiconductor devices such as MOS transistors using the above-mentioned high melting point metal as a gate electrode,
The reproducibility of the threshold voltage is poor, and one reason for this is that the refractory metal gate is sometimes used as an ion implantation mask in the manufacturing process, but the masking effect at that time is incomplete. . In other words, in general, a MOS transistor with a high melting point metal gate is manufactured by forming a silicon oxide film 1 for element isolation, growing a gate oxide film 2, and then depositing and processing a high melting point metal as shown in Figure 1a. Gate electrode 3
make. Thereafter, as shown in FIG. 1b, impurities having a conductivity type opposite to that of the substrate are implanted by ion implantation to form regions 4 that will become the source and drain of the MOS transistor.
In this process, the gate metal prevents the impurity atoms from penetrating through the ion implantation, preventing the impurity atoms from entering the channel part of the MOS transistor, and also prevents the subsequent thermal process. It is also extremely effective when the gate metal does not melt, and has the advantage that self-alignment is possible during ion implantation. In silicon planar technology, when elements are normally formed by photolithography, the advantage of self-alignment cannot be obtained and allowances for misalignment must be taken into account, but self-alignment is possible as described above. In this case, this is not necessary and is essential for increasing the density of integrated circuits. However, since the crystal grains of high melting point metals have a columnar structure, some of the ion-implanted impurity atoms are channeled along the grain boundaries and some through the crystal grains. It can even penetrate the gate metal and even the gate oxide film and reach the silicon substrate. This phenomenon is something that the present inventors particularly paid attention to. This is because impurity atoms for forming source/drain regions are
Since they contribute to form a conduction type opposite to that of the substrate, if even a portion of such impurity atoms reach the channel region, the impurity concentration of the substrate in the channel region is compensated and becomes lower than the initial impurity concentration of the substrate. This is because the absolute value of the threshold voltage of the MOS transistor becomes smaller because the surface inversion layer is more likely to be formed and the absolute value of the threshold voltage of the MOS transistor becomes smaller. Moreover, the penetration of impurity atoms that occurs in the case of the above-mentioned high-melting point metal gate occurs along crystal grain boundaries or due to channeling within crystal grains, so the amount of impurity atoms that pass through depends on the formation of the metal film. This is because it changes depending on delicate conditions at the time, resulting in variations in the threshold voltage of MOS transistors and lack of reproducibility.
上記のような、イオン注入による不純物原子の
ゲート金属の貫通を防ぐ手段としては、第１にゲ
ート金属膜を厚くする手段がある。しかしながら
この方法は、表面の凹凸が激しくなり、ソース・
ドレイン等の配線部形成時に所謂段切れを起す確
率が高くなり、歩留りを悪くする原因となる。ま
た、微細加工の観点からもサイドエツチ量が増大
する結果となり不適当である。さらに、金属膜を
厚くすることによる内部応力等々の歪の増大もま
た素子の性能に悪影響を及ぼすことになる。以上
のことから、ゲート金属膜を厚くすることによる
手段は不適当である。 As a means for preventing impurity atoms from penetrating the gate metal due to ion implantation as described above, there is a first method of increasing the thickness of the gate metal film. However, with this method, the surface becomes extremely uneven and the source
There is a high probability that so-called step breakage will occur when forming wiring portions such as drains, which causes a decrease in yield. Further, from the viewpoint of microfabrication, the amount of side etching increases, which is inappropriate. Furthermore, an increase in strain such as internal stress due to thickening of the metal film also has an adverse effect on the performance of the element. For the above reasons, the method of increasing the thickness of the gate metal film is inappropriate.
第２の方法としては、ゲート金属膜表面を阻止
能の高い他の物質例えば、シリコン窒化膜や厚い
シリコン酸化膜等で被うことである。これらの被
膜はたとえばCVD法等々の手段で比較的容易に
形成できる。この第２の方法の一例を第２図に示
す。第２図ａは、素子分離用シリコン酸化膜１及
びゲート酸化膜２を形成した後、高融点金属３を
蒸着し、さらにその上にシリコン窒化膜２０を
CVD法で堆積し、MOSトランジスタのゲートと
なるべき部分を加工した断面図である。第２図ａ
は第１図ａに於けるゲート金属膜の上にシリコン
窒化膜を堆積したものになつている。第２図ｂ
は、シリコン窒化膜をマスクとしてイオン注入法
により、MOSトランジスタのソース及びドレイ
ン領域４を形成したものである。第２図ｃは、そ
の後シリコン窒化膜を熱リン酸で除去し、その上
に層間絶縁膜となるべきシリコン酸化膜６を厚く
堆積し、ソース、ドレイン及びゲート金属上の層
間絶縁膜に孔あけして、Al等の金属７でコンタ
クトをとり、配線部形成を行つたものである。こ
の第２の方法では、前記第１の手段のようにゲー
ト金属のみのマスク作用を利用してイオン注入法
によるソース、ドレイン領域を形成する方法に比
べて、シリコン窒化膜を堆積し、加工し、またそ
の後除去するという工程が新たにつけ加わるため
に、工程が長く複雑になりまた、ゲート金属の加
工精度も悪くなるという欠点がある。 A second method is to cover the surface of the gate metal film with another material having high stopping power, such as a silicon nitride film or a thick silicon oxide film. These films can be formed relatively easily by means such as CVD. An example of this second method is shown in FIG. In FIG. 2a, after forming a silicon oxide film 1 for element isolation and a gate oxide film 2, a high melting point metal 3 is deposited, and a silicon nitride film 20 is further formed on top of it.
FIG. 2 is a cross-sectional view of a portion deposited by the CVD method and processed to become the gate of a MOS transistor. Figure 2a
1A, a silicon nitride film is deposited on the gate metal film in FIG. 1A. Figure 2b
The source and drain regions 4 of the MOS transistor are formed by ion implantation using a silicon nitride film as a mask. In Figure 2c, the silicon nitride film is then removed with hot phosphoric acid, a silicon oxide film 6 that will become an interlayer insulating film is deposited thickly on it, and holes are made in the interlayer insulating film on the source, drain, and gate metals. Then, a contact is made with a metal 7 such as Al, and a wiring portion is formed. In this second method, a silicon nitride film is deposited and processed, compared to the first method in which the source and drain regions are formed by ion implantation using the masking effect of only the gate metal. Furthermore, since a new step of removing the gate metal is added, the process becomes longer and more complicated, and the processing accuracy of the gate metal also deteriorates.
本発明は、上記従来技術の欠点をなくし、かつ
高融点金属ゲートの特徴を生かした半導体装置の
製造方法を提供するものである。本発明に於て
は、少くとも、そのゲート電極配線の一部に下層
が高融点金属で構成され、その上層に高融点金属
の窒化物層が積層された２層構造膜を形成する工
程と、該ゲート電極配線を有する構造にイオン注
入により自己整合的にソース・ドレイン領域を形
成する工程を含む半導体装置の製造方法に特徴が
ある。高融点金属の窒化物は、高融点金属に比べ
て、結晶粒が小さく、さらに高融点金属のほとん
どが体心立方格子の結晶構造をとつているのに対
し、その窒化物は、面心立方格子の最密充填構造
をとつており、イオン注入に対するマスク作用が
大である。高融点金属が完全にアミルフアス状で
あれば、イオン注入時の加速電圧が100keVの時
1000Åの膜厚があれば貫通が阻止されることがわ
かつているが、3000Å程度の膜厚の場合も貫通が
起る。これは、前述したように、結晶粒界に沿つ
たり、チヤネリングによつて不純物原子が透過す
るものと考えられる。従つて高融点金属ゲートの
上にさらに結晶粒径の異なる、また、結晶構造も
異なる高融点金属の窒化物をつけ２層ゲート構造
にすることにより、貫通は完全に阻止される。さ
らに、上記窒化物は導電性であり、高融点金属の
比抵抗の10倍から20倍の値をもつているにすぎな
い。稀にこれらの窒化物が絶縁物であると信じて
いる方があるが、これは事実に反する。従つて、
前述のシリコン窒化膜をつけた場合のようにシリ
コン窒化膜を除去するというような工程は不要で
あり、このことも本発明の利点の１つである。 The present invention provides a method for manufacturing a semiconductor device that eliminates the drawbacks of the above-mentioned prior art and takes advantage of the characteristics of a high-melting point metal gate. In the present invention, there is a step of forming a two-layer structure film on at least a part of the gate electrode wiring, in which the lower layer is made of a high melting point metal and the upper layer is laminated with a nitride layer of the high melting point metal. The present invention is characterized by a method of manufacturing a semiconductor device including a step of forming source/drain regions in a self-aligned manner by ion implantation into a structure having the gate electrode wiring. Nitrides of high melting point metals have smaller crystal grains than high melting point metals, and most high melting point metals have a body-centered cubic lattice crystal structure, whereas nitrides have a face-centered cubic lattice crystal structure. It has a close-packed lattice structure and has a large masking effect for ion implantation. If the refractory metal is completely amilfous-like, when the accelerating voltage during ion implantation is 100keV
Although it is known that penetration is prevented with a film thickness of 1000 Å, penetration occurs even with a film thickness of about 3000 Å. This is thought to be due to impurity atoms permeating along grain boundaries or by channeling, as described above. Therefore, by further applying nitride of a high melting point metal having different crystal grain sizes and different crystal structures on the high melting point metal gate to form a two-layer gate structure, penetration can be completely prevented. Furthermore, the nitride is electrically conductive and has a resistivity that is only 10 to 20 times higher than that of the refractory metal. Some people believe that these nitrides are insulators, but this is not true. Therefore,
There is no need for a step of removing the silicon nitride film as in the case where the silicon nitride film is applied as described above, and this is also one of the advantages of the present invention.
以下本発明を実施例によつて説明する。第３図
ａに示すように素子分離用シリコン酸化膜１及び
ゲート酸化膜２を基板シリコン上に形成した後、
Arガス中でMoをスパツタリング法で堆積し厚さ
2000ÅのMo膜３２を形成する。その後、その状
態で、Arガス中にN2ガスを導入し、いわゆる反
応性スパツタリング法によつてMo窒化物３３を
1000Å蒸着する。Mo窒化物は、Mo対Ｎ元素の比
が２：１の化合物γMo2Nがf.c.c.構造をとつてお
り、本発明のMo窒化物として最も望ましい組成
であるが、Ｎ元素がそれよりも１桁少なくても、
結晶粒がMoに比して小さく、本発明の電極とし
て使用することができる。その後、上記Mo及び
Mo窒化物からなる２層金属をたとえばCF4系の
ガスによるプラズマエツチングで加工し、ゲート
電極とする。湿式法によつても加工することは可
能であるが、エツチング速度が異なるため、プラ
ズマエツチングの方が望ましい。ゲート電極加工
後、イオン注入法により、ソース及びドレイン領
域を形成したのが第３図ａに示す概略断面であ
る。第３図ｂは、その後、イオン注入層の活性化
を行い、層間絶縁膜６をつけ、ソース、ドレイン
及びゲート電極上の層間絶縁膜に孔あけし、Al
７でコンタクトをとり、配線部を形成し終つた後
の断面図である。第４図は、従来のMo単層ゲー
ト構造および本発明のMoおよびMo窒化物の２層
ゲート構造を持つたそれぞれのMOSトランジス
タのしきい値電圧とゲート膜厚との関係を示す図
である。実線で示した４１が本発明による２層構
造のもの、点線で示した４２が従来のMo単層の
ものである。但し、２層ゲートにおけるMo窒化
物はいずれも1000Å厚である。第４図から、本発
明による２層ゲート構造の場合、総膜厚が1500Å
以上であれば、十分、イオン注入時のマスク作用
があることがわかる。 The present invention will be explained below with reference to Examples. After forming a silicon oxide film 1 for element isolation and a gate oxide film 2 on the silicon substrate as shown in FIG. 3a,
Thickness of Mo deposited by sputtering method in Ar gas
A Mo film 32 of 2000 Å is formed. Then, in that state, N2 gas was introduced into the Ar gas, and Mo nitride 33 was formed by the so-called reactive sputtering method.
Deposit 1000Å. Mo nitride has an fcc structure of γMo 2 N, a compound with a Mo to N element ratio of 2:1, and is the most desirable composition for the Mo nitride of the present invention. At least,
Its crystal grains are smaller than that of Mo, and it can be used as an electrode in the present invention. Then, the above Mo and
A two-layer metal layer made of Mo nitride is processed by plasma etching using, for example, CF 4 gas to form a gate electrode. Although it is possible to process using a wet method, plasma etching is preferable because the etching speed is different. After processing the gate electrode, source and drain regions were formed by ion implantation, as shown in the schematic cross section of FIG. 3a. FIG. 3b shows that the ion implantation layer is then activated, an interlayer insulating film 6 is attached, holes are formed in the interlayer insulating film on the source, drain and gate electrodes, and the Al
7 is a sectional view after making contact and forming a wiring portion. FIG. FIG. 4 is a diagram showing the relationship between threshold voltage and gate film thickness of MOS transistors having a conventional Mo single-layer gate structure and the present invention's Mo and Mo nitride double-layer gate structure. . 41 shown by a solid line is a two-layer structure according to the present invention, and 42 shown by a dotted line is a conventional Mo single layer structure. However, the Mo nitride in the two-layer gate is 1000 Å thick. From Figure 4, in the case of the two-layer gate structure according to the present invention, the total film thickness is 1500 Å.
If the above is the case, it can be seen that there is a sufficient masking effect during ion implantation.
以上本発明によれば、自己整合可能な低抵抗ゲ
ート配線を持つ、安定なMOS型半導体装置が得
られる。また従来の高融点金属ゲートよりも薄い
膜でもマスク作用が完全であり、ゲート電極部の
段差が小さく、ソース・ドレインの配線に於て
も、段切れが少なくなる利点がある。また、高融
点金属の窒化膜は、耐酸化性が強く、下層の高融
点金属の保護という点からも望ましい素材であ
る。 As described above, according to the present invention, a stable MOS type semiconductor device having a low resistance gate wiring that can be self-aligned can be obtained. Furthermore, even a film thinner than a conventional high-melting point metal gate has a complete masking effect, has small step differences in the gate electrode portion, and has the advantage that there are fewer step breaks in the source/drain wiring. Further, a nitride film of a high melting point metal has strong oxidation resistance and is a desirable material from the viewpoint of protecting the underlying high melting point metal.
本実施例では、Mo層の上にMo窒化物層を形成
したが、異なる高融点金属の窒化物層を形成して
良いことは言うまでもない。またMoに替えて他
の高融点金属を用いることも当然有効である。有
効な高融点金属としてはMo以外にＷ、Ta、Ti、
Zr、Nb、Hf等があり、これらの高融点金属の窒
化物もまた前記Mo窒化物に替えて使用して良い
結果を得る。Ｗ窒化物としては、たとえばβ
W2Nが望ましく、これは、格子定数が4.118Åの
面心立方構造をもつている。Ta窒化物として
は、TaNが簿ましく、六方構造で格子定数は面内
で5.191Å軸方向で2.913Åである。 In this example, a Mo nitride layer is formed on the Mo layer, but it goes without saying that a nitride layer of a different high melting point metal may be formed. Naturally, it is also effective to use other high melting point metals in place of Mo. In addition to Mo, effective high melting point metals include W, Ta, Ti,
There are Zr, Nb, Hf, etc., and nitrides of these high melting point metals can also be used in place of the Mo nitride with good results. As W nitride, for example, β
W 2 N is preferred, and has a face-centered cubic structure with a lattice constant of 4.118 Å. TaN is the most economical Ta nitride, with a hexagonal structure and a lattice constant of 5.191 Å in the plane and 2.913 Å in the axial direction.
また本実施例ではMOS型半導体装置を上げた
が、接合型半導体装置の場合にも用いることがで
きるのは当然である。従つて以上の説明でゲート
電極配線等々とMOS型特有の表現を用いた個所
もあるが、これは実施の一例について具体化に表
現し本発明の本質を理解しやすくするための配慮
であり、本発明を限定する意味合いではない。 Furthermore, although a MOS type semiconductor device is used in this embodiment, it goes without saying that the present invention can also be used in a junction type semiconductor device. Therefore, in the above explanation, there are some places where expressions specific to the MOS type, such as gate electrode wiring, etc., are used, but this is for the purpose of concretely expressing an example of implementation and making it easier to understand the essence of the present invention. This is not intended to limit the invention.
第１図は、高融点金属をゲートに用いた従来の
MOSトランジスタ及びその製造工程を説明する
ための概念図であり、第１図ａは、ゲート金属加
工後の断面図、第１図ｂはゲート金属加工後、イ
オン注入によるソース・ドレイン領域形成後の断
面図である。図中１は、素子分離用シリコン酸化
膜、２はゲート酸化膜、３は高融点金属ゲート、
４はソース・ドレイン領域、５はチヤネル部分を
示す。
第２図は、イオン注入による不純物イオンの貫
通を阻止するためにシリコン窒化膜でゲート金属
上を被つた従来のMOSトランジスタ及びその製
造工程を説明するための概念図である。第２図ａ
は、高融点金属ゲート上をシリコン窒化膜で被つ
たところであり、第２図ｂは、高融点金属ゲート
及びシリコン窒化膜をイオン注入マスクとして、
ソース・ドレイン領域を形成した後の断面図であ
る。第２図ｃは、シリコン窒化膜をとつてAl配
線工程を終えたMOSトランジスタの断面図であ
る。図中１から４は第１図と同じ領域を示し、６
は層間絶縁膜、７はAlによる配線で、２０はシ
リコン窒化膜である。
第３図は、本発明の一実施例としてMOSトラ
ンジスタの例とその製造工程を説明するための概
念図である。第３図ａは、本発明による２層ゲー
ト電極形成後、イオン注入でソース・ドレイン領
域形成後の断面図であり、第３図ｂは、Al配線
工程終了後のMOSトランジスタの断面図であ
る。図中１から４は第１図と同じ領域を示し、６
は層間絶縁膜、７はAl配線であり、３２はMo
層、３３はMo窒化物層を示す。
第４図は、従来の所謂Moゲート構造と本発明
による２層ゲート構造のMOSトランジスタとに
ついてそのしきい値電圧とゲート膜厚との関係を
示したものである。図中、曲線４１は、本発明を
実施した２層ゲート構造の場合である。Mo窒化
物の膜厚は1000Å固定であり、横軸は全膜厚を示
す。曲線４２は、従来のMoゲートの場合であ
る。
Figure 1 shows a conventional gate using a high melting point metal.
These are conceptual diagrams for explaining a MOS transistor and its manufacturing process. FIG. 1a is a cross-sectional view after gate metal processing, and FIG. 1b is a cross-sectional view after gate metal processing and after formation of source/drain regions by ion implantation. FIG. In the figure, 1 is a silicon oxide film for element isolation, 2 is a gate oxide film, 3 is a high melting point metal gate,
Reference numeral 4 indicates a source/drain region, and reference numeral 5 indicates a channel portion. FIG. 2 is a conceptual diagram for explaining a conventional MOS transistor in which a gate metal is covered with a silicon nitride film to prevent impurity ions from penetrating through ion implantation, and its manufacturing process. Figure 2a
Figure 2b shows a high melting point metal gate covered with a silicon nitride film, and Figure 2b shows a high melting point metal gate and silicon nitride film used as an ion implantation mask.
FIG. 3 is a cross-sectional view after forming source/drain regions. FIG. 2c is a cross-sectional view of a MOS transistor after the silicon nitride film has been removed and the Al wiring process has been completed. In the figure, 1 to 4 indicate the same area as in Figure 1, and 6
is an interlayer insulating film, 7 is a wiring made of Al, and 20 is a silicon nitride film. FIG. 3 is a conceptual diagram for explaining an example of a MOS transistor and its manufacturing process as an embodiment of the present invention. FIG. 3a is a cross-sectional view after forming a two-layer gate electrode according to the present invention and forming source/drain regions by ion implantation, and FIG. 3b is a cross-sectional view of the MOS transistor after the Al wiring process is completed. . In the figure, 1 to 4 indicate the same area as in Figure 1, and 6
is an interlayer insulating film, 7 is an Al wiring, and 32 is a Mo
Layer 33 represents a Mo nitride layer. FIG. 4 shows the relationship between threshold voltage and gate film thickness for a conventional so-called Mo gate structure and a two-layer gate structure MOS transistor according to the present invention. In the figure, a curve 41 is for a two-layer gate structure in which the present invention is implemented. The film thickness of Mo nitride is fixed at 1000 Å, and the horizontal axis shows the total film thickness. Curve 42 is for a conventional Mo gate.
Claims (1)
が高融点金属で構成され、その上層に高融点金属
の窒化物層が積層された２層構造膜を形成する工
程と、該ゲート電極配線を有する構造にイオン注
入により自己整合的にソース・ドレイン領域を形
成する工程を含むことを特徴とする半導体装置の
製造方法。1. At least a step of forming a two-layer structure film in which the lower layer is made of a high melting point metal and the upper layer is laminated with a nitride layer of the high melting point metal on at least a part of the gate electrode wiring, and the gate electrode wiring is 1. A method of manufacturing a semiconductor device, comprising the step of forming source/drain regions in a self-aligned structure by ion implantation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3446380A JPS56130948A (en) | 1980-03-18 | 1980-03-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3446380A JPS56130948A (en) | 1980-03-18 | 1980-03-18 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56130948A JPS56130948A (en) | 1981-10-14 |
| JPS6262468B2 true JPS6262468B2 (en) | 1987-12-26 |
Family
ID=12414937
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3446380A Granted JPS56130948A (en) | 1980-03-18 | 1980-03-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56130948A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02260690A (en) * | 1989-03-31 | 1990-10-23 | Matsushita Electric Ind Co Ltd | Component fitting device of printed board |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0697667B2 (en) * | 1983-10-21 | 1994-11-30 | セイコーエプソン株式会社 | Method for manufacturing semiconductor device |
| JPS6154648A (en) * | 1984-08-24 | 1986-03-18 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH025477A (en) * | 1988-06-23 | 1990-01-10 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5365088A (en) * | 1976-11-22 | 1978-06-10 | Nec Corp | Semiconductor device |
-
1980
- 1980-03-18 JP JP3446380A patent/JPS56130948A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5365088A (en) * | 1976-11-22 | 1978-06-10 | Nec Corp | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02260690A (en) * | 1989-03-31 | 1990-10-23 | Matsushita Electric Ind Co Ltd | Component fitting device of printed board |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56130948A (en) | 1981-10-14 |
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