JPS6260341A - Semiconductor integrated circuit for telephone set - Google Patents

Semiconductor integrated circuit for telephone set

Info

Publication number
JPS6260341A
JPS6260341A JP19995485A JP19995485A JPS6260341A JP S6260341 A JPS6260341 A JP S6260341A JP 19995485 A JP19995485 A JP 19995485A JP 19995485 A JP19995485 A JP 19995485A JP S6260341 A JPS6260341 A JP S6260341A
Authority
JP
Japan
Prior art keywords
output
storage device
circuit
ram
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19995485A
Other languages
Japanese (ja)
Other versions
JPH073983B2 (en
Inventor
Kazuyuki Tanaka
和幸 田中
Yuji Hishiki
飛鋪 雄爾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP60199954A priority Critical patent/JPH073983B2/en
Publication of JPS6260341A publication Critical patent/JPS6260341A/en
Publication of JPH073983B2 publication Critical patent/JPH073983B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To prevent a call from being a wrong call when an address not written is called in error by writing a data end code (end code) to the 1st one digit or several digits of a telephone number at application of power. CONSTITUTION:A RAM 6 with an initializing signal input terminal is placed to the 1st digit or plural several digits of each telephone number storage address and the rest of the entire memory consists of a conventional RAM 7. An output 9 of a pulse generating circuit 8 is inputted to the RAM 6. The output 9 is inputted also to a control circuit 10 to initialize the control section. The output 11 of the memory is inputted to an output generating circuit 13 and an end code detection gate 14 from a READ/WRITE buffer 12. The output 15 of the detection gate 14 is inputted to a control circuit 10, and outputs 16-18 of the circuit 10 are inputted respectively to the output generating circuit 13, the buffer 12 and an address counter 1. As a result, when an end code is detected at the output of the RAM, the output, the read of the RAM and the increment of the address counter are stopped immediately.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、電話用ダイアラ−半導体集積回路(以下ダイ
アル機能Oと称する] 、iたはダイアル機能を内蔵し
た集積回路(以下IOと称する]に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a telephone dialer-semiconductor integrated circuit (hereinafter referred to as dialing function O), i or an integrated circuit with a built-in dialing function (hereinafter referred to as IO). Regarding.

〔発明の概要〕[Summary of the invention]

この発明は、書き換え可能な半導体記憶装置c以下RA
Mと称する〕全内蔵し電話番号全記憶するダイアラ−I
Cまたは同様のダイアル機能を内蔵するIOにおいて、
電源投入時に電話番号の最初の一桁乃至複数桁にデータ
終了符号C以下エンドコードと称する〕を書き込むこと
により、未嘗邑込みのアドレスが誤って呼び出された時
にまちがい電話となることを防止するものである。
This invention provides a rewritable semiconductor memory device c and below RA.
Called M] Fully built-in dialer-I that stores all phone numbers
In an IO with a built-in C or similar dial function,
By writing a data end code C (hereinafter referred to as an end code) in the first digit or multiple digits of the telephone number when the power is turned on, it prevents an incorrect call from being made when an address with a pre-existing address is called by mistake. It is.

〔従来の技術〕[Conventional technology]

従来の電話用ダイアラ−ICはメモリを有する場合、電
源投入時に逐一マニュアル操作でメモリクリアを行なう
ものと、ソフトウェアによりメモリをアクセスして初期
化するものとがあった。
When conventional telephone dialer ICs have a memory, there are those in which the memory is cleared manually each time the power is turned on, and those in which the memory is accessed and initialized by software.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、マニュアルでメモリクリアを行なうこと
は面倒であり、誤操作が介在する可能性もある。またソ
フトウェアでメモリをイニシャライズするためには、ア
ドレスを変化妊せながらメモリ金アクセスし初期化ブー
タラ讐き込むという操作を記憶する電話番号の数だけ繰
り返嘔ねばならず、その九めの回路は複雑でありかつ時
間もかかるという欠点を有していた。
However, manually clearing the memory is troublesome, and there is a possibility that an erroneous operation may occur. In addition, in order to initialize the memory using software, the operation of accessing the memory money while changing the address and running the initialization booter must be repeated as many times as there are phone numbers to be memorized, and the ninth circuit is This method has the drawbacks of being complicated and time-consuming.

そこで、この発明は、従来のこの様な欠点を解決するた
めに、電源投入時にハードウェア的にメモリの初期化を
行なうことにより、容易に且つ高い信顆性でダイアル機
能0の誤操作によるまちがい電話を防止することを目的
としている。
Therefore, in order to solve the above-mentioned drawbacks of the conventional technology, the present invention has been developed to initialize the memory using hardware when the power is turned on, thereby easily and with high reliability to prevent mistaken calls caused by incorrect operation of the dial function 0. The purpose is to prevent

〔問題点を解決するための手段〕[Means for solving problems]

上記問題点t−肩決するために、この発明は電話番号の
最初の一桁内至複数桁を記憶するRAMメモリセルに初
期化信号入力端子全役け、電源投入時にパワーオンリセ
ット信号等を用いて該RAMにエンドコードが書き込ま
れる様にした。
In order to solve the above problem, the present invention uses all initialization signal input terminals in the RAM memory cell that stores the first digit to several digits of a telephone number, and uses a power-on reset signal when the power is turned on. Then, the end code was written to the RAM.

〔作用〕[Effect]

上記の様に構成されたRAMを内蔵した電話用ダイアラ
ーエ0では電話番号未記入のアドレスがアクセスされる
と、エンドコードが読み出され。
In the telephone dialer 0 having a built-in RAM configured as described above, when an address without a telephone number is accessed, an end code is read out.

エンドコード検出ゲートの出力が制御回路に入力されて
厘ちにRAMのアクセスは停止され、出力発生回路の出
力も停止される。この六めまちがい電話が防止できるの
である。
As soon as the output of the end code detection gate is input to the control circuit, access to the RAM is stopped, and the output of the output generation circuit is also stopped. These six mistaken calls can be prevented.

〔実施例〕〔Example〕

以下にこの発明の実施例を図面にもとづいて説明する。 Embodiments of the present invention will be described below based on the drawings.

第1図においてRAMのアドレスカウンタ1の出力2,
3は、それぞれYアドレスデコーダ4,1アドレスデコ
ーダ5に入力されている。
In FIG. 1, output 2 of address counter 1 of RAM,
3 are input to a Y address decoder 4 and a 1 address decoder 5, respectively.

初期化信号入力端予信RAM5は、各電話番号格納アド
レスの最初の桁円至複数桁に位置し、他は通常のRAM
7によりメモリ全体が構成されている。初期化信号入力
端予信RAM5には、パルス発生回路8の出力9が入力
される。この出力9は、さらに制御回路10にも入力さ
れ、制御部の初期化を行なう。メモリの出力11は、R
EAD/WR工TKバッファ12より出力発生回路13
及びエンドコード検出ゲート14に入力される。検出ゲ
ート14の出力15が制御回路10に入力されて、制御
回路10の出力16 、17 、18がそれぞれ出力発
生回路13.RK A D / W R工TFiバッフ
ァ12.アドレスカウンタ1に入力される。この結果、
RAMの出力にエンドコードが検出されると頁ちに出力
、RAMの読み出し、アドレスカウンタのインクリメン
トが停止する。入力信号19は通常、同一集積回路上に
設けられたキーボードインターフェース回路(図示ちれ
ていない〕全通して外部のキーボード(図示されていな
い〕より入力される。
The initialization signal input end pre-read RAM 5 is located at the first digit to the first digit of each telephone number storage address, and the rest are ordinary RAM.
7 constitutes the entire memory. The output 9 of the pulse generation circuit 8 is input to the initialization signal input end prediction RAM 5. This output 9 is further input to the control circuit 10 to initialize the control section. The output 11 of the memory is R
Output generation circuit 13 from EAD/WR engineering TK buffer 12
and is input to the end code detection gate 14. The output 15 of the detection gate 14 is input to the control circuit 10, and the outputs 16, 17, and 18 of the control circuit 10 are respectively input to the output generation circuit 13. RK AD/W R Engineering TFi Buffer 12. Input to address counter 1. As a result,
When an end code is detected in the output of the RAM, page output, reading from the RAM, and incrementing of the address counter are stopped. Input signals 19 are typically input from a keyboard interface circuit (not shown) provided on the same integrated circuit and entirely from an external keyboard (not shown).

なお、第2図@)はRAM5の第1の詳細回路図、同様
に第2図(b) 、 to)はそれぞれRAM5の第2
、第8の詳細回路図である。
In addition, Fig. 2(b) and to) are the first detailed circuit diagram of RAM5, and Fig. 2(b) and to) are the second detailed circuit diagram of RAM5, respectively.
, is an eighth detailed circuit diagram.

〔発明の効果〕〔Effect of the invention〕

この発明は以上説明したように、簡単な構成でメモリの
初期化を行なうことKより、電話用ダイアラーエCのま
ちがい電話全防止できるという効果がある。
As explained above, the present invention has the effect of completely preventing wrong calls from the telephone dialer C by initializing the memory with a simple configuration.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の実施例のブロンねL第2図(ロ)、
 Cb) 、ω)は、それぞれこの発明にかかる初期化
信号入力端予信RAMの第1.第2及び第3の詳細回路
図である。 60.初期化信号入力端子性RAM 7、、RAM 80.パルス発生回路 10、、制御回路 131.出力発生回路 140.エンドコード検出ゲート 以上 出願人 セイコー電子工業株式会社 代理人 弁理士 最 上    務 重話用ギ濾体X看世湿6のためのプロ1す7回第1図
Fig. 1 shows the bronze L of the embodiment of this invention Fig. 2 (b);
Cb) and ω) are the first . FIG. 3 is a second and third detailed circuit diagram. 60. Initialization signal input terminal RAM 7, RAM 80. Pulse generation circuit 10, control circuit 131. Output generation circuit 140. End code detection gate and above Applicant Seiko Electronic Industries Co., Ltd. Agent Patent Attorney Mogami Professional for Gyrobody

Claims (4)

【特許請求の範囲】[Claims] (1)電源投入時にパルスを発生する回路と、前記パル
ス発生回路の出力によりその内容が初期化される初期化
信号入力端子付書き換え可能な記憶装置を各電話番号格
納アドレスの1桁目乃至最初の複数桁に持つ書き換え可
能な記憶装置と、前記書き換え可能な記憶装置の出力か
らデータ終了符号を検出する検出ゲートと、前記検出ゲ
ートの出力を受けて前記記憶装置の読み出しを停止する
制御回路と、前記制御回路により制御され前記記憶装置
から読み出されたデータに対応する出力を発生し、且つ
前記検出ゲートの出力を受けた前記制御回路によりその
出力発生が停止される出力信号発生回路とから成る電話
用半導体集積回路。
(1) A rewritable memory device with a circuit that generates a pulse when the power is turned on and an initialization signal input terminal whose contents are initialized by the output of the pulse generation circuit from the first digit to the beginning of each telephone number storage address. a rewritable storage device having multiple digits; a detection gate that detects a data end code from an output of the rewritable storage device; and a control circuit that stops reading the storage device upon receiving the output of the detection gate. , an output signal generation circuit that is controlled by the control circuit and generates an output corresponding to data read from the storage device, and whose output generation is stopped by the control circuit that receives the output of the detection gate. Semiconductor integrated circuits for telephones.
(2)前記初期化信号入力端子付記憶装置が、出力を互
いに他の入力に接続した2入力N@O@Rゲートとイン
バータとにより構成されることを特徴とする特許請求の
範囲第1項記載の電話用半導体集積回路。
(2) Claim 1, characterized in that the storage device with an initialization signal input terminal is constituted by a two-input N@O@R gate and an inverter whose outputs are connected to each other's inputs. The semiconductor integrated circuit for telephone described above.
(3)前記初期化信号入力端子付記憶装置が、出力を互
いに他の入力に接続した2入力NANDゲートとインバ
ータとにより構成されることを特徴とする特許請求の範
囲第1項記載の電話用半導体集積回路。
(3) A telephone according to claim 1, wherein the storage device with an initialization signal input terminal is constituted by a two-input NAND gate and an inverter whose outputs are connected to each other's inputs. Semiconductor integrated circuit.
(4)前記初期化信号入力端子付記憶装置が、出力を互
いに他の入力に接続した一対のインバータより成るフリ
ップフロップと、前記フリップフロップの一方の出力と
或る電位との間に電気的に接続されたスイッチング素子
とから構成されることを特徴とする特許請求の範囲第1
項記載の電話用半導体集積回路。
(4) The storage device with an initialization signal input terminal includes a flip-flop consisting of a pair of inverters whose outputs are connected to each other's input, and an electrical connection between one output of the flip-flop and a certain potential. Claim 1 characterized in that it is composed of a connected switching element.
Semiconductor integrated circuit for telephones as described in .
JP60199954A 1985-09-10 1985-09-10 Telephone semiconductor integrated circuit Expired - Lifetime JPH073983B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60199954A JPH073983B2 (en) 1985-09-10 1985-09-10 Telephone semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60199954A JPH073983B2 (en) 1985-09-10 1985-09-10 Telephone semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPS6260341A true JPS6260341A (en) 1987-03-17
JPH073983B2 JPH073983B2 (en) 1995-01-18

Family

ID=16416360

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60199954A Expired - Lifetime JPH073983B2 (en) 1985-09-10 1985-09-10 Telephone semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH073983B2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5599868A (en) * 1979-01-23 1980-07-30 Anritsu Corp Automatic dial unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5599868A (en) * 1979-01-23 1980-07-30 Anritsu Corp Automatic dial unit

Also Published As

Publication number Publication date
JPH073983B2 (en) 1995-01-18

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