JPH0227595A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To read information from two ports by making the gate of la floating type MOS transistor (TR) into a high-voltage rewriting signal line with the memory cell of an EPROM having the two ports, and connecting the word lines of the respective ports through the two MOS TRs at an N channel to the inputted to the gate to a digit line. CONSTITUTION:N-channel type MOS TRs T1 and T2 to transmit the information to a digit line 1 having an A port and a floating type MOS TR T3 constitute a memory cell. At the time of reading, first the input gate of the floating type MOS TR T3 is activated, and word lines 3 and 4 having the A port or a B port are selected. When '1' is read, since the TR T3 remains to be turned off, even when the word line is selected, the digit line remains at the high potential. Further, when '0' is read, since the TR T3 is turned on, by selecting the word line, the potential of the digit line is pulled. Thus, the information can be read from the two ports.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an erasable read semiconductor memory capable of reading from two ports, and more particularly to the structure of its memory cells.

[Conventional technology]

Typically, erasable readout semiconductor memory (hereinafter referred to as EP')
(referred to as ROM) is composed of one port of input/output terminals. Recently, as the field of application of EPROM has expanded, some users have begun to desire an EPROM that can be accessed asynchronously from two boards.

Conventionally, the memory cell configuration of a one-boat EFROM has a floating type MOS transistor connected to a word line and a digit line, as shown in FIG.

Write and read operations will be explained.

When writing "l", a high electric field is applied to the digit line and word line to accumulate negative charges in the floating gate.

When writing "0", the digit line remains in a high electric field, but if the word line is not selected, no charge is accumulated on the floating gate.

On the other hand, at the time of 1'' reading, the floating type MOS transistor remains off even if it is selected because negative charges are accumulated in the floating gate.

When reading '0', no negative charge is accumulated in the floating gate, so when selected, the floating type MO3) transistor is turned on.

Due to the configuration of the memory cells selected as described above, reading from two ports is clearly impossible.

[Problem to be solved by the invention]

Due to the structure of the conventional EPROM memory cells described above, it was impossible to read data asynchronously from two ports.

An object of the present invention is to improve such an EFROM memory cell so that reading can be performed from two ports.7', CE
The purpose of the present invention is to provide a PROM memory cell.

[Means to solve the problem]

The EFROM memory cell with two ports of the present invention uses the gate of a floating MOS transistor as a high-voltage rewriting signal line, and the word line of each boat as a gate input through two N-channel MOS transistors. It is characterized by being connected to each boat's digit line.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. In the embodiment shown in FIG. 1, 1 is a digit line in the A port, 2 is a digit line in the B port, 3 is a word line in the A port,
4 is a word line in the B boat, T1 is an N-channel MOS transistor that transmits information to the digit line of the A port, T3 is a floating MOS transistor,
This is a memory cell composed of three MOS transistors.

The operation will be explained with reference to FIG.

During writing, floating type MOS transistor T
The gate input and selected digital and digital lines of No. 3 are activated to a high electric field. After that, in the case of writing "1", a high electric field is applied to the word line of port A or port B to accumulate negative charge on the floating gate. If it is left in the selected state, charges will not be accumulated on the floating gate.

On the other hand, when reading, first activate the input gate of floating type MOS transistor T3 and select the word line of A boat or B boat.
3 remains off, so even if the word line is selected, the high potential of the digital and digital lines remains. In the case of '0' reading, the floating type MO3) transistor T3 is on, so by selecting the word line, the potential of the digit line is pulled.

That is, at the time of reading, the floating type MOS transistor is turned on/off depending on the presence or absence of negative charge in the floating type MOS transistor to transmit information to the next stage sense circuit. Here, the gate input of the floating type MOS transistor during reading may keep all memory cells activated at all times.

Since the memory cell of the present invention has a word line and a digit line for each of the A port and the B port, it is possible to access the memory cell asynchronously from both the A port and the B port.

〔Effect of the invention〕

As described above, since the present invention is a memory cell that can be read from two ports asynchronously, a complicated peripheral circuit of an arbiter circuit can be omitted, and the present invention has the effect of facilitating the design of a two-point EPROM.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a memory cell of the present invention. FIG. 2 is a circuit diagram of a conventional memory cell. 1... Digit line at A port, 2...
... Digit line on B boat, 3...
・Word line in A boat, 4... Word line 5 in B port... High voltage rewriting signal line, TI, T2... N channel type MOS transistor, T3 ...Floating type MO3)
Ranjista. Agent Patent Attorney Oto Uchihara

Claims (1)

[Claims] In an erasable read semiconductor memory that can be read from two ports, the memory cells constituting this memory have a floating MOS transistor whose gate is a high-voltage rewriting signal line, and a word line of each port. What is claimed is: 1. An erasable readout semiconductor memory connected to a digit line of each port through two transistors having gate inputs.