JPS6260315A - Counter circuit - Google Patents

Abstract

PURPOSE:To attain miniaturization of the titled circuit and low power consumption by providing a selection means switching the 1st prescribed setting value temporarily by a special external input signal to the 2nd setting value that is can be given externally. CONSTITUTION:An output of an OR circuit 3 ORing a period load pulse I and an external load pulse J inputted externally becomes a load pulse of a 1/N counter 1. On the other hand, an output of a selection circuit 4 selecting n-set of frequency division load values M and n-set of external phase designation values K is a load value of the 1/N counter 1. When no external load pulse J is inputted to the selection circuit 4, the 1/N counter 1 keeps counting from the frequency division load value M loaded to the 1/N counter 1 by a period load pulse 1 up to the decoded value L. So long as the period is N and the period of the external load pulse J is an integral number of multiple of the N, the external phase designation value K is loaded by the external load pulse J and the period N is unchanged even when the frequency division phase is changed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a counter circuit that divides and counts a clock signal using a digital circuit.

In particular, the present invention relates to a counter circuit whose frequency division phase can be changed externally.

〔overview〕

In a counter circuit that divides the frequency of an incoming clock signal, by temporarily changing the count setting value, the frequency division phase of the output of the counter circuit can be changed.

[Conventional technology]

FIG. 3 shows the configuration of a conventional counter circuit.

A 1/N counter 1 is driven by a clock H, and a decode circuit 2 compares one count output value with a decode value. When they match, a periodic load pulse I is output, which becomes a load pulse for a 1/N counter 1 with a period of N bits, and when this is input, a frequency-divided load value M is loaded into the counter. Figure 4 shows this operation as a time chart. Figure 4 (a) shows the clock H, Figure 4 (b) shows the count value of the 1/N counter, and Figure 4 (C1 shows the synchronous load represents pulse I.

In this circuit, it is possible to change the period N by changing the decode value or the division load value M, and by changing both the decode value and the division load value M, the count range can be changed without changing the period N. It is possible to change. However, in such a circuit configuration, if you want to change the division phase without changing the cycle of l/N counter 1, clock to pause.

[Problem that the invention seeks to solve]

In such a conventional circuit, when changing the division phase without changing the period of 1/N counter 1, clock I (is 1/
It is necessary to stop the N counter 1 after detecting the count value, and furthermore, the timing for starting the operation of the 1/N counter 1 needs to be calculated each time according to the value at which the Callan value is stopped. This results in drawbacks such as increased circuit scale, complexity, and increased power consumption.

The present invention aims to eliminate such drawbacks, and aims to provide a counter circuit in which the frequency division phase can be changed without changing the cycle by adding a small-scale circuit.

[Failure to solve the problem]

The present invention provides a counter circuit equipped with a counting means that sends an output every time a predetermined first setting value (LM) is counted for an incoming clock signal. It is characterized by comprising a selection means (4) for switching one set value to a second set value (L-K) which can be given from the outside.

[Effect]

When changing the frequency division phase without changing the period of the counter circuit that divides and counts, temporarily enable the selection means and load a setting value to the counting means that outputs a value different from the normal frequency division value. .

〔Example〕

Hereinafter, circuits according to embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of this embodiment circuit. Figure 2 is a time chart 1 showing the operation of this embodiment circuit.
・It is.

The 1/N counter 1 of the frequency jjlN pin is driven by the clock H and outputs a count value of 0. The decoding circuit 2, which compares this count output value with a decode value input from the outside, outputs a periodic load pulse I when the count output value and the decode value match. The output of the OR circuit 3 which takes the logical sum of the periodic load pulse I and the external load pulse J inputted from the outside becomes the load pulse of the 1/N counter l, while the divided load value M of 0 and the 0
The output of the selection circuit 4 which selects the specified external phase value becomes the load value of the 1/N counter 1. The selection circuit 4 loads the external phase designation value K into the l/N counter 1 when the external load pulse J is input, and otherwise loads the frequency division load value M at the time when the periodic load pulse ■ is output. 1/
Load into N counter 1.

The time chart shown in Fig. 2 (al, (b),
FC+ and (d) represent the clock H1 external load pulse J, the load value and count output value of the 1/N counter 1, and the periodic load pulse ■, respectively. Further, N is a period. When the "1" bit pulse of the periodic load pulse ■ shown in FIG. 2 (dl) is input, the frequency division load value M is loaded. After that, the value of the divided load value M is counted up by the clock H shown in FIG. 2 (al), but the "1" bit of the external load pulse J shown in FIG. 1/N when pulse is input
The external phase designation value K is loaded into the counter 1. After that, the value of the external phase designation value is counted up by the clock H shown in Fig. 2 (a), and when the counter output value becomes equal to the decoded value, the period is increased as shown in Fig. 2 (d). Load pulse ■ is output with a focus width of "1".

Here, if the external load pulse J is not input, the 1/N counter l is the divided load value M loaded into the 1/N counter l by the periodic load pulse The count continues from to the decode value.As long as this period is N and the period of the external load pulse J is an integral multiple of N, the external phase specified value K is loaded by the external load pulse J, and the divided phase is Even if it changes, the period N will not change.

〔Effect of the invention〕

As explained above, in the present invention, the phase of the 1/N counter can be specified externally, so there is no need to know the count value of the 1/N counter, and there is no need to calculate the start timing according to the count value. , Therefore, there is an effect that the circuit can be miniaturized and power consumption can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram showing the configuration of a circuit according to an embodiment of the present invention. FIG. 2 is a time chart showing the operation of the circuit according to the embodiment of the present invention. FIG. 3 is a block configuration diagram showing the configuration of a conventional circuit. FIG. 4 is a timing chart showing the operation of the conventional circuit. 1...1/N counter, 2...decoding circuit, 3...
...OR circuit, 4...selection circuit.

Claims (1)

[Claims] (1) A predetermined first setting value (
In a counter circuit equipped with a counting means that sends out an output every time LM) is counted, a second setting value (L A counter circuit characterized in that it comprises a selection means (4) for switching to -K).