JPS6260250A - Package - Google Patents

Package

Info

Publication number
JPS6260250A
JPS6260250A JP60199138A JP19913885A JPS6260250A JP S6260250 A JPS6260250 A JP S6260250A JP 60199138 A JP60199138 A JP 60199138A JP 19913885 A JP19913885 A JP 19913885A JP S6260250 A JPS6260250 A JP S6260250A
Authority
JP
Japan
Prior art keywords
semiconductor circuit
semiconductor
pad
package
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60199138A
Other languages
Japanese (ja)
Inventor
Kazuo Tanaka
和雄 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP60199138A priority Critical patent/JPS6260250A/en
Publication of JPS6260250A publication Critical patent/JPS6260250A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent poor bonding and thereby to protect a pad from peeling by a method wherein a conductor pattern for taking signals out of semiconductor circuits and a conducting tab, positioned between semiconductor circuits, are provided. CONSTITUTION:For the construction of wiring between a semiconductor circuit 2 and semiconductor circuit 3 inserted into a ceramic package 1, a wire 6 is used to bond a pad 4 of a semiconductor circuit 2 or semiconductor circuit 3 to a conductor pattern 5 that takes signals out of the semiconductor circuit 2 or 3. For the establishment of connection between the semiconductor circuits 2 and 3, a conducting tab 7 is installed between the semiconductor circuits 2 and 3. The semiconductor circuit 2 is wire-bonded to the conducting tab 7 and the semiconductor circuit 3 is also wire-bonded to the conducting tab 7, which establishes an electrical connection between the pad 4 of the semiconductor circuit 2 and the pad 4 of the semiconductor circuit 3. In a package designed as such, pads are protected from peeling, which improves reliability as well as manufacturing efficiency.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、中導体集積回路Ｑパッケージの改良に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to improvements in medium conductor integrated circuit Q packages.

〔発明の概要〕[Summary of the invention]

本発明は、２コ以上の半導体回路を相互配線するパッケ
ージにおいて、半導体回路から外部へ信号を取り出すた
めの導体パターンの他に、半導体回路間に導電性タブを
具備することにより、ワイヤーボンデイ／グＯ信頼性を
向上させると共に、タブＯ形状を変化させれば、交差し
たＰ［株］ｄのボデイングも確爽に行なえるようになる
も■である。The present invention provides a package in which two or more semiconductor circuits are interconnected, by providing a conductive tab between the semiconductor circuits in addition to a conductive pattern for extracting signals from the semiconductor circuit to the outside. By improving the reliability of the tab O and changing the shape of the tab O, it becomes possible to reliably perform crossed P [stock] d bodies.

〔従来の技術〕[Conventional technology]

従来、たとえば第２図に示すように、セラミックパッケ
ージ内１に、半導体回路２及び半導体回路３を挿入し、
相互配線を行なう場合、半導体回路２または半導体回路
３のパッド４から信号を外部に取り出すためＯ導体パタ
ーン５ヘワイヤボンデング６をする他に、半導体回路３
θパツドから半導体回路２のパッドに直接ワイヤボンデ
ィングする必要があった。Conventionally, for example, as shown in FIG. 2, a semiconductor circuit 2 and a semiconductor circuit 3 are inserted into a ceramic package 1,
When performing mutual wiring, in addition to wire bonding 6 to the O conductor pattern 5 in order to extract signals from the pad 4 of the semiconductor circuit 2 or the semiconductor circuit 3 to the outside,
It was necessary to perform wire bonding directly from the θ pad to the pad of the semiconductor circuit 2.

〔発明が解決しようとする問題点及び目的〕しかし、前
述の従来技術ではパッドから直接他■パツドヘボンディ
ングするため、半導体回路の相対的な位置のずれによる
ボンディング不良及びボンディング時に印加される引張
り力のためにパッド部が剥離してしまう、！ニーう問題
点があった。[Problems and objects to be solved by the invention] However, in the above-mentioned conventional technology, bonding is performed directly from a pad to another pad, resulting in poor bonding due to relative positional deviation of the semiconductor circuit and tensile force applied during bonding. The pad part peels off because of this! There was a problem.

本発明ｔｉｔこの様な問題点を解決するものでそＱ目的
とするところは、ボンディング不良及びパッド■剥離が
起こらないパッケージを提供することにある。The present invention aims to solve these problems and aims to provide a package in which bonding defects and pad peeling do not occur.

〔問題点を解決するため■手段〕[Means to solve the problem]

本発明■パッケージは、パッケージ内に２コ以上の半導
体回路を相互配線して封止する場合において、半導体回
路から外部へ信号を敗り出すためＱ導体パターンと、半
導体回路間に導電性タブを具備することを特徴とする。The present invention ■ When two or more semiconductor circuits are mutually interconnected and sealed within the package, the package includes a Q conductor pattern and a conductive tab between the semiconductor circuits in order to send signals from the semiconductor circuits to the outside. It is characterized by comprising:

〔実施例〕〔Example〕

以下、本発明について、実施例に基づき詳細に説明する
。Hereinafter, the present invention will be described in detail based on examples.

第１図（α）は、本発明の実施例である。セラミックパ
ッケージ内１に半導体回路２及び半導体回路３を挿入し
、相互配線を行なう場合、半導体回路２または半導体回
路３のパッド４から信号を外部に取り出すための導体パ
ターン５ヘワイヤーボンデイング６ケする他に、半導体
回路２■パツドから、半導体回路３０バツドヘボンデン
グするｓｈ、半導体回路２及び半導体回路３の間に導電
性タブ７を設け、半導体回路２から導電性タブ７までワ
イヤーボンデングし、半導体回路３から導電性タブ７ま
でワイヤーボンディングすることによって半導体回路２
のパッドと半導体回路３■パツドとを電気的に接続する
。FIG. 1(α) shows an embodiment of the present invention. When inserting the semiconductor circuit 2 and the semiconductor circuit 3 into the ceramic package 1 and performing mutual wiring, six wire bondings are performed to the conductor pattern 5 for taking out the signal from the pad 4 of the semiconductor circuit 2 or the semiconductor circuit 3 to the outside. Then, bonding is performed from the semiconductor circuit 2 pad to the semiconductor circuit 30 pad, a conductive tab 7 is provided between the semiconductor circuit 2 and the semiconductor circuit 3, and wire bonding is performed from the semiconductor circuit 2 to the conductive tab 7, The semiconductor circuit 2 is connected by wire bonding from the semiconductor circuit 3 to the conductive tab 7.
The pad of the semiconductor circuit 3 is electrically connected to the pad of the semiconductor circuit 3.

第１図（６）は、導電性タブ■形状を変化させることに
より、互いに交差したＰａｄ間の相互接続を示している
。FIG. 1(6) shows the interconnection between pads that cross each other by changing the shape of the conductive tabs.

以上、本発明の長所を具体例によって示したがこれらの
実施例はあくまで一実施例にすぎない。Although the advantages of the present invention have been shown above using specific examples, these examples are merely examples.

〔発明の効果〕〔Effect of the invention〕

以上述べたように、本発明のパッケージによれば、半導
体回路間に導電性タブを具備することにより、半導体回
路間の相対位置の変化、及びパッドに印加される引張り
力によるパッドの剥離がないため信頼性が向上すると共
に作業能率も高めることが出来た。またタブの形状を変
化させることにより交差したボンディングも確実に行な
える様になった。As described above, according to the package of the present invention, by providing the conductive tabs between the semiconductor circuits, there is no change in the relative position between the semiconductor circuits, and there is no peeling of the pads due to the tensile force applied to the pads. This not only improved reliability but also increased work efficiency. Also, by changing the shape of the tabs, cross-bonding can now be performed reliably.

【図面の簡単な説明】[Brief explanation of drawings]

→− 第１図（ｃＬ）　、　（ｂ）は本発明のパッケージＯ平
面図第２図は従来のパッケージの平面図 １：セラミックパッケージ（１部拡大）２：３＝半導体
回路 ４：パッド ５：導体パターン（の一部） ６：ワイヤ ７：タブ 以　　　上→- Fig. 1 (cL), (b) is a plan view of the package O of the present invention Fig. 2 is a plan view of a conventional package 1: Ceramic package (1 part enlarged) 2: 3 = semiconductor circuit 4: Pad 5: Conductor pattern (part of) 6: Wire 7: Tab or more

Claims (1)

【特許請求の範囲】[Claims] パッケージ内に２コ以上の半導体回路を相互配線して封
止する場合において、半導体回路から外部へ信号を取り
出すための導体パターンと、半導体回路間に導電性タブ
を具備することを特徴とするパッケージ。A package characterized by having a conductive pattern for extracting signals from the semiconductor circuits to the outside and conductive tabs between the semiconductor circuits, when two or more semiconductor circuits are interconnected and sealed within the package. .
JP60199138A 1985-09-09 1985-09-09 Package Pending JPS6260250A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60199138A JPS6260250A (en) 1985-09-09 1985-09-09 Package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60199138A JPS6260250A (en) 1985-09-09 1985-09-09 Package

Publications (1)

Publication Number Publication Date
JPS6260250A true JPS6260250A (en) 1987-03-16

Family

ID=16402772

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60199138A Pending JPS6260250A (en) 1985-09-09 1985-09-09 Package

Country Status (1)

Country Link
JP (1) JPS6260250A (en)

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