JPS6259952B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention aims to improve the performance of an automatic gain control circuit of a video signal processing circuit used in a video signal recording/reproducing device such as a video tape recorder.

In conventional automatic gain control circuits, when the level of the composite video signal deviates from the specified value, for example, the level of the synchronization signal is abnormally reduced, the synchronization signal separation circuit malfunctions, and the leading and trailing edges of the pedestal portion of the video signal are If an erroneous wide pulse is generated by performing a separation operation in the section, the control voltage that controls the automatic gain control circuit will become an abnormally large value, resulting in a very small gain of the automatic gain control circuit, resulting in a compound problem. There was a problem that the video signal output became small. This will be explained using FIGS. 1 and 2.

FIG. 1 shows an example of the configuration of a conventional automatic gain control circuit. When a composite video signal (I-A in FIG. 2) enters an input terminal 1, it passes through a variable gain amplifier circuit 2 and outputs from an output terminal 3. A composite video signal (FIG. 2 E-D) in which the leading end of the synchronization signal of the composite video signal is clamped by the clamp circuit 4 is supplied to the adder circuit 5. On the other hand, the composite video signal at the input terminal 1 is separated into a synchronization signal (E-B in FIG. 2) by a synchronization signal separation circuit 6, and a pulse delay circuit 7
Then, a reference pulse (FIG. 2, E-C) of a constant amplitude delayed by a certain period of time is generated and added to the adder circuit 5. Note that the polarity of the reference pulse and the polarity of the leading end of the synchronization signal of the composite video signal are applied in such a way that they are opposite to each other. The signal outputs added by the adding circuit 5 as described above become the signals shown in FIG. The difference voltage from the reference value is amplified in the error amplification circuit 9, and the amplification degree of the variable gain amplification circuit 2 is controlled, so that the peak voltage shown in _FIG . Keep the output video signal constant. However, when a composite video signal in which the synchronization signal is compressed as shown in Figure 2 Row A' is input to input terminal 1, the purpose is to detect the synchronization signal with a voltage of V _D from the tip of the synchronization signal. It is conceivable that the synchronizing signal cannot be detected, resulting in detection of the front edge of the front pouch and the rear edge of the back pouch, as shown in FIG. 2, row B'. Therefore, the reference pulse becomes a delayed wide pulse as shown in Figure 2, Row C', and overlaps with the video signal area after the trailing edge of the back pouch, so it is shown in Figure 2 as in the former case. By adding the low-C' reference pulse and the composite video signal shown by the low-D' dotted line, the peak voltage becomes low-C'.
The output shown at E' appears and the peak voltage becomes a high voltage of V _C2 . This makes the degree of amplification of the variable gain amplifier circuit 2 very small, and in order for the automatic gain control circuit to reach a balanced peak voltage V _C1 , the composite video signal is shown by the solid line in Figure 2, R-D'. A major problem was that only very small signals could be obtained.

The present invention provides an effective means for solving these problems, and will be described in detail below.

FIGS. 3 and 4 are circuit configuration diagrams and waveform diagrams for explaining the operation of the present invention, which will be explained below with reference to these figures. The composite video signal E-a in FIG. 4 applied to the input terminal 10 passes through the variable gain amplification circuit 11 and is output to the output terminal 12, and at the same time is output to the clamp circuit 1.
3, the tip of the synchronization signal is at a certain voltage (V _CL )
The signal is clamped and supplied to the adder circuit 14. On the other hand, the composite video signal at the input terminal 10 enters the synchronizing signal separation circuit 15 and separates the synchronizing signal E-b in FIG. 4 using the level of V _D (E-a) as a reference. The monostable oscillation circuit 16 is triggered by the leading edge of the synchronization signal obtained here to oscillate for a certain period of time (T), and using this pulse, the reference pulse generation circuit 19 generates the pulse width shown in FIG. A reference pulse with a constant amplitude and baseline level (V _CL ) is created and added to the adder circuit 14, and added to the clamped composite video signal to obtain an added output as shown in Fig. 4E, and the peak of the added output is determined. The voltage V _C1 is detected and held by the peak hold circuit 17,
It is transmitted to the error amplification circuit 18. However, the oscillation time T of the monostable oscillation circuit 16 is t ₁ <T<
It is assumed that t ₁ <+t ₂ (where t ₁ is the synchronizing signal pulse period and t ₂ is the back porch period). The error amplification circuit 18 detects and amplifies the difference voltage between the peak value voltage and another reference DC voltage to generate a control voltage to control the variable gain amplification circuit 11. Note that the variable gain amplifier circuit 11 used here is configured such that the gain decreases as the peak value voltage increases, and the gain increases as the peak value voltage decreases.

Next, a case where a normal composite video signal and an abnormal composite video signal in which the synchronization signal is shortened are input to the automatic gain control circuit of the present invention will be explained with reference to the operational waveform diagram in FIG.

First, the normal composite video signal E-a is input to the input terminal 10.
The operating waveforms in each part when the state is entered are as shown in FIG. 4A. When the synchronizing signal in the composite video signal is separated at a level V _D from the leading edge of the synchronizing signal as shown in E-a, a synchronizing signal E-b is obtained.
The monostable oscillation circuit 16 is triggered by the rising edge of the leading edge of this synchronization signal, and a pulse with a width of time T is generated.The pulse width is synchronized with the synchronization signal and the amplitude is constant in the reference pulse generation circuit 19. A reference pulse e-c is created in which the baseline level (V _CL in the figure) is regulated. Next, the leading end of the synchronization signal of the composite video signal that has passed through the variable gain amplification circuit 11 is clamped by a clamp circuit 13 (to V _CL in the figure), and the adder circuit 1
4 and the reference pulse E-c to obtain the addition output E-e. The peak value voltage (V _C1 ) of the addition output e is detected by the peak hold circuit 17 , and the difference voltage between it and a separately set reference DC voltage is detected and amplified by the error amplifier circuit 18 to obtain the gain of the variable gain amplifier circuit 11 . It controls the

When the reference DC voltage is set so that the automatic gain control circuit is balanced at the peak detection voltage V _C1 , the gain of the variable gain amplifier circuit is adjusted according to the magnitude of the input composite video signal so that the peak detection voltage becomes V _C1 . It is possible to obtain a composite video signal output that changes and is always at a constant level. Next, the operation when a composite video signal whose synchronization signal is abnormally shortened is input will be explained with reference to FIG. 4B. When the synchronizing signal separation circuit 15 attempts to separate the composite video signal low-a' with the synchronizing signal reduced using the voltage V _D from the leading edge of the synchronizing signal as a reference, it is ignored because the synchronizing signal is shrunken. A separation circuit may operate at the leading edge of the front porch and the trailing edge of the back porch of the composite video signal, and a pulse like low-b' may be output. In such a state, the monostable oscillation circuit 16 is triggered by the rising edge of the leading edge of the low-b' pulse appearing in the synchronizing signal separation circuit 15 as described above, and generates a time relationship as shown in low-c'. Generates pulses and uses reference pulse generation circuit 1
9, a reference pulse low c' having a pulse width of time T synchronized with the leading edge of the front porch, a constant amplitude and a constant base level (V _CL in the figure) is obtained.

Similar to the former, the input composite video signal passes through the variable gain amplifier circuit 11, and a clamp circuit generates a signal low d' (indicated by a dotted line) in which the leading edge of the synchronizing signal is clamped to the voltage _VCL . Therefore, as in the former case, when the above two signals are added by the adder circuit, the added output shown by the dotted line of low-e' is obtained, and the peak hold circuit 17 detects the peak voltage V _C3 . In this case, as in the former case, if the peak hold voltage is set to V _C1 and the automatic gain control circuit is balanced, the voltage V _C3 is smaller than V _C1 , so the gain of the variable gain amplifier circuit increases and the output increases. When the signal level reaches the signal level shown by the solid line of low-d', the added output voltage becomes as shown by the solid line of low-e', and the peak hold voltage also becomes V _C1 , and the automatic gain control device is balanced and a fixed level complex A video signal is obtained at the output terminal. Furthermore, a concrete example of the configuration shown in FIG. 3 is shown in FIG. In the figure, a variable gain amplifier circuit 11, a clamp circuit 13, and a synchronization signal separation circuit 15 are generally used, and an error amplifier circuit 1
Since 8 is a differential amplifier circuit, its explanation will be omitted.
16 surrounded by a dotted line is a monostable oscillation circuit, and the output pulse of the synchronous signal separation circuit 15 is connected to a capacitor C ₁ and a resistor.
The pulse is differentiated with respect to _R1 , and a thin pulse is passed through the diode _D1 to switch the switch transistor _Q1 , thereby triggering a monostable oscillator circuit composed of transistors _Q2 and _Q3 . The oscillation pulse width of this monostable oscillator circuit is determined by the resistor R ₃ and the capacitor C ₂ , and a positive constant width pulse is supplied to the circuit F surrounded by the dotted line through the emitter follower transistor Q ₄ . The circuit F has a function of generating a reference pulse for addition and adding the composite video signal of the clamp circuit 13. That is, the positive voltage pulse of the transistor Q ₄ is applied to the base of Q ₆ of the differential amplifier circuit consisting of transistors Q ₆ and Q ₇ , and the resistor
When a switching operation is performed based on the voltage determined by R ₈ and R ₉ , the collector of transistor Q ₇ has an amplitude of resistance R ₁₀ × current I ₀ , and a positive polarity equal to the oscillation pulse width of the monostable oscillation circuit. A reference pulse is obtained. On the other hand, the composite video signal with the tip of the synchronization signal clamped to the resistor _R10 is connected to the transistor.
It is supplied via the emitter follower of _Q5 , and the voltage corresponding to the composite video signal is supplied using the voltage at the tip of the synchronization signal as the lowest reference. As can be seen from the above, the voltage that is the sum of the reference pulse and the composite video signal is applied to the collector of transistor _Q7 .
Current amplification is performed by the emitter follower of _Q8 , and the peak value voltage is rapidly held in the capacitor _C3 . Note that the resistor _R13 is a resistor for gradually discharging the charge of _C3 , and 17 surrounded by a dotted line is a peak hold circuit. In the above explanation, the composite video signal supplied to the synchronization signal separation circuit 15 is input to the input terminal 10.
However, it goes without saying that the same operation can be performed even if the signal is obtained from the output of the variable gain amplifier circuit 11.

As you can see from the previous explanation, since the leading edge of the synchronization signal separation output is used to create a reference pulse of a constant width, it is difficult to separate the synchronization signal, resulting in errors such as the one shown in Figure 4, row a'. It is possible to perform high-performance and stable automatic gain control that does not cause malfunctions even for signals, and a great effect can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional example of an automatic gain control device, FIG. 2 is an operation waveform diagram for explaining the operation of the same device, and FIG. 3 is a block diagram showing an embodiment of the automatic gain control device according to the present invention. 4 are operation waveform diagrams of various parts for explaining the operation of the device, and FIG. 5 is a concrete example of a circuit according to the present invention. 11... Variable gain amplifier circuit, 13... Clamp circuit, 14... Adder circuit, 15... Synchronous separation circuit, 16... Monostable oscillation circuit, 17... Peak hold circuit, 18... Error amplifier circuit, 19 ...Reference pulse generation circuit.

Claims (1)

[Claims] 1. A synchronization signal separation circuit that extracts a synchronization signal from a composite video signal, and a period that is triggered by the leading edge of the output of the synchronization signal separation circuit and is at least longer than the synchronization signal pulse period and longer than the sum of the synchronization signal pulse period and the back porch period. a reference pulse generation circuit that generates a pulse with a short constant pulse width and a constant amplitude; a variable gain amplifier circuit that amplifies the composite video signal; and a synchronization signal tip of the composite video signal output from the variable gain amplifier circuit. The addition circuit includes a clamp circuit that fixes the potential to a constant potential, and an addition circuit that adds the reference pulse and the synchronization signal of the clamped composite video signal so that the polarities of the signals are opposite to each other. An automatic gain control device characterized in that it detects a peak value of a summation output and controls the variable gain amplifier circuit according to the detected peak value voltage.