JPS625658A - Hetero junction bipolar transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce the capacity by forming a semi-insulation between a collector region and a base electrode leading layer, and reducing the areas of emitter- base and base-collector junctions smaller than that of an emitter electrode leading semiconductor layer. CONSTITUTION:An SiO2 film is formed on a semi-insulating GaAs substrate 16, a resist mask is formed, and etched in a mesa shape to expose a collector electrode leading GaAs layer 17. Then, an Al1Ga1-xAs emitter layer 20 and a collector 18 are merely selectively etched from the section of the mesa to recess the emitter. Then, the resist is removed, and a semi-insulating AlyGa1-yAs film 22 and a P-type GaAs film 23 are formed. Then, a resist mask is formed on emitter and base forming portions, and etched to expose a collector electrode leading GaAs layer 17. Then, the resist and the SiO2 film are removed to form ohmic electrodes 34-26. Thus, the collector and emitter capacities are reduced while holding the easiness of leading the base electrode to improve high frequency characteristics.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a beterojunction bipolar transistor with excellent high frequency characteristics.

Prior Art A typical structure of a conventional bipolar transistor is shown in FIG. In the figure, 1 is an n-type silicon substrate, 2 is an n-type collector provided thereon by epitaxial growth, 3 is a p-type base provided by diffusion, 4 is an n-type emitter provided by diffusion or alloy, 6 is a collector electrode, 6 is a base electrode, and 7 is an emitter electrode.

Although this is an npn transistor, a pnp transistor may also be used. This example uses the same semiconductor material, silicon, to form the emitter, base, and collector.

By the way, it is known that when the emitter is formed using a semiconductor having a higher forbidden band energy than the base, a very high current gain can be obtained.

This is because by appropriately selecting materials, the band structure of the emitter-base junction can be configured so that it does not provide a weak barrier to electrons, but provides a large barrier to holes. A typical example is the emitter with 1xG
This is IL1-xAS using GaAs for the base and collector.

Furthermore, it is known that such a structure can significantly improve high frequency characteristics. The maximum cutoff frequency Fc of the bipolar transistor is FC=1/(2πRbCc) (1) Rbi
Base resistance CC: It is formed by collector capacitance. As mentioned above, if the emitter is formed using a semiconductor with higher forbidden band energy than the base,
By appropriately selecting materials, the band structure of the emitter-base junction can be changed to a structure that is not a weak barrier to electrons.
It can be configured to provide a large barrier to holes. Therefore, the carrier concentration (hole concentration) of the base can be made very high. Therefore, the base resistance can be made extremely small, and as a result, a very large maximum cutoff frequency Fc can be obtained.

However, obtaining this structure is extremely difficult in terms of process. In particular, when attempting to shorten the base length in order to improve high-frequency characteristics, it becomes difficult to remove the base electrode.

FIG. 5 shows a conventional example (Japanese Patent Publication No. 55-3829) in which the extraction of the base electrode is improved. In the figure, 8 is n
type caAs substrate, 9 is n-type GaAs forming the collector
, 10 is p-type σaAs forming the base, 11 is n-type 1xGa1-xAs forming the emitter, 12 is p-type 1xGa1, As, 13 is for taking out the base electrode.
14 is a collector electrode, 14 is a base electrode, and 15 is an emitter electrode.

First, layers 9, 1o, and 11 are formed on a GaAs substrate 8 by a liquid phase epitaxial method. Next, a part of the collector layer 9 is exposed by mesa etching, and a p-type "lx (r a 1-x
An As layer is formed and an electrode is formed on each layer.

Problems to be Solved by the Invention In such a conventional configuration, the collector capacitance and emitter capacitance are still large, and therefore it is not possible to obtain sufficiently excellent high frequency characteristics. The present invention has been made in view of the above, and an object of the present invention is to provide a structure with small collector capacitance and emitter capacitance while maintaining ease of taking out the base electrode.

Means for Solving the Problems In order to solve the above problems, the present invention forms a semi-insulating semiconductor layer between the collector region and the layer for exposing the base electrode region, thereby making it easier to take out the base electrode. To provide a structure in which the emitter capacitance is small by making the area of the emitter base junction and the base-collector junction part smaller than the area of the semiconductor layer for taking out the emitter electrode. It is something.

Effects The present invention improves high frequency characteristics because the collector capacitance and emitter capacitance are reduced by the above-described structure.

Example FIG. 1 shows an embodiment of the structure of the present invention.

In FIG. 1, 1e is a semi-insulating QaAs substrate, 17 is an n+ type Ga layer, and 18 is an n type GaAs layer.
kuta layer, 19 is p-type GaAs base layer, 2) is n-saint 7
IxGa1-xAS emitter layer (x=0.3), 21 is an n-type GaAs layer for electrode extraction, 22 is 17 (7)
A semi-insulating layer formed on the n+ type Ga S collector layer (7=0.3), 23 is 2
A p-type GaAs layer is formed on 2 and adjacent to the p-type GaAs base layer 19, 24 is a collector electrode, 25 is a base electrode, and 26 is an emitter electrode.

The bonding area between the emitter layer and the base layer 2o and the bonding area between the collector layer 18 and the base layer are smaller than the area of the GaAs region 21 formed thereon for exposing the emitter electrode area. .

The thickness of each layer is 400μ for the 160 semi-insulating GaAs substrate.
m, 17 n+ type GaAs layers are 40 QO people, 18 n type G2LA5rL/kuta layers are 2)00 people, 19 p type Ga
As base layer is 1000 people, 2) n-type mum 1xGa1-
The xAs emitter layer is 15ooX, and the n-type Gaps layer for taking out the 21 GaAs electrodes is 1sooX.

22) Semi-insulating AlyGa1-As layer is 1esooX
.

The p-type GaAs layer of 23 is 2)00X. 17-23
Each layer of was formed by molecular beam epitaxy (MBE).

Next, a method of manufacturing an element having the structure of this example will be described.

First, layers 17 to 21 were formed to a predetermined thickness on a semi-insulating GaAs substrate 16 by molecular beam epitaxy. Next, by chemical vapor deposition (CYD) method, 30%
A 00X S i 02 film was formed. Next, a resist mask is formed by a normal photolithography method, and using this resist mask, as shown in FIG.
The s-layer was exposed. In FIG. 2, 27 is a 5i02 film and 28 is a resist. Etching of S i 02 is performed using 1(F (hydrofluoric acid)), G+aAs, AJxGa
The etching of lxAs is H2so4-H2O2-H
2) 2) Conducted using a membrane.

Next, using a KKI-r2-H2) based etching solution, only the M1xG2L1-xAS emitter and collector parts were selectively etched from the cross section of the mesa part, and the emitter part was recessed into a concave shape as shown in FIG. The depth of the depression could be arbitrarily controlled by changing the etching time.

Next, the resist was removed with acetone, and a semi-insulating AlyGa1. A 2)00X p-type GaAs film was formed. The film formed on the n+GaAS of No. 17 was epitaxially grown and was a perfect single crystal film, but the film formed on the 5i02 film was a polycrystalline film. H2S04-H2O2-
H2) 2) When etching is performed using a film, there is a large difference in etching speed between the single crystal film and the polycrystalline film, and the polycrystalline film can be removed while the newly grown single crystal film is hardly etched. Ta.

Next, by photolithography, a resist mask is formed on the portion where the emitter and base will be formed, and using this resist mask, each layer of 18 to 23 is formed using H2SO4.
The GaAs layer for taking out the collector electrode was exposed by etching using a mixed solution of -H2O2-a, , and o.

Next, the resist portion was removed with acetone and the 5i02 film was removed with HF, and ohmic electrodes of p 24 , 25 , and 26 were formed using conventional photolithography, vacuum evaporation, and heat treatment techniques.

The collector capacitance Cc of the structure of this example is 18 and 19 pn.
It is the sum of the junction capacitance of the junction and the junction capacitance of the junctions 22 and 23.

In general, the capacitance Cpn of a pn junction is a; junction area q; charge NA1; acceptor concentration of p-type semiconductor ND2H donor concentration of n-type semiconductor ε1; dielectric constant of p-type semiconductor ε2; dielectric constant of n-type semiconductor vb; Given.

From this, it can be seen that when the difference between the acceptor concentration and the donor concentration is large, the difference is approximately determined by the smaller one. In this example, the acceptor concentration of the p-type GaAs base layer is 1.1019/c7j1, and the donor concentration of the n-type GaAs collector layer is 5.1019.

Therefore, the collector capacitance is approximately Cj p n oc V "" (3).On the other hand, the
The junction capacitance with the 2L1-yAs layer is semi-insulating! A Ga
1-Since the acceptor concentration of the S layer is less than 1·1014//i, the junction capacitance is proportional to the square root of this acceptor concentration, and its value is much smaller than the value in equation (3). becomes. If there is no semi-insulating layer, 22
The junction capacitance of For the above reasons, as in this example, the p-type base electrode removal GaAs layer and the n-type GaAs
By forming a semi-insulating layer between the collector layer and the collector layer, the collector capacitance can be made much smaller if the structure has the same area.

In this example, AlyGa1-As is used as the semi-insulating layer.
(0,3), but y=o In other words, even if GaAs is used, the collector capacitance will not be reduced.
It is clear that they have the same effect.

In this example, y=0.3 was used, but if y>0.3 βA G&, -yAs is used, the forbidden band energy is larger than that of the collector, so it is better to take out the p-type base electrode. Leakage current between the GaAs layer and the n-type collector layer can be further reduced.

Since leakage current reduces the current amplification factor of the transistor, the current amplification factor can be improved by reducing the leakage current.

In this embodiment, the area of the collector base junction is further made much smaller than the area of the GaAs portion for taking out the emitter by etching, so that the collector capacitance is further reduced.

The area of the collector paste junction can be arbitrarily controlled by changing the etching time.

Furthermore, the maximum frequency yt at which the current amplification factor of the transistor is 1 is Ft=(1/2π)-(A-Ce+B) (4)Ce
; It is given by emitter capacitance m+Bi constant. (S, M, Sze; Physics
f'Sem1conductor Devices,
John Wiley & 5ons, Inc.
pp, 283.1969. ) Therefore, by reducing the emitter capacitance Go, the high frequency characteristics can be improved.

This has been known for a long time, but due to the limitations of photolithography technology, mask dimensions below a certain level cannot be obtained, so the conventional method (the area of the base-emitter part is However, it was not possible to obtain a device with an emitter-base junction area below that limit.

In this embodiment, the area of the emitter-base junction is made very small by machining and etching, and Ce (Ce is proportional to the area of the emitter-base junction) is small, so that the high frequency characteristics are improved.

The heterojunction bipolar transistor obtained in this example exhibited the following characteristics as expected.

First, we were able to form a good ohmic electrode on a very thin base of 1oooX. In addition, since the collector capacitance and emitter capacitance have become extremely small, the high-frequency characteristics are greatly improved compared to conventional products when the dimensions are the same.

In this example, the semi-insulating semiconductor layer is formed on the n-type GaAs layer for taking out the collector electrode, but
It is clear that the same effect can be obtained even if it is formed on a GaAs type collector layer.

Further, in this embodiment, molecular beam epitaxy was used to obtain a predetermined structure, but it can also be created using, for example, metal organic chemical vapor deposition (Mo-CVN) method.

In this embodiment, the semiconductor is G2LA! ! -A.J.
Although xG&1-xAs was used, other semiconductor materials such as InP-InGaAsP can also be used. In addition, Aββ variation was used, and X-〇, 3, y-〇, 3 were used, but this can be arbitrarily selected within the range of Q to 1. When the value of X is large, it is possible to use HF as a selective etching solution for the emitter layer.

Further, in this example, a 5i02 film was used, but Si, 3N
A film made of other materials such as No. 4 may also be used.

In this embodiment, the emitter and collector are n-type and the base is p-type, but if the emitter and collector electrode types and the base are n-type, the base extraction layer may be n-type.

Further, in this embodiment, the substrate side is used as the collector, but it is clear that similar characteristics can be obtained even if the substrate side is used as the emitter, since the structure is symmetrical.

Effects of the Invention As described above, the present invention provides a heterojunction bipolar transistor with excellent high frequency characteristics by significantly reducing the collector and emitter capacitance while maintaining the ease of taking out the base electrode. .

[Brief explanation of drawings]

FIG. 1 is a diagram showing one embodiment of the present invention, FIG. 2 and FIG.
The figure is a structural diagram of a device in the process of manufacturing to realize the structure of the present invention.
Figure 4 is a structural diagram of a conventional bipolar transistor, Figure 5
The figure is a structural diagram of a conventional heterojunction transistor. 16... Semi-insulating GaAs substrate, 17...
...n+G & human S layer, 18...n-type GaAs collector layer, 19...pWGaAs base! ,2
)・・・・・・n saint JxGa1-xAszmitta layer,
21'・-・-・n + GaAs layer, 22...
...Semi-insulated resident 1xG2L1-xAS layer, 23...
...p-type Gaps layer, 24...collector electrode,
25...Base electrode, 26...Emitter electrode, 27...S i 02 film, 28...
...Resist. Name of agent: Patent attorney Toshio Nakao and 1 other person d-
Collector Figure 2 To N 1N2 'NN5 Figure 4 Figure 5v! J

Claims (4)

[Claims] (1) It has at least an emitter region, a semiconductor layer for taking out an emitter (collector) electrode provided adjacent to this, a base region, and a collector region, and the emitter and collector have a higher forbidden band energy than the semiconductor forming the base. furthermore, the emitter, base junction and base, collector junction area are smaller than the area of the semiconductor layer for taking out the emitter (collector) electrode, and the area for taking out the collector (emitter) or the collector (emitter) electrode. a semi-insulating layer on a part of the substrate, and electrical contact to the base is made through a semiconductor region provided on the semi-insulating layer in contact with at least the base region. junction bipolar transistor. (2) The heterojunction bipolar transistor according to claim (1), wherein a semiconductor having a higher forbidden band energy than the semiconductor forming the base is used as the semi-insulating layer. (3) Form a collector (emitter) extraction semiconductor layer on the semiconductor substrate using the same semiconductor that forms the base, and then use a semiconductor that has a higher forbidden band energy than the semiconductor that forms the base. Collector (emitter)
forming a base region thereon, forming an emitter (collector) region thereon using a semiconductor having a higher forbidden band energy than the semiconductor forming the base;
A semiconductor layer for forming an emitter (collector) electrode is formed thereon, and a part of the emitter, base, and collector region is left in a mesa (plateau) shape by etching using an insulating film mask. The semiconductor layer for taking out the collector (emitter) is exposed, and only the emitter layer and the collector layer are etched in a concave shape using a selective etching solution, and then the exposed semiconductor region for forming the collector (emitter) electrode and the A semi-insulating layer is formed on the insulating film mask, a semiconductor region is formed on the semi-insulating layer in contact with at least the base region, the insulating film mask is removed by etching, and the semiconductor region and the semi-insulating layer are removed by etching. A portion of the insulating layer is removed by etching to form the collector (
1. A method for manufacturing a heterojunction bipolar transistor, characterized in that a part of a heterojunction bipolar transistor (emitter) is exposed, and an emitter electrode, a base electrode, and a collector electrode are formed in the emitter layer, the semiconductor region, and the collector region, respectively. (4) The method for manufacturing a heterojunction bipolar transistor according to claim (3), wherein a semiconductor having a higher forbidden band energy than the semiconductor forming the base is used as the semi-insulating layer.