JPS625635A - Forming method for electrode of electronic device - Google Patents

Forming method for electrode of electronic device

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Publication number
JPS625635A
JPS625635A JP14620685A JP14620685A JPS625635A JP S625635 A JPS625635 A JP S625635A JP 14620685 A JP14620685 A JP 14620685A JP 14620685 A JP14620685 A JP 14620685A JP S625635 A JPS625635 A JP S625635A
Authority
JP
Japan
Prior art keywords
film
electrode
melting point
silicon
point metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14620685A
Other languages
Japanese (ja)
Inventor
Eiji Nagasawa
長澤 英二
Hidekazu Okabayashi
岡林 秀和
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP14620685A priority Critical patent/JPS625635A/en
Publication of JPS625635A publication Critical patent/JPS625635A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To obtain an ohmic electrode having heat resistance of 550 deg.C or higher for a sinter by accumulating a high melting point metal on the surface of a silicon, ion implanting, then annealing to selectively form a silicide layer, heat treating in nonreduced atmosphere, and then forming aluminum electrode wirings which contain Si. CONSTITUTION:A field oxide film 12 is formed on a P-type single crystal Si substrate 11. After the surface of a silicon is then cleaned, an Mo film 13 is formed by sputtering. Then, Si ions are implanted through the film 13 to mix the boundary of the substrate 11 and the film 13. Subsequently, after As ions of dopant ions are implanted, it is annealed at 550 deg.C in H2 gas, an unreacted Mo film on the film 12 is then etched to selectively form an MoSi2 film 14, and an As doping layer 15 is formed in a self-aligned manner on the film 14. Thereafter, after an interlayer SiO2 film 16 is accumulated, a heat treatment of 900 deg.C is performed, a contacting hole is then formed, an Al-Si film is then formed, and A-Si electrode wirings 17 are formed by photoetching.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明はアルミニウム系金属を電極配線に用いたシリコ
ン半導体デバイスの耐熱性があるオーミックス電極及び
ショットキー電極の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method for manufacturing heat-resistant ohmic electrodes and Schottky electrodes for silicon semiconductor devices using aluminum metal for electrode wiring.

(従来の技術) アルミニウム系金属を電極配線として使用したオーミッ
ク電極やシミツトキー電極において、アルミニウム系電
極配線形成後に行うシンターに対する耐熱性を向上させ
たオーミック電極の従来の製造方法としては、例えば、
ジャーナル・オプーアプライドーフィジックス(Jou
rnal  ofApplied  phy81e3)
誌第50巻第11号第6915〜6926頁(1979
年)に記載されている様に、電極を形成すべきシリコン
表面に高融点金属であるMoを堆積した後、6000C
のアニールを行って〜2500AのMo S i 2を
形成した後アルミニウム電極配線を形成する方法が知ら
れている。この方法は熱反応で形成したMo511gを
アルミニウムとシリコンとの相互拡散を防止するための
バリヤ層として用いることを意図したものである。
(Prior Art) Conventional manufacturing methods for ohmic electrodes and scimitar key electrodes that use aluminum-based metal as electrode wiring have improved heat resistance against sintering performed after aluminum-based electrode wiring is formed, for example.
Journal of Applied Physics (Jou)
rnal of Applied phy81e3)
Magazine Vol. 50 No. 11 No. 6915-6926 (1979
After depositing Mo, a high melting point metal, on the silicon surface where electrodes are to be formed, as described in
A method is known in which aluminum electrode wiring is formed after annealing is performed to form MoSi2 of ~2500A. This method is intended to use Mo511g formed by thermal reaction as a barrier layer to prevent interdiffusion between aluminum and silicon.

(発明が解決しようとする問題点) しかしながら、前記従来法で形成したオーミック電極に
534℃、30分間のシンターを実施した場合、熱反応
で形成したMo S i、膜内のピンホール等を介して
Mo S i !層下のシリコンがアルミニウム電極配
線中へ移送され、Mo S i 2膜のバリヤ性がない
ことが示されている。高融点金属シリサイドがシンター
に対して不十分な耐熱性しか示さない大きな要因は、熱
反応で形成される高融点金属シリサイド膜の膜質の不均
一性にある。
(Problems to be Solved by the Invention) However, when the ohmic electrode formed by the conventional method is sintered at 534°C for 30 minutes, MoSi formed by the thermal reaction and pinholes in the film are removed. Te Mo Si! It is shown that the underlying silicon is transferred into the aluminum electrode wiring and lacks the barrier properties of the Mo Si 2 film. A major reason why high melting point metal silicide exhibits insufficient heat resistance against sintering is the non-uniformity of the film quality of the high melting point metal silicide film formed by thermal reaction.

本発明の目的はシンターに対して少なくとも550℃の
耐熱性を持ったオーミック電極及びショットキー電極の
製造方法を提供することにある。
An object of the present invention is to provide a method for manufacturing an ohmic electrode and a Schottky electrode that have a heat resistance of at least 550° C. against sintering.

(問題点を解決するための手段) 本発明によれば、電極を形成すべき単結晶シリコン表面
又は多結晶シリコン表面に高融点金属を堆積する工程と
、イオン注入を行って該高融点金属と前記シリコン表面
との界面を混合させ、400〜600’Cのアニールを
行ない、その後1反応せずに残った高融点金属をエツチ
ング除去し、前記高融点金属のシリサイド層を前記電極
を形成すべき単結晶シリコン表面又は多結晶シリコン表
面に選択的に形成する工程と、800℃以上の温度で非
還元性雰囲気で熱処理を行う工程と、前記シリサイド層
の表面にSiを含むAA’it極配線を接触させて形成
する工程とを含むことを特徴とする電子デバイスのに極
の形成方法が得られる。
(Means for Solving the Problems) According to the present invention, there are a step of depositing a high melting point metal on a surface of single crystal silicon or a surface of polycrystalline silicon on which an electrode is to be formed, and a step of depositing a high melting point metal on the surface of single crystal silicon or polycrystalline silicon on which an electrode is to be formed, and performing ion implantation to deposit the high melting point metal. The interface with the silicon surface is mixed, annealing is performed at 400 to 600'C, and then the high melting point metal remaining without any reaction is etched away, and the silicide layer of the high melting point metal is formed into the electrode. A process of selectively forming on a single crystal silicon surface or a polycrystalline silicon surface, a process of heat treatment in a non-reducing atmosphere at a temperature of 800°C or more, and an AA'it electrode wiring containing Si on the surface of the silicide layer. A method for forming a pole of an electronic device is obtained, the method comprising the step of contacting the electrode.

(作用) 本発明においてアルミニウム系電極配線とシリコン表面
との間にバリヤメタルとして介在させる高融点金属シリ
サイドは、シリコン表面に形成された高触点金属膜を通
してイオン注入を行ってシリコン表面と高融点金1iA
 Ilとの界面を混合させた後、400〜600℃のア
ニールを行ってシリサイド形成を行う方法によって形成
されているために、平滑かつ均一な膜質を写しており、
ピンホール等を介してのシリコンのアルミニウム系=a
配線の移送が抑えられており、バリヤメタルとじて有効
である。、400〜600℃に限定したのはイオン注入
後にいきなり高温のアニールを行うと、シリサイドがは
みだして形成され自己整合性がなくなるからである。
(Function) In the present invention, the high melting point metal silicide interposed as a barrier metal between the aluminum-based electrode wiring and the silicon surface is formed by ion implantation through the high contact point metal film formed on the silicon surface. 1iA
Because it is formed by a method of mixing the interface with Il and then annealing at 400 to 600°C to form silicide, it has a smooth and uniform film quality.
Aluminum system of silicon via pinhole etc. = a
Transfer of wiring is suppressed, making it effective as a barrier metal. The reason why the temperature is limited to 400 to 600 DEG C. is that if high-temperature annealing is suddenly performed after ion implantation, silicide will be formed protruding and self-alignment will be lost.

また二度目のアニールを800℃以上の非還元性雰囲気
で行うのは平滑かつ均一な膜質を保ちながらシリサイド
の低抵抗化とイオン注入の損傷回復を同時に行うためで
ある。
The reason why the second annealing is performed in a non-reducing atmosphere at 800° C. or higher is to simultaneously lower the resistance of the silicide and recover damage caused by ion implantation while maintaining smooth and uniform film quality.

またAJ電電極線線中Siの含有量があまり多いと、シ
ンターしたときSiの析出物が形成され高抵抗になる恐
れがあるので3重量パーセント以下が望ましい。
Furthermore, if the Si content in the AJ electrode wire is too high, Si precipitates may be formed during sintering, resulting in high resistance, so it is preferably 3% by weight or less.

(実施例) 以下、図示の実施例により本発明の土延遣方法を説明す
る、第1図(a)〜(d)は本発明の製造工程の一例を
示した概略断面図である。
(Example) Hereinafter, the soil spreading method of the present invention will be explained with reference to the illustrated examples. FIGS. 1(a) to 1(d) are schematic cross-sectional views showing an example of the manufacturing process of the present invention.

まず、アクセプタ濃W 6.5 X 10” Cnt=
のP型単結晶Si基板11を用量し1通常のLOCO8
法により5oooAのフィールド酸化膜12を形成した
(第1図(a))。次に、薄いHF溶液にてシリサイド
層を形成すべきシリコン表面を清浄にした後、マグネト
ロンスパッタリングにより+Qさ4ooAのMo膜13
を形成し第1図(b)の構造とした、次に、Mo膜13
を通してSiイオン注入をイオンエネルギー80 ke
Vで5×101scIrL−2行イ、シリコン基板11
とMO膜13との界面を混合した後、ドーパントイオン
であるA8イオンをイオンエネルギー140keVでI
 X I Q” cm−”注入した後、H4カス中で5
50℃、20分間のアニールを行い、次に、ル0.系エ
ツチング液にてフィールド酸化膜12上の未反応なMo
膜をエツチングすることにより、第1I図(e)に示す
様にMo S i @膜14を選択的に形成し、かつM
o S i を膜14に自己整合力にAsドーピング層
15を形成した◎ 次に、CVD法により厚さ6500人の層間5int膜
16を堆積した後、Sin、膜の緻密化のため900℃
、20分間の熱処理を行い、その後、コンタクトホール
を開口後、1.2μmのAl−2%Siをスパッタリン
グにより形成し1通常のフォトエラ千ン〃゛法によりA
l−2%Si電極配線i7を形成し第1図(d)の構造
を得た。以上の本発明の手順に従って形成した kl−
2%S i/Mog 1 t/ n −p(接合深さ0
.16μm)電極(接合面at ; 300/jmX3
00μm。
First, acceptor density W 6.5 x 10” Cnt=
A P-type single crystal Si substrate 11 is dosed with 1 ordinary LOCO8.
A field oxide film 12 of 500A was formed by the method (FIG. 1(a)). Next, after cleaning the silicon surface on which a silicide layer is to be formed with a dilute HF solution, a Mo film 13 of +Q4ooA is formed by magnetron sputtering.
was formed to have the structure shown in FIG. 1(b). Next, a Mo film 13 was formed.
Si ion implantation through ion energy 80 ke
5×101scIrL-2 rows at V, silicon substrate 11
After mixing the interface between the MO film 13 and the MO film 13, A8 ions, which are dopant ions, are irradiated with I at an ion energy of 140 keV.
After injecting X I Q"cm-", 5
Annealing was carried out at 50°C for 20 minutes, and then the temperature was 0.5°C. Unreacted Mo on the field oxide film 12 is removed using an etching solution.
By etching the film, a Mo Si@ film 14 is selectively formed as shown in FIG. 1I(e), and M
An As doped layer 15 was formed on the Si film 14 with a self-aligning force. Next, a 5-inch interlayer film 16 with a thickness of 6,500 layers was deposited by the CVD method, and then Si was deposited at 900°C to make the film denser
, heat treatment was performed for 20 minutes, and then, after opening a contact hole, 1.2 μm of Al-2% Si was formed by sputtering, and A
A 1-2% Si electrode wiring i7 was formed to obtain the structure shown in FIG. 1(d). kl- formed according to the above procedure of the present invention
2%Si/Mog 1t/n-p (junction depth 0
.. 16μm) electrode (joint surface at; 300/jmX3
00μm.

Al −2(i S f/MoS t、コン〜タクト面
積;250ArnX40μm)の550℃、30分間の
シンター後の逆方向り・−り電流の逆方向電圧依存性を
第2図に示す(測定サンプル数5)。通常の動作電圧で
ある10V以下の逆方向電圧の領域では10−”A台の
小さいリーク電流である。このレベルのリーク電流は現
在シリコンデバイスの電極として使用されているAsイ
オン注入のみで形成されたn −p接合(接合深さ0.
25μm)の450℃のシンター後のリークレベルとほ
ぼ同様である。pn接合上に形成されたバリヤメタルの
バリヤ性の評価指標としては接合深さに対するリーク電
流の関係が挙げられるが、本発明の製造方法で形成した
場合lこは。
Figure 2 shows the reverse voltage dependence of reverse current after sintering Al-2 (iS f/MoS t, contact area: 250 Arn x 40 μm) at 550°C for 30 minutes (measurement sample Number 5). In the region of reverse voltage below 10V, which is the normal operating voltage, the leakage current is small on the order of 10-''A.Leakage current at this level can only be created by As ion implantation, which is currently used as electrodes in silicon devices. n-p junction (junction depth 0.
The leakage level is almost the same as that after sintering at 450° C. (25 μm). An evaluation index of the barrier properties of a barrier metal formed on a pn junction is the relationship between leakage current and junction depth, and this is true when formed by the manufacturing method of the present invention.

接合深さが0.13μmと浅い場合にも、接合深さが0
.26μmと深いものに対しても同様なリークレベルで
あった。第3図に第1図の実施例に従って形成した試料
の450℃、500℃、550℃で30分間のシンター
を行った場合の逆方向電圧5■における逆方向リーク電
流の値を示す。シンター@度の違いによる逆方向リーク
電流の差は1 pA程度である。
Even when the junction depth is as shallow as 0.13 μm, the junction depth is 0.
.. A similar leakage level was observed for a depth as deep as 26 μm. FIG. 3 shows the values of reverse leakage current at a reverse voltage of 5 .ANG. when sintering was performed for 30 minutes at 450.degree. C., 500.degree. C., and 550.degree. C. for the sample formed according to the embodiment shown in FIG. The difference in reverse leakage current due to the difference in sinter degree is about 1 pA.

(発明の効果) この様に、本発明の製造方法で形成したオーミック電極
は550℃までのシンターに対する耐熱性を持つことが
わかる。更に、本発明の製造方法lこよろオーミック電
極の接合深さはMo S i z膜の0.1μmの膜厚
分を含んで0.15μm8度と非常に浅いにかかわらず
550℃のシンターの耐熱性を有しており、サブミクロ
ンMO8FETで代表される微細半導体素子における′
rt極に有用である。特に、アルミニウム系金属配線の
サブミクロン寸法の加工に成子ビームやX線露光等を用
いた場合にMO8界面に導入される損傷を十分に回復さ
せうる550℃の高温シンターを本発明の製造方法によ
る電極Iこ実施することができる〇 前記実施例においてはAI!注入によるn−p接合の場
合を示したが、B注入によるp−n接合の場合も同様に
卓効があった。更に、ドーパントイオン注入を行わない
でSi注大のみによってショットキー電極を形成した場
合にも550℃のシンター耐熱性が確保された。才だ、
実施例では?vIc)Si、膜をバリヤメタルとして用
いた場合を示したが、WSi2 、 Ta5ilの場合
も同様に卓効があった。また前記実施例では単結晶シリ
コンの場合を述べたが多結晶シリコンの場合も同様であ
る。たとえばMosトラレジスタ24のゲート電極コン
タクトに用いれば良好なつまり低いコンタクト抵抗が維
持できた。
(Effects of the Invention) As described above, it can be seen that the ohmic electrode formed by the manufacturing method of the present invention has heat resistance against sintering up to 550°C. Furthermore, although the junction depth of the Koyoro ohmic electrode manufactured by the manufacturing method of the present invention is very shallow at 0.15 μm and 8 degrees, including the 0.1 μm thickness of the MoSiZ film, it has a sinter heat resistance of 550 degrees Celsius. ' in micro semiconductor devices represented by submicron MO8FETs
Useful for rt poles. In particular, the manufacturing method of the present invention can produce high-temperature sintering at 550°C, which can sufficiently recover damage introduced to the MO8 interface when a beam beam or X-ray exposure is used to process aluminum-based metal wiring to submicron dimensions. The electrode I can be implemented. In the above embodiment, AI! Although the case of an n-p junction formed by implantation is shown, the case of a p-n junction formed by B injection is equally effective. Furthermore, sinter heat resistance of 550° C. was ensured even when the Schottky electrode was formed only by Si pouring without dopant ion implantation. He's talented.
In the example? vIc) Although the case where a Si film was used as the barrier metal was shown, the cases of WSi2 and Ta5il were equally effective. Further, in the above embodiment, the case of single crystal silicon was described, but the same applies to the case of polycrystal silicon. For example, when used for the gate electrode contact of the Mos transistor resistor 24, good, ie, low contact resistance could be maintained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(d)は本発明の実施例を示す[所面図
。 図中11はP型Si基板、12フイールド酸化1摸、1
3はMo膜、14はMo S t t 膜、15はドー
ピング層、16は層間S iO,膜、17はAl−2φ
Si’α極配線を示す。第2図は本方法lこよって形成
したAl−2%SしMoSi、/n−P接合の550℃
、30分間のシンター後の逆方向特性図。第3図は同上
の450℃、500℃、550℃の逆方同室EE5Vに
おけるリークのシンター温If依存性を示す図。 第 1 (2) 第2図 AL−2’105J105J?/n”−F#合の550
′C230分間のシシター膣の在方陶詩小生逆力間V、
万(V゛〕
FIGS. 1(a) to 1(d) show an embodiment of the present invention. In the figure, 11 is a P-type Si substrate, 12 is a field oxidation sample, 1
3 is a Mo film, 14 is a Mo S t t film, 15 is a doping layer, 16 is an interlayer SiO film, 17 is an Al-2φ
The Si'α pole wiring is shown. Figure 2 shows the Al-2%S, MoSi,/n-P junction formed by this method at 550°C.
, Reverse characteristic diagram after 30 minutes of sintering. FIG. 3 is a diagram showing the dependence of leakage on the sinter temperature If in the opposite room EE5V at 450° C., 500° C., and 550° C. as above. 1st (2) Figure 2 AL-2'105J105J? /n”-F# 550
'C 230 minutes of Shishita vagina's existence, poetry, and Gyakurikima V,
Ten thousand (V゛)

Claims (1)

【特許請求の範囲】[Claims]  電極を形成すべき単結晶シリコン表面又は多結晶シリ
コン表面に高融点金属を堆積する工程と、イオン注入を
行って該高融点金属と前記シリコン表面との界面を混合
させ、400〜600℃の熱処理を行ない、その後、反
応せずに残った高融点金属をエッチング除去し、前記高
融点金属のシリサイド層を前記電極を形成すべきシリコ
ン表面に選択的に形成する工程と、800℃以上の温度
で非還元性雰囲気で熱処理を行う工程と、前記シリサイ
ド層の表面にSiを含むAl電極配線を接触させて形成
する工程とを含むことを特徴とする電子デバイスの電極
の形成方法。
A step of depositing a high melting point metal on the single crystal silicon surface or polycrystalline silicon surface on which an electrode is to be formed, ion implantation to mix the high melting point metal and the silicon surface, and heat treatment at 400 to 600°C. Thereafter, the high melting point metal remaining without reaction is removed by etching, and a silicide layer of the high melting point metal is selectively formed on the silicon surface where the electrode is to be formed. A method for forming an electrode for an electronic device, comprising the steps of performing heat treatment in a non-reducing atmosphere and forming an Al electrode wiring containing Si in contact with the surface of the silicide layer.
JP14620685A 1985-07-02 1985-07-02 Forming method for electrode of electronic device Pending JPS625635A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14620685A JPS625635A (en) 1985-07-02 1985-07-02 Forming method for electrode of electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14620685A JPS625635A (en) 1985-07-02 1985-07-02 Forming method for electrode of electronic device

Publications (1)

Publication Number Publication Date
JPS625635A true JPS625635A (en) 1987-01-12

Family

ID=15402516

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14620685A Pending JPS625635A (en) 1985-07-02 1985-07-02 Forming method for electrode of electronic device

Country Status (1)

Country Link
JP (1) JPS625635A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0542919A (en) * 1991-08-09 1993-02-23 Gunze Ltd Rotary device of cylinder
JP2017118104A (en) * 2015-12-01 2017-06-29 インフィネオン テクノロジーズ アーゲーInfineon Technologies Ag Forming contact layer on semiconductor body

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0542919A (en) * 1991-08-09 1993-02-23 Gunze Ltd Rotary device of cylinder
JP2017118104A (en) * 2015-12-01 2017-06-29 インフィネオン テクノロジーズ アーゲーInfineon Technologies Ag Forming contact layer on semiconductor body
US10002930B2 (en) 2015-12-01 2018-06-19 Infineon Technologies Ag Forming a contact layer on a semiconductor body

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