JPS6255938A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6255938A
JPS6255938A JP19632585A JP19632585A JPS6255938A JP S6255938 A JPS6255938 A JP S6255938A JP 19632585 A JP19632585 A JP 19632585A JP 19632585 A JP19632585 A JP 19632585A JP S6255938 A JPS6255938 A JP S6255938A
Authority
JP
Japan
Prior art keywords
film
resist
insulating film
etching
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19632585A
Other languages
Japanese (ja)
Inventor
Hiroyuki Okada
裕幸 岡田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP19632585A priority Critical patent/JPS6255938A/en
Publication of JPS6255938A publication Critical patent/JPS6255938A/en
Pending legal-status Critical Current

Links

Landscapes

  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To improve the coating property of an electrode metal and thereby to prevent the stage cut and contact fault thereof, by giving a gentle taper to the upper and lower ends of an opening of an insulating film. CONSTITUTION:A resist mask 3 is provided on an SiO2 film 2 formed on an Si substrate 1, and etching is conducted by an HF solution to form eaves 4 on the film 2 at the edge of an opening. A resist 5 is subjected to rotary coating to pack a space formed by the eaves 4. When the film 2 is etched by a dry etching method, a gentle taper 6 is formed on the lower side wall of the film 2. The resist 3 is removed, the whole surface of the substrate 1 is etched by an HF solution to remove the resist 5 remaining in the space formed by the eaves 4, and thereby a taper 8 is formed at the upper edge of the opening 7. According to this constitution, a gentle taper can be formed with excellent reproducibility and mass-productivity, and thus the stage cut and contact fault of a wiring metal are prevented.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置の製造方法に関するものである。[Detailed description of the invention] Industrial applications The present invention relates to a method of manufacturing a semiconductor device.

従来の技術 絶縁膜に電極窓を開口する方法として、比較的大きいパ
ターンについては弗酸系の溶液を用いたウェット法が用
いられ、微細パターンについてはドライエツチング法が
用いられている。しかしながら、パターンの微細化が進
むと、ドライエツチング法で基板に垂直に窓を開口する
と、電極金属が開口部の上下端で被覆性が悪くなり、電
極配線の段切れやコンタクト不良が生じる。このため、
電極窓の側壁は基板に対してテーパーを持つ必要があり
ドライエツチングの条件を変えたり、多段ステップのエ
ツチング条件にしたり、又選択エッチのマスクであるレ
ジストの縮退を用いてテーパーを形成する方法が試みら
れている。
BACKGROUND ART As a method for opening electrode windows in an insulating film, a wet method using a hydrofluoric acid solution is used for relatively large patterns, and a dry etching method is used for fine patterns. However, as patterns become finer, if a window is opened perpendicularly to the substrate using a dry etching method, the coverage of the electrode metal at the upper and lower ends of the opening becomes poor, resulting in disconnections in the electrode wiring and poor contact. For this reason,
The side wall of the electrode window needs to have a taper relative to the substrate, so there are methods to form a taper by changing the dry etching conditions, using multi-step etching conditions, or by using the degeneracy of the resist, which is a mask for selective etching. is being attempted.

発明が解決しようとする問題点 このように絶縁膜の開口窓の形成には電極金属の被覆性
を良くするためにテーパーを形成する必要があるが、ド
ライエツチング条件の多段ステップ化やレジストマスク
端の縮退によるテーパーエツチングは再現性が悪く、量
産性に乏しいという問題がある。
Problems to be Solved by the Invention As described above, when forming an opening window in an insulating film, it is necessary to form a taper in order to improve the coverage of the electrode metal. Taper etching due to degeneracy has problems in that reproducibility is poor and mass production is poor.

本発明はこのような問題点を解決するもので、再現性良
く、又斌産性良く開口窓の上下端にデーパ−を形成でき
るようにすることを目的とするものである。
The present invention is intended to solve these problems, and aims to form tapers at the upper and lower ends of an opening window with good reproducibility and good productivity.

問題点を解決するための手段 この問題点を解決するために本発明は、表面に絶縁膜を
有する半導体基板の前記絶縁膜上にレジスト3間を付着
してこのレジスト膜を開(コする工程と、前記レジスト
膜の開口部内に位置する絶縁膜を等方性二ノチング法に
よって浅くエツチングする工程と、この絶縁膜のエツチ
ング部と前記レジスト膜の面上にスピンコート法によっ
てエツチング形状補正用膜を形成する工程と、前記エツ
チング形状補正用膜とその下の絶縁膜とをドライエツチ
ング法によってエツチングする工程とを備えたものであ
る。
Means for Solving the Problem In order to solve this problem, the present invention provides a step of attaching a resist 3 on the insulating film of a semiconductor substrate having an insulating film on the surface and opening the resist film. a step of shallowly etching an insulating film located within the opening of the resist film by an isotropic di-notching method; and a step of etching a film for etching shape correction by a spin coating method on the etched portion of the insulating film and the surface of the resist film. and a step of etching the etched shape correction film and the underlying insulating film by dry etching.

作用 この構成により、絶縁膜開口窓の上下端になだらかなテ
ーパー形成され、これによって電極金属の被覆性が良く
なり、段切れや基板と電極金属の間のコンタクト不良が
なくなる。
Effect: With this configuration, a gentle taper is formed at the upper and lower ends of the insulating film opening window, which improves the coverage of the electrode metal and eliminates step breakage and poor contact between the substrate and the electrode metal.

実施例 以下、本発明の一実施例について、図面に基づいて説明
する。
EXAMPLE Hereinafter, an example of the present invention will be described based on the drawings.

先ず、第1図において基板1上の二酸化ケイ素から成る
絶縁膜2に窓を開口するため、レジスト3にパターンを
形成する。次に第2図において弗酸系の溶液で約100
0人エツチングを行ない、レジスト3のパターンの端部
において絶縁膜2にアンダーカット部4を生ぜしぬる。
First, in FIG. 1, a pattern is formed in the resist 3 in order to open a window in the insulating film 2 made of silicon dioxide on the substrate 1. Next, in Figure 2, approximately 100
Zero etching is performed to create an undercut portion 4 in the insulating film 2 at the end of the pattern of the resist 3.

次に第3図においてスピンコート法により約1000〜
1500人塗布膜5を形成する。このとき、スピンコー
ト法の回転時の遠心力と塗布膜5とレジスト3間の付着
力とにより壁面部に厚く、平坦部に薄く塗布膜5が塗布
され、前記アンダーカット部4が塗布1115で埋めら
れる。次に第4図においてドライエツチング法を用いて
絶縁膜2をエッチオフする。その場合、絶縁膜2下部の
サイドウオール部になだらかなテーパー6が形成される
。次に第5図においてレジスト3を除去し、基板1全面
を弗酸系の溶液でエツチングして、アンダーカット部4
に残っている塗布膜5をエッチオフする。これにより第
6図に示すようになり、電極開口窓7の側壁の上下端に
なだらかなテーパー6.8を備えることになる。
Next, in Fig. 3, approximately 1000~
A coating film 5 was formed by 1,500 people. At this time, the centrifugal force during rotation of the spin coating method and the adhesive force between the coating film 5 and the resist 3 cause the coating film 5 to be applied thickly to the wall surface portion and thinly to the flat portion, and the undercut portion 4 is coated with the coating 1115. Buried. Next, in FIG. 4, the insulating film 2 is etched off using a dry etching method. In that case, a gentle taper 6 is formed in the sidewall portion below the insulating film 2. Next, as shown in FIG. 5, the resist 3 is removed, and the entire surface of the substrate 1 is etched with a hydrofluoric acid solution.
The remaining coating film 5 is etched off. As a result, as shown in FIG. 6, the upper and lower ends of the side walls of the electrode opening window 7 are provided with gentle tapers 6.8.

尚、前記塗布膜5としてはスピニオングラス(SOG)
が用いられるが、その代りにドライエツチング可能なレ
ジストを用いても良い。
Incidentally, the coating film 5 is made of spinion glass (SOG).
is used, but a dry-etchable resist may be used instead.

発明の効果 以上のように本発明によれば、電極開口窓の側壁の上下
端になだらかなテーパーを再現性、量産性ともに良く形
成できるため、配線金属の段切れや基板とのコンタクト
不良が大幅に低減される。
Effects of the Invention As described above, according to the present invention, a gentle taper can be formed at the upper and lower ends of the side wall of the electrode opening window with good reproducibility and mass production, thereby significantly reducing the occurrence of disconnections in the wiring metal and poor contact with the substrate. reduced to

又、開口窓の面積もレジストパターンに忠実に転写され
るため、マスクの補正の必要がない。
Furthermore, since the area of the opening window is faithfully transferred to the resist pattern, there is no need for mask correction.

【図面の簡単な説明】[Brief explanation of drawings]

第1図〜第6図は本発明の一実施例を示す工程断面図で
ある。 1・・・基板、2・・・絶縁膜、3・・・レジスト、4
・・・アンダーカット部、5・・・塗布膜、6・・・テ
ーパー、7・・・電極開口窓、8・・・テーパー 代理人   森  本  義  弘 第1図 第2図 第3図 ケ 第4図 〕 第5図 第6図
1 to 6 are process sectional views showing one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Substrate, 2...Insulating film, 3...Resist, 4
... Undercut portion, 5... Coating film, 6... Taper, 7... Electrode opening window, 8... Taper agent Yoshihiro Morimoto Figure 1 Figure 2 Figure 3 Figure 3 Figure 4] Figure 5 Figure 6

Claims (1)

【特許請求の範囲】 1、表面に絶縁膜を有する半導体基板の前記絶縁膜上に
レジスト膜を付着してこのレジスト膜を開口する工程と
、前記レジスト膜の開口部内に位置する絶縁膜を等方性
エッチング法によって浅くエッチングする工程と、この
絶縁膜のエッチング部と前記レジスト膜の面上にスピン
コート法によってエッチング形状補正用膜を形成する工
程と、前記エッチング形状補正用膜とその下の絶縁膜と
をドライエッチング法によってエッチングする工程とを
備えた半導体装置の製造方法。 2、エッチング形状補正用膜をスピニオングラスで形成
した特許請求の範囲第1項記載の半導体装置の製造方法
。 3、エッチング形状補正用膜をレジストで形成した特許
請求の範囲第1項記載の半導体装置の製造方法。
[Claims] 1. A step of depositing a resist film on the insulating film of a semiconductor substrate having an insulating film on the surface and opening the resist film, and forming an insulating film located in the opening of the resist film, etc. a step of shallowly etching by a directional etching method; a step of forming an etching shape correction film on the etched portion of the insulating film and the surface of the resist film by a spin coating method; A method for manufacturing a semiconductor device, comprising a step of etching an insulating film using a dry etching method. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the etching shape correction film is formed of spinion glass. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the etching shape correction film is formed of a resist.
JP19632585A 1985-09-05 1985-09-05 Manufacture of semiconductor device Pending JPS6255938A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19632585A JPS6255938A (en) 1985-09-05 1985-09-05 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19632585A JPS6255938A (en) 1985-09-05 1985-09-05 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6255938A true JPS6255938A (en) 1987-03-11

Family

ID=16355940

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19632585A Pending JPS6255938A (en) 1985-09-05 1985-09-05 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6255938A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06349789A (en) * 1993-03-02 1994-12-22 Hyundai Electron Ind Co Ltd Method for formation of contact hole in high-integration semiconductor device
JP2002176962A (en) * 2000-12-12 2002-06-25 Fukushima Industries Corp Apparatus for washing food material

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06349789A (en) * 1993-03-02 1994-12-22 Hyundai Electron Ind Co Ltd Method for formation of contact hole in high-integration semiconductor device
JP2002176962A (en) * 2000-12-12 2002-06-25 Fukushima Industries Corp Apparatus for washing food material

Similar Documents

Publication Publication Date Title
JPS6376330A (en) Manufacture of semiconductor device
JPH0135495B2 (en)
US5935876A (en) Via structure using a composite dielectric layer
JPS6237936A (en) Formation of openings simultaneously in layers different in thickness
JPS6255938A (en) Manufacture of semiconductor device
JPS6255936A (en) Manufacture of semiconductor device
JPS5840338B2 (en) Manufacturing method for semiconductor devices
JPH06104206A (en) Method and apparatus for manufacturing semiconductor device
JPH0745551A (en) Forming method of contact hole
KR100537195B1 (en) Capacitor Manufacturing Method of Semiconductor Memory Device
JPH0349228A (en) Manufacture of semiconductor integrated circuit
JPH0220043A (en) Manufacture of semiconductor device
JPH02292824A (en) Manufacture of semiconductor device
JPH04157730A (en) Manufacture of semiconductor device
JPS62274715A (en) Manufacture of semiconductor device
JPS62140433A (en) Manufacture of semiconductor device
JPH047095B2 (en)
JPS62172721A (en) Formation of contact hole
JPS6386451A (en) Semiconductor device
JPS63117468A (en) Manufacture of semiconductor device
JPS60153131A (en) Manufacture of semiconductor element
JPH0350826A (en) Manufacture of semiconductor device
JPS61184828A (en) Manufacture of semiconductor device
JPS6362352A (en) Manufacture of semiconductor device
JPS6246527A (en) Manufacture of semiconductor device