JPS625502B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention receives multiplexed information signals such as character information and graphic information that are superimposed and transmitted during the vertical retrace period of a television signal, and stores the pattern data signals. An object of the present invention is to provide a multiplexed information receiving device that displays multiplexed information on a TV, etc., and that can make it easy to understand what kind of information is being transmitted in addition to information on a specific program that one wishes to receive. do.

In order to achieve such an object, the present invention provides a program selection circuit in a device that receives a multiplexed information signal such as character information superimposed during a vertical retrace period of a television signal and displays the multiplexed information. a first storage means and a display means for selecting and storing only the multiplexed information signal of a program specified in advance by the program and displaying only the information of the program; The present invention is characterized by comprising second storage means and display means for storing and sequentially displaying multiplexed information signals transmitted by signals, regardless of which program they are received, each time they are received.

EMBODIMENT OF THE INVENTION Hereinafter, the present invention will be described in detail with reference to the drawings showing one embodiment thereof.

First, Fig. 1 is a block diagram showing the general configuration of the entire system. 1 is a video detection circuit of a television receiver, and 2 is a circuit for transmitting multiplexed information such as characters and graphics.
A video signal is obtained in which a value information signal is superimposed on a horizontal scanning period during a vertical retrace period. 2, since the transmitted binary information signal is subject to waveform distortion due to the frequency characteristics of the transmission system and various distortions, the received signal is sliced at an appropriate level, etc.
This is a waveform shaping circuit that shapes a predetermined binary signal waveform as shown in the figure. 3 is a sync separation circuit, 4 is a color subcarrier (SC) regeneration circuit, and 5 is a sync separation circuit 3.
vertical sync pulse and horizontal sync pulse from 2
To extract the signal during the period when the value information signal is superimposed (for example, the 20th H during the vertical retrace period)
A circuit that generates a 1H width gate pulse, 6 is sc
Various clock pulses such as a sampling clock for sampling the received binary information signal based on the color subcarrier etc. from the reproduction circuit 4 and a memory clock for writing and reading the received signal into the main memory. This is a circuit that generates

7 is a sampling circuit, and 2 is a waveform shaping circuit 2.
The received binary information signal, which has been shaped into a value waveform, is sampled using a sampling clock, and then converted into serial and parallel signals, and is output as an 8-bit parallel output. Reference numeral 8 denotes a detection circuit that detects a framing code (FC) signal of a specific code in the binary information signal from the output signal of the sampling circuit 7, and uses the detection output to control the clock generation circuit 6 to generate a clock. control the phase of That is, in the clock generation circuit 6, the FC
During the period until the signal is detected, the clock run in (CRI) signal placed at the beginning of the received binary information signal is used to generate a sampling clock synchronized with it, and the FC signal is detected. After that, the color subcarrier from the sc reproduction circuit 4 is multiplied and divided, and the frequency division phase is controlled by the FC detection output to generate 8/5sc that is synchronized with the color subcarrier and the FC detection output. Generates clocks for reception and main memory.

Reference numeral 9 denotes a control circuit for controlling the writing and reading of pattern data in the binary information signal into the two sets of main memories 10 and 11, and this part is realized using processing calculation means such as a microcomputer.

In this device, first and second main memories 10 and 11 are used as main memories for storing pattern data in received binary information signals and displaying images of characters and figures as multiplexed information. 13 and 14 are first and second CRTs for display, respectively. Here, the multiplexed information to be received and displayed is character information or graphic information that consists of 248-bit picture elements in the horizontal direction and 204 horizontal scanning lines in the vertical direction. Then, each of the main memories 10 and 11 has a storage capacity of at least 50592 (=248×204) bits or more. Here, since the sampling circuit 7 is of an 8-bit parallel output type, the main memories 10 and 11 are
It is recommended to use eight 8K-bit memories in parallel, and perform parallel-to-serial conversion before outputting when reading.

On the other hand, numeral 12 is a program selection circuit that specifies what you wish to receive from the types of multiplexed information (hereinafter referred to as programs) such as multiple types of character information and graphic information that are multiplexed and transmitted in the television broadcast signal. ,
When a program is selected by a viewer, an 8-bit code signal representing the program is generated, and this is applied to the W/R control circuit 9, which controls only the pattern data of the binary information signal of the selected program. memory 1
This command instructs the data to be written to and stored.

These 1 to 14 are the second main memory 11 and
Except for the CRT14, it operates in the same way as a normal teletext receiver.

FIG. 2 shows an aspect of the binary information signal multiplexed into the television signal received in the present invention. As shown in A, this binary information signal is superimposed on any horizontal scanning period during the vertical retrace period of the television signal, here the 20th H, and depending on the signal content, B ,C,D
There are three types such as. B is PCP (Page
This control packet signal is sent to the first field of each multiplexed information prior to transmitting the binary information signal for one page. C is CCP
(Color Control Packet) signal, which is sent to the first field of one line of characters and figures to be transmitted and displayed. However, this CCP signal is omitted when an information image of characters or figures is displayed only in black and white. Furthermore, D is PDP (Pattern Data
This is a 248-bit pattern data signal for one line in the horizontal direction of an information image of characters and figures to be transmitted and displayed. this
In the PDP signal, the data identification signals DI ₁ and DI ₂ are inserted into the control signal part, 4 bits each, 8 bits in total (excluding the parity bit).
indicates which line from the top of one page of information pictorial the pattern data signal is on.

The transmission mode of these signals is determined by the Radio Technology Council No. 4.
This is similar to what was written in the subcommittee's report for 1978.

Now, when a multiplexed information program that the program selection circuit 12 in FIG. When the program number signals PR ₁ and PR ₂ in The CCP signal and PDP signal for one page of the specified program are selectively received, and the pattern data for that one page is sequentially written and stored in the first main memory 10. After that, this first main memory 1
The pattern data stored in 0 is read out in synchronization with the raster scanning of the CRT 13 and supplied to the CRT 13, and the multiplexed information image of one page of the specified program is displayed on the screen in a static state for a certain period of time. do. When the display of that page is finished and a binary information signal containing pattern data for a new page is transmitted in the same designated program, the program number signals PR ₁ and PR ₂ will match in this case as well, so that pattern will be transmitted. The data is stored in the main memory 10 and the image of the new page is displayed on the CRT 13. In this way, each time a new binary information signal of a designated program is transmitted, its pattern data is stored in the main memory 10 and displayed for a fixed period of time.

In the above explanation, one PCP signal is followed by a CCP signal for one page of that program.
Although the above description assumes that only PDP signals are transmitted continuously, multiplexed information signals of other programs or pages may be partially interrupted and transmitted in the middle of these signals. In that case, the interrupt signal has a second
A specific interrupt code signal is attached to the service identification/interrupt identification signal SI/IN part of each signal in Figures B, C, and D, so by detecting this, it is possible to determine the interrupt signal. What is necessary is to detect whether or not it exists.

Next, the second main memory 11, which is a feature of this device,
The following describes the CRT 14 and its peripheral circuits.

Unlike the first main memory 10 described above, this second main memory 11 can transmit multiplexed information signals of any program, regardless of the selection of the program desired to be received in the program selection circuit 12. All received pattern data are sequentially written and stored, and all images of the multiplexed information transmitted are transferred to the second CRT 14.
This is what is displayed on the screen.

First, in FIG. 3, the memory element 11M of the second main memory 11 is configured as eight 8K-bit memory chips connected in parallel as described above. Reference numeral 11B is a buffer amplifier that converts pattern data from parallel to serial at the time of reading. Further, 9D is a latch circuit that latches data identification signals DI ₁ and DI ₂ , which are line number designation signals in the received PDP signal, as line address signals during writing, and 9L is a latch circuit that is reset by a vertical synchronization pulse. A line counter that counts horizontal synchronization signals and generates a line address signal during reading; 9V is a vertical address selector that selectively applies these two types of line address signals to the vertical address terminal of the memory element 11M; 9H is for reception. This horizontal address counter counts clock pulses (for writing) and clock pulses for display (reading) and applies a horizontal address signal to the horizontal address terminal of the memory element 11M. 9I is service identification/interrupt identification signal SI/IN
This is an SI/IN detection circuit that determines whether the binary information signal is an interrupt signal or not. Also,
9C is controlled by horizontal pulse, CRT1
A period for displaying an image of multiplexing information on the screen of 4.
For example, for display (reading) of 248 bits per line in 45 μsec at the center during the horizontal scanning period.
It is a gated oscillator that generates clock pulses.

Now, in such a configuration, if a binary information signal of any arbitrary program transmitted in the 20th H of an arbitrary field is received, and if the signal is a PDP signal, first the SI/IN
The detection circuit 9I detects whether or not it is an interrupt signal, and if it is not an interrupt signal, a high level detection output is generated, and the output of the NAND gate 9G to which the 20th gate pulse is applied is set to a low level. The memory element 11M is controlled to be in the write state.

Then the line number signal in that PDP signal
DI ₁ and DI ₂ are latched by the latch circuit 9D, and the output thereof is taken out by the vertical address selector 9V, which is switched to the input A side by the 20th H gate pulse, and is applied to the memory element 11 as a line address signal. Therefore, the position of that line becomes writable.

On the other hand, at this time, the write clock pulse from the clock generation circuit 6 is applied to the AND gate 91 which is made conductive by the 20th H gate pulse.
It is added to the horizontal address counter 9H from the OR gate 93 via the OR gate 93. This clock pulse is PDP
It is generated in synchronization with each bit in the pattern data signal portion of the signal, and the address counter 9H counts this and changes the address by "1" every 8th bit. Therefore,
A horizontal address signal that changes every 8th bit of the received pattern data signal is applied from the horizontal address counter 9H to the horizontal address terminal of the memory element 11M, and the memory location becomes sequentially in a writable state.

The pattern data signal in the received PDP signal is converted into a parallel signal every 8 bits from the sampling circuit 7 and is applied to the input/output terminal of the memory element 11M via the bus line. 11M has the line number signal mentioned above.
Pattern data signals are sequentially written to the memory locations of the lines designated by DI ₁ and DI ₂ .

Thus, each time a new PDP signal is transmitted and received, all pattern data signals are sequentially written and stored in the memory element 11M, regardless of the program, unless it is an interrupt signal.

The horizontal address counter 9H is automatically self-reset when a horizontal address signal corresponding to one line of the pattern data signal is applied to the memory element 11M. The operation will be more reliable if it is always reset (cleared) at the beginning of every H using a pulse or the like.

Next, the pattern data stored in the memory element 11M each time it is received in this way is stored in the second
It is read out in synchronization with raster scanning of the screen of the CRT 14 and displayed on the CRT 14.

That is, here, it is assumed that an image of one page of multiplexed information consisting of 204 lines is displayed on the screen of the CRT 14 from the 39th line to the 242nd line counting from the vertical retrace line. Therefore, the line counter 9L counts the horizontal synchronizing pulses while resetting each field with the vertical pulses, and counts the horizontal synchronizing pulses to "1" when the 39th line on the screen is horizontally scanned.
Therefore, a setting is made so that a vertical address signal of "204" is generated during horizontal scanning of the 242nd line.
The vertical address selector 9V is switched to the B side during the other periods except the 20th H, which is the reception pattern data signal write period mentioned above, and the vertical address signal from the line counter 9L is applied to the vertical address of the memory element 11M. Applied to address terminals.

On the other hand, as mentioned above, from the gated oscillator 9C, one line of 248
An AND gate 92 is generated with a bit-by-bit display (readout) clock pulse, and is made conductive by inverting the gate pulse with an inverter 94 during a period other than the 20th H mentioned above.
The horizontal address counter 9H receives this clock pulse via the gate 93 and applies a horizontal address signal that changes every 8th bit of the clock pulse to the memory element 11M to control the horizontal address.

In this way, pattern data signals are sequentially read out one line at a time from the memory element 11M in 8-bit parallel output using the horizontal and vertical addresses synchronized with the scanning of the screen of the CRT 14. The signal is then parallel-serial converted using a clock pulse in the buffer amplifier 11B, and is applied to the CRT 14 as a video signal for display, thereby displaying an image of the multiplexed information stored in the memory element 11M.

In this way, the second main memory 11 stores the image pattern data of the multiplexed information that has been multiplexed and transmitted on the television signal, regardless of the designation of the program desired to be received from the program selection circuit 12. You can accumulate all of them one after another each time they are sent,
All the information images being transmitted are sent to the CRT one after another.
14 can be displayed. Therefore, while the viewer reads the specified multiplexing information image on the display on the first CRT 13, the viewer can check what other multiplexing information is being sent on the second CRT 13.
This can be known by looking at the display on the screen of the CRT 14, and when other desired information is being transmitted, the display on the first CRT 13 can be switched to it, and all multiplexed information throughout the entire It can be monitored in its entirety.

Note that FIG. 4 shows a detailed comparison of the control parts of the first main memory 10 and the second main memory 11, and the control circuit on the second main memory 11 side is the same as that shown in FIG. However, in the first main memory 10, the memory elements 10 of the main memory 10 are similarly controlled by the vertical and horizontal address signals from the vertical address selector 9V and the horizontal address counter 9H.
While controlling the address of M, this memory element 1
0M is a program code signal PR ₁ ,
The comparison circuit 9C compares PR ₂ with the code signal of the desired program specified by the program designation circuit 12, and when the two match, that is, the binary information signal of the desired program is transmitted. By controlling the write state by generating an output from the NAND gate 9G' only when the program is received, only the pattern data of the binary information signal of the program desired to be received is stored in the memory element. 10M
I am trying to write and accumulate the data. In this way, only the images of the multiplexed information of the program desired to be received can be stored in the main memory 10, and only the images of that program can be displayed on the CRT 13. Note that 7B is a buffer amplifier for distributing and supplying the received binary information signal from the sampling circuit 7 to the main memories 10 and 11.

Further, in the above explanation, only the storage and display of pattern data has been described, but it goes without saying that color code signals can be processed in exactly the same way to display a color image.

Furthermore, in the embodiment described above, the interrupt signal among the binary information signals is not stored in the second main memory 11, but this may also be stored.

As detailed above, according to the present invention, the first memory and display means such as CRT receive and display the multiplexed information of a pre-specified program, while the second memory and display means such as CRT The display means can display transmitted multiplexed information in sequence each time it is received, regardless of the designated program, so it is possible to constantly monitor what kind of multiplexed information is being transmitted by programs other than the designated program. This makes it easy to change the designated program and prevent information from being overlooked.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a multiplexed information receiving device according to an embodiment of the present invention, FIG. 2 is a waveform diagram of an example of a multiplexed information signal received by the same device, and FIGS. 3 and 4 are diagrams of the same device. It is a specific circuit diagram of the main part. 1... Video detection circuit, 2... Waveform shaping circuit, 3
... Synchronization separation circuit, 4 ... Color subcarrier regeneration circuit,
5... Gate pulse generation circuit, 6... Clock generation circuit, 7... Sampling circuit, 8... FC detection circuit, 9... W/R control circuit, 10... First main memory, 11... 2 main memory, 12... program selection circuit, 13... first CRT, 14... second CRT.

Claims (1)

[Claims] 1. In a device that receives a multiplexed information signal such as character information superimposed during the vertical blanking period of a television signal and displays the multiplexed information, the multiplexed information signal of a program specified in advance by a program selection circuit. a first storage means and a display means for selectively storing and displaying only the information of the selected program; Multiplexed information reception characterized by comprising second storage means and display means for storing information on all programs received each time they are received and sequentially displaying information on all transmitted programs. Device.