JPS6254352A - System test controller - Google Patents

Abstract

PURPOSE:To attain a system test without using an I/O control device and an I/O device by applying a command equivalent to a real I/O instruction to an I/O control simulator through a CPU on the basis of a program stored in an MMU. CONSTITUTION:Testing data are formed in the MMU 3 to prepare the system test. Then, the command equivalent to the real I/O instruction is applied to the I/O simulator device 17 through the CPU 2 on the basis of the program stored in the MMU 3 to generate the timing or the like with a body 1 simulatively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a system test control device, and particularly to a system test device for testing a channel control device system in a computer system.

[Conventional technology]

This Yuzu device was shown in Figure 4. Fourth
The figure is a block diagram showing the configuration of a computer system showing a conventional computer testing device. A central processing unit (hereinafter referred to as CPU) that executes programs, etc. (3+ is a main memory that stores programs and data (hereinafter referred to as ■)
, (41 is the MMU +31K already stored test program (hereinafter referred to as the program), +51 is the channel control device which is connected to the input/output control device! (25) (hereinafter the input/output control device is referred to as the IOC). (6) is the system control console for operating the program, (7) is the external memory 1, 01, +81, where the program is stored.
+91 and (10) are channel control devices to be tested, respectively (12a).

(12b), (13), (14), (15
) are each channel control device t i81 to (10) respectively.
IOC% (20a), (20b) connected to I
A magnetic tape device (2) connected to the OC (12a)
0c) is a magnetic tape device connected to IOC (12b), (22) is a terminal device connected to IOC (13), (23) is a line printer device connected to IOC (14), ( 24a), (24b) are IOC(1
5) is a magnetic disk device connected to. FIG. 5 is a flowchart showing the processing flow when performing a system test from the main body (1), and in the figure (30a
) to (30p) are each step.

Next, the operation of the conventional device will be explained. The main body (1) is ■l (31K stored programs (4) are CP
The operation is defined by sequential execution in U(2), but here, this operation is defined as the operation of the main body (1), and
The program (4) that performs the system test is on the external storage device f.
it +61 via cIOc (25), + Janel, via B113 device (5), MMLT +31
The explanation will be given assuming that it is stored within.

First, the program (4) for performing a system test performs necessary initialization (3Oa) for the program itself to operate, such as flags and tables. Furthermore, test data is generated in the +VMU 13) (30b), and preparations are made before performing a system test.

Next, in order to start the test, one device to be diagnosed is selected and an input/output command is activated for that device (30c).

Once the input/output interrupt is enabled (30d), if there is an input/output interrupt request, that interrupt is taken. The device to be diagnosed here directly refers to the valley channel control device 1.
8) to (10), and IOCs (12a), (12b), (13), and (1) connected to each channel control device.
4).

(15), and magnetic tape devices connected to these IOCs (20a), (20b), (20c),
Terminal device (22) Line printer device (23),
Input/output devices such as magnetic disk units (24a) and (24b) are shown, and indirectly include CPU +21, IU +31, etc. When input/output interrupts are enabled, if there is an interrupt request, the interrupt is immediately disabled (30g) to disable interrupts and perform interrupt processing.

In this interrupt processing, it is checked whether the interrupt information such as the status of the device that is generated when the interrupt occurs is correct or not.
Test whether the transferred data is correctly transferred to the MVLI [31] and whether the data is correctly transferred to the device (30h). Here, if these test results are correct, preparations are made for entering the next test (30j). Also, if an input/output interrupt is not requested in (30e), immediately disable this interrupt,
Start testing the next device. Also, at (30h), if the test result is incorrect, an error message is output to the system control console (6) via the main body (1). Next (3
Load the next device address after 0j) (30k)
. Next, check whether 5 minutes have passed since the start of the test (30tχ If within 5 minutes, proceed to (30n).
In step n), it is checked whether all the devices are in the I/O interrupt wait state, and if they are in the interrupt wait state, the CPU 111 enters a wait state and waits for an I/O interrupt (30p). If an interrupt occurs here, the process goes to (30g) again and the same interrupt processing is performed thereafter. Also, if more than 5 minutes have passed at (30t), move to the next diagnosis mode (3orn),
The test is performed again in the same procedure from (30a). The diagnostic mode (3orn) here means - For example, MM
U f3+ and the device to be diagnosed, such as a magnetic tape device (2
This refers to changing the number of transfer blocks in 0a), fc, and changing the test processing method depending on parameters.

As described above, the system is tested according to the flow shown in FIG.

FIG. 6 is a time chart showing the operating status of each device shown in FIG. When an input/output command is started for the device (20a), the magnetic tape device (20a) becomes busy as shown by code (33), and after a certain amount of time has passed, the operation of the device ends and the process starts as shown by code (34). It becomes ready as shown. That is, the shaded area indicates that the device is in operation. When the operation is completed, an input/output interrupt is generated. While the magnetic tape device (20a) is in operation, an input/output command is activated for the next device, the magnetic tape im(zob). Similarly, input/output commands are sequentially activated for other devices as shown in FIG. 6, for example. On the other hand, if the first device finishes its operation during the start-up process of this input/output command, an input/output interrupt is generated and preparations for the next test begin. In FIG. 6, the time other than the shaded area is the time during which the processing by program (4) is being performed, that is, the time during which the test schedule, test preparation, input/output interrupt processing, and interrupt information testing are being performed. As described above, the operation of each device including the channel control device [t and IOC] is tested.

[Problem that the invention seeks to solve]

In conventional system test control equipment that focuses on the main body, in addition to each input/output control device as mentioned above, input/output devices connected to it are required, and it takes up a lot of space to install these devices. Further, there is a problem in that the test efficiency is significantly reduced in cases where the IOC and each input/output device used for testing are broken down.

This invention was made to solve such problems, and is a system test control device that can test the channel control system built into the main body without reducing test efficiency due to failure of the input/output control device. The purpose is to obtain.

[Means for solving problems]

A system test control device according to the present invention is configured to perform a system test using an input/output control simulator device as a replacement for an IOC and an input/output device.

[Operation] In this invention, a program stored in the MMU gives commands equivalent to actual input/output commands to the input/output control simulator device via the CPU, and simulates timing etc. with the main unit. By generating this signal, the same operation as before can be performed even without the 10C1 input/output device, and the purpose of the system test can be achieved.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention,
The same symbols as in Figure 4 indicate the same or equivalent parts, (17)
is an input/output control simulator device that serves as a diagnostic device, (21
a) to (21d) are simulator addresses. or,
FIG. 2 is a flowchart showing the processing flow when performing a system test from the main body (1) according to the present invention. In FIG. 2, the same reference numerals as in FIG. 5 indicate the same or equivalent steps (31c).

(31j), (31k), and (31n) are (30c) in FIG. 5, respectively.

These steps correspond to (30j), (30k), and (30n).

Next, the operation of the apparatus of this invention will be explained.

Similar to the conventional device description, the main body (1) has its MMU+
Program (4) stored in CPUf21
The operation is regulated by executing it sequentially in the main unit (1), but here it will be explained as the operation of the main unit (1), and the system test program (4) is stored in the external storage device (6 ) has already been stored in the MMU+31 via the channel control device (5) via the IOC (25).

First, the program (4) that performs the system test performs initialization (e (30a)) necessary for the program itself to operate, such as flags and tables.Furthermore, test data is generated in MM[J[31] (30b). , prepare before conducting a system test. Next, in order to start the test, one of the simulator addresses (21a) to (21d) built in the input/output simulator device vJt (17) is taken out, and an input/output command is started for that simulator address. Enable Deba Side Engagement (30
d) If there is a request for side cutting, the interrupt will be taken there. The objects to be diagnosed here are directly the channel control devices 11f81 and +91.

(lo) 1, and indirectly the CPU [21, MM
The inclusion of U131 and the like is the same as in the conventional device. Also, the simulator address is shown in the conventional example (
It is equivalent to the input/output device address such as 20a), and can be arbitrarily designated by a switch or the like within the input/output control simulator device (17). When input/output interrupts are enabled, if there is an interrupt request, the interrupt is immediately disabled (30g) to prohibit interrupts and perform interrupt processing.

This interrupt processing checks whether the interrupt information such as the status of the simulator address that occurs when an interrupt occurs is correct, and whether the transferred data is correct or not.
and whether the data is correctly transferred to the simulator device (30 hours)
). If these tests are correct, preparations are made for entering the next test (31j). If an input/output interrupt is not requested at step (30e), the interrupt is immediately disabled and the next simulator address test begins. If the test result is not correct (30h), an error message is output to the system control console (6) via the main body (1). If no input/output interrupt is requested at (30e), the interrupt is immediately disabled and the next simulator address test begins. After (31j), load the simulator address (31J), then check whether 5 minutes have passed since the start of the test (30t), and if it is within 5 minutes, proceed to (31n). At (31n), it is checked whether all simulator addresses are in the input/output interrupt waiting state or not. If the CPU t21 is in the interrupt waiting state, the CPU t21 enters wait state 9 and waits for the input/output interrupt (30p). If an interrupt occurs here, the process goes to (30g) again and the same interrupt processing is performed thereafter.

If 5 minutes or more have elapsed at (30/=), the mode moves to the next diagnostic mode (30m) and the test is performed again in the same procedure from (30a). The diagnostic mode here means, for example, changing the number of transfer blocks of the MMU+31 and the diagnostic device, for example, the simulator address (21a), and changing the test processing method depending on parameters. As described above, the system is tested according to the processing procedure shown in FIG.

Figure 3 is a time chart showing the operating status at each simulator address shown in Figure 1.
The program (4) stored in the MU 131 is executed according to the processing flow shown in FIG.
21a) becomes busy. Then, after a certain amount of time has passed, the operation of the simulator address (21a) changes to ip:#
), the state becomes ready as shown by symbol (34). That is, the shaded area in FIG. 3 is the time during which the simulator address is operating. An input/output interrupt is generated when the simulator address operation is completed. Here, while the simulator address (21a) is in operation, an input/output instruction is activated for the next simulator address (21b). Thereafter, input/output instructions are sequentially activated for other simulator addresses in the same way.

On the other hand, when the first simulator address completes its operation during the input/output instruction activation process, an input/output interrupt is generated and preparations for the next test begin. The areas other than the hatched areas in FIG. 3 are the time during which the program (4) is processing, ie, test schedule, test preparation, input/output interrupt processing, interrupt information testing, etc. By using the input/output control simulator device (17) in this way, the channel control device +81, 191, (10) (!:, C
It becomes possible to test systems including PU t21 and MML13).

Note that in the above embodiment, the input/output control simulator device (
Although the set of simulator addresses built into 17) can be specified arbitrarily using switches, it is also possible to specify them using a program.

Further, in the above embodiment, one simulator device is connected to each system, but any number of simulator devices can be attached to each channel control device, and there is no particular restriction.

〔Effect of the invention〕

As described above, this invention enables testing of a system including a CPU, MMU, and channel control device without actually connecting an IOC or input/output device, thereby saving space. Since the input/output control simulator device does not involve mechanical movement, it has the effect of providing high quality and efficient system testing.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a flowchart showing the processing flow of the system test control device according to the invention, and FIG. 3 shows the operating status of each simulator address shown in FIG. FIG. 4 is a block diagram showing the configuration of a conventional system test control device, i]! FIG. 5 is a flowchart showing the processing flow of the device shown in FIG. 4, and the wcG diagram is a time chart showing the operating state of the conventional input/output device. (1) is the main body, (2) is the CPU, +31 is the MMU,
14) is a test program, +51, +81,
[91, (10) are respectively channel control devices, (6)
is a system control console, (7) is an external storage bag [, (17) is an input/output control simulator device, (21a) to (21d)
is the simulator address. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] A test program stored in a main storage device is sequentially read and executed by a central processing unit, and based on the execution results, each input/output control device is connected to the channel control device via each channel control device. The above is achieved by giving commands to the input/output controller, operating each input/output device controlled by the input/output controller, and inputting and processing reports of the operation results of the input/output devices from the input/output controller via the channel controller. In a system test control device that tests the operation of a system including each channel control device, the main storage device, and the central processing unit, an input/output control simulator device that simulates the operation of each input/output control device controls each channel. The input/output control simulator device is connected to the device, and each simulator address corresponding to the address of each input/output control device is provided in the input/output control simulator device, and a command input by specifying a simulator address from each channel control device is received. , execute a simulation of the operation corresponding to the command of the input/output control device corresponding to the simulator address, and operate to send a predetermined report as a completion report of this simulation to the channel control device. A system test control device featuring: