JPS6254276B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a color killer circuit in a color television receiver.

A color killer circuit stops the operation of color amplifiers, etc. when receiving black-and-white television broadcasts or color television broadcasts in weak electric field conditions. The detection output is smoothed by an integrating circuit equipped with a charging/discharging capacitor to create a color killer signal. In addition, a color killer circuit that detects the burst signal by using the output of a color demodulator during the color burst period is also disclosed in Japanese Patent Publication No. 47-28170 [97
(5)K71].

However, if the detection output of the burst signal is simply integrated (smoothed) and used as a color killer signal, the following problems arise. That is, if we now consider the case where we switch from a color broadcasting channel with a normal electric field strength to a color broadcasting channel with a weak electric field, the amplitude of the color burst signal in that weak electric field channel will be smaller and the phase will be disturbed. , the burst signal is no longer detected. For this reason,
The color killer voltage obtained from the integrating circuit that smoothes the output of the detection circuit remains in the state during normal color reception until the discharging of the integrating circuit is completed. Therefore, in such a transient state immediately after channel switching, the color signal system within the receiver operates, but
In this state, color synchronization is disrupted as described above, so color noise will occur on the screen.

Therefore, the present invention proposes a color killer circuit that prevents the occurrence of color noise immediately after channel switching. That is, the present invention focuses on the fact that color synchronization is largely deviated in a weak electric field state, and achieves the above object by forcibly controlling an integrating circuit for color killer signal smoothing when color synchronization is largely deviated. In addition, by configuring the system to compare the output sizes of the two color demodulators during the color burst period to detect the presence or absence of a burst signal and the deviation of color synchronization, it is possible to prevent malfunctions. Made it possible to realize color killer operation.

The embodiments will be described in detail below according to the embodiments shown in the drawings.

In FIG. 1, numeral 1 is a color amplifier (hereinafter referred to as "color gain control circuit") that amplifies the composite color signal (carrier color signal, color burst signal) given through a bandpass circuit and allows manual adjustment of its gain. ), 2 is
The gain is controlled by a control signal from an ACC (automatic color control) detection circuit 8.
ACC amplifier 3 is the second color amplifier. The ACC detection circuit 8 receives the outputs of the R-Y demodulator 4 and the B-Y demodulator 6 during the color burst period.
Forms the ACC signal. Reference numeral 13 denotes a voltage-controlled color subcarrier generator, which supplies color subcarriers of a predetermined phase to the R-Y demodulator 4 and the B-Y demodulator 6 through the hue adjustment circuit 14 and the phase shifter 15, respectively. On the other hand, the hue adjustment circuit 14→phase shifter 15
The frequency and phase are controlled by a PLL loop consisting of → phase comparator 11 → low pass filter 12 → color subcarrier generator 13. In order to facilitate locking in the PLL loop, a sweeper circuit 16 is provided to superimpose a stepwise sweep waveform on the output of the phase comparator. 10 is a burst gate for supplying a color burst signal to the phase comparator 11; Color killer signal generation circuit 7, ACC detection circuit 8, burst gate 1
0 corresponds to a pulse P ₁ approximately corresponding to the color burst period.
is given. The inputs to the color killer signal generation circuit 7 are the output of the B-Y demodulator 6 and the output of the R-Y demodulator 4, but instead of the output of the R-Y demodulator 4, G-Y demodulation is performed as shown by the dotted line. The output of the device 5 may also be used. This is because the output of the RY demodulator 4 and the output of the G-Y demodulator 5 during the color burst period can be considered to be substantially the same.

That is, the demodulated output of the color burst R-Y demodulator 4 is 0, while the demodulated output of the G-Y demodulator 5 is obtained by matrixing the outputs of the B-Y demodulator and the R-Y demodulator. However, originally G-Y
The output of the demodulator is set to about 3/10 of the demodulation output of the R-Y demodulator and the B-Y demodulator, so the B-
Since the color burst demodulation output input from the Y demodulator to the G-Y demodulator (the color burst output from the R-Y demodulator is 0 as described above) is reduced by 3/10, the color of the G-Y demodulator is reduced by 3/10. Burst demodulation output is approximately 0
It can be regarded as.

In the illustrated embodiment, the color killer signal generation circuit 7 stops the function of the color gain control circuit 1 when receiving abnormal color broadcasts (color synchronization is disturbed) or when receiving monochrome broadcasts. The burst period is not stopped by the killer nullifying means 9.] It not only operates during color reception, but also controls the sweeper circuit 16. For the sweeper circuit 16, the color killer signal generation circuit 7 operates the sweeper circuit when the PLL is not locked and the color synchronization is disturbed, and stops the sweeper circuit 16 when the color synchronization is in effect. work. A horizontal blanking pulse _P2 including a color burst period is applied to the killer nullifying means 9. The color killer signal generation circuit 7 compares the amplitude of the color burst period output of the B-Y demodulator 6 and the color burst period output of the R-Y demodulator 4 or the G-Y demodulator 5 to obtain a killer signal. There is. Therefore, noise is transmitted to the color killer signal generation circuit 7 from the B-Y demodulator 6 and the R-
Color killer signal generation circuit 7
This is canceled out by the in-phase removal effect of the internal comparator, and the color killer signal generation circuit 7 works stably against noise.

Next, a specific implementation circuit will be explained.

In the color killer signal generation circuit shown in FIG. 2, the output of the R-Y demodulator is connected from the line 17 to the _resistor R
The base of the first transistor T 77 forming a differential pair for the _{amplitude comparator 19 is applied to the base of an emitter follower transistor T 76 through} a low-pass filter 18 consisting of a capacitor C ₂ and through a resistor R ₉₅ on the emitter side of this transistor T ₇₆ . is supplied to On the other hand, the output of the B-Y demodulator is transmitted from a line 20 to a low-pass film 21 consisting of a resistor R ₁₀₈ and a capacitor C ₁₀ , and then to an emitter follower transistor.
given to the base of T ₇₉ , this transistor T ₇₉
is applied directly to the base of the other second transistor _T78 of the comparator 19.

Here, the DC bias from the demodulator applied to lines 17 and 20 is the same, and the resistance R ₁₀₁ and
The R-Y path and the B-Y path are under the same conditions, such as R ₁₀₈ and capacitors C ₂ and C ₁₀ are selected to have the same value, but for the comparator 19, R
-Y demodulator output side is given through resistor _R95 , so this resistor _R95 is more important than B-Y demodulator output side.
A lower value will be added due to the voltage drop caused by the voltage drop. This voltage drop is approximately 0.3V. The output of the comparator 19 is given to an integrating circuit 23 via a current mirror circuit 22 formed of transistors T ₇₃ , T ₇₄ , T ₇₅ and resistors R ₉₂ , R ₉₃ , R ₉₄ , and is smoothed by the integrating circuit 23 . be done. Such a smoothed output is connected to the differential pair T ₇₀ and T ₇₁ via the emitter follower T ₇₂ [as a supply bias, a fixed potential V ₁ is directly applied to the base of T ₇₀ , and a diode D ₁₀ and a resistor are applied to the base of T ₇₁ .
R ₈₇ is provided through the base-emitter of transistor T ₇₂ . ] and is supplied from the collector of the common emitter transistor T ₆₉ to the color gain control circuit 1 shown in FIG. 1, and on the other hand, from the collector of the common emitter transistor T ₆₈ to the sweeper circuit 16 (see FIG. 1). The comparator 19 operates only during the burst gate pulse _R1 applied to the base of the constant current source transistor _T83 , and is inactive at other times. Of course, the outputs of the demodulator output and the BY demodulator output other than the color burst period have no influence on the color killer operation.

Next, the operation shown in FIG. 2 will be explained.

First, consider a case where there is no color burst signal (for example, when receiving a black and white broadcast). R-Y demodulator output E _R
Since the demodulators 4 and 6 are designed so that the DC levels of the outputs of the B and Y demodulators E _B are equal, the differential pair transistors T ₇₇ and B of the comparator 19 are
_When the base potentials of T ₇₈ are V _T77B and V _T78B , respectively, V _T77B < V _T78B , and in the differential pair transistors T _{77 and} T 78, T ₇₇ is off and T ₇₈ is on. Since _T77 is in the off state, no current flows through the current mirror circuit 22, and therefore the capacitor 24 of the integrating circuit 23 is not charged, so the potential at point A does not rise. Therefore, the differential pair transistors T ₇₀ and T ₇₁ on the output side are T ₇₀
is on and _T71 is off.

The on-state of _T70 turns on transistor _T69 , and a voltage that stops the color gain control circuit 1 is generated at the first output point _O1 .
[However, the signal at the first output point _O1 is the killer nullification means 9
The color gain control circuit 1 is not stopped at least during the color burst period. On the other hand, due to the off state of _T71 , the transistor _T68 is off, and no voltage for stopping the sweeper circuit 16 is generated at the second output point _O2 , so that the sweeper circuit 16 is in an operating state.

Next, if we consider the case where a color burst signal is applied and the color synchronization is achieved, the color burst signal is transmitted to the B-Y demodulator at 180 degrees as shown in Figure 3.
゜If there is a color burst because the phases are different, the color burst demodulation output of the B-Y demodulator 6 becomes a negative voltage, so the potential of the line 20 decreases, and therefore the base potential V _T78B of the transistor _T78 also decreases. . Note that the transistor T ₇₇ caused by the resistor R ₉₅
Letting the difference voltage between the base potentials of T and _T78 be ΔV ₁ , it is given by ΔV ₁ =(E _R −Vf)R ₉₅ /R ₉₅ +R ₉₇ . However, Vf is the base-emitter voltage when the transistor is conductive. Capacitor by color burst demodulation in B-Y demodulator
When the voltage across C ₁₀ drops and the base potential V _78B of the transistor T ₇₈ drops by more than △V ₁ , the states of the transistors T ₇₇ and T ₇₈ are reversed, and T ₇₇ is turned on and T ₇₈ is turned on.
is turned off. When the transistor _T77 is turned on, a current flows through the current mirror circuit 22, and a current flows through the A point to charge the capacitor 24, so that the potential at the A point rises. Due to the rise in the potential at point A, the base potential of the transistor T ₇₁ also rises, turning off the transistor T ₇₀ of the differential pair and turning on T ₇₁ . When _T70 is turned off, no base current is supplied to the transistor _T69 , so the transistor _T69 is turned off, and no voltage is generated at the first output point _O1 to stop the operation of the color gain control circuit 1. Therefore, the color gain control circuit 1 operates normally. On the other hand, transistor T ₇₁
When T68 is turned on, transistor _T68 is also turned on, and the second
A voltage for stopping the operation of the sweeper circuit 16 is generated at the output point _O2 , and the sweeper circuit 16 is thereby stopped.

FIG. 2 further shows an auxiliary circuit that generates a control voltage in the direction to stop color generation when the B-Y demodulator produces a positive color burst demodulation output (therefore, color synchronization is disturbed). 25 is added, and its auxiliary circuit includes first and second transistors T ₈₁ and T ₈₂ forming a differential pair, a constant current source transistor T ₈₄ and a resistor R ₁₀₂ , and a backflow prevention diode D. It is formed by ₁₁ . and,
The R-Y demodulated output and the B-Y demodulated output input to the auxiliary circuit 25 are provided with levels opposite to those input to the comparator 19 described above. That is, the R-Y demodulator output is supplied directly from the emitter of the emitter follower transistor _T76 to the base of the transistor _T82 ,
On the other hand, the B-Y demodulator output is a resistor with a voltage drop of approximately 0.3V from the emitter of the emitter follower transistor _T79 .
Since it is applied to the base of the transistor T ₈₁ via R ₁₀₀ , it has a magnitude relationship opposite to that of the demodulator output applied to the comparator 19. The base of the constant current source transistor _T84 is connected to the burst gate pulse in common with the constant current source transistor _T83 for the comparator 19.
P ₁ is applied, so the auxiliary circuit 25 also operates during the color burst period.

Next, its operation will be explained. First, the base potentials of transistors T ₈₁ and T ₈₂ are set to V _T81B and
If V _T82B is given, V _T82B = E _R − Vf V _T81B = (E _B − Vf) R ₁₀₀ /R ₉₉ + R ₁₀₀ , and since E _R = E _B , the base potential of transistors T ₈₁ and T _{82 The differential voltage △ V 2 of _ _ _} Even if there is a burst, when a positive output is not produced as the color burst demodulation output of the B-Y demodulator (when the color burst and the B-Y demodulation axis are in the relationship shown in Figure 3), the transistor _T82 is turned on. However, since the transistor _T81 is off, it has no effect on the potential at point A.

However, for example, when receiving a color broadcast in a weak electric field, the phase of the color burst tends to be random, and if the phase of the color burst is particularly disturbed, the positive color burst demodulation output from the B-Y demodulator 6 is RY demodulator 4
A negative color burst demodulation output may occur. In such a case, the transistor T ₇₇ of the comparator 19 is off, so the capacitor 24 is not charged, but when switching from the normal electric field channel to the weak electric field channel, the capacitor 2
4 remains charged during normal electric field reception for a while, and color noise will occur on both sides during that time.In such a case, the auxiliary circuit 2
5, the charge in the capacitor 24 is immediately discharged, so the color gain control circuit 1
stops and the color noise on the screen disappears immediately. That is, the transistor _T81 of the auxiliary circuit 25 is turned on, and the charge on the capacitor 24 is transferred to the capacitor 2.
4 → diode D ₁₁ → transistor T ₈₁ → constant current source transistor T ₈₄ and resistor R ₁₀₂ → earth, and immediately discharges.

Further, the auxiliary circuit 25 includes the color subcarrier generator 1
The color subcarrier generated in 3 is the regular 3.579545MHz.
For example, when there is a deviation of ±1/2f _H (f _H is the horizontal frequency) or a deviation of ±1/4 f _H , the color is erased and the sweeper circuit is activated. Color subcarrier is ±3.579545MHz
When 1/2f _H =±7.875 KHz deviates, the color burst demodulated output from the BY demodulator 6 becomes one in which the polarity is reversed at intervals of 1H (one line) as shown in FIG. Incidentally, the phase relationship between the color subcarrier CW and the color burst at each point A to O in FIG. 4 is shown in FIG.

B- whose polarity is reversed at 1H intervals as shown in Figure 4.
When the Y color burst demodulated output is input to the color killer circuit in Fig. 2, first in the part c of Fig. 4, the transistor _T77 of the comparator 19 is turned on, so a charging current flows to the capacitor 24 and A The potential at the point increases. Next, in the section E (same as the section A), the transistor _T77 of the comparator 19 is turned off, and the capacitor 24 is not charged. Moreover, in the auxiliary circuit 25, the transistor _T81
turns on, the charge on the capacitor 24 is discharged through the diode D ₁₁ and the transistor T ₈₁ . In this way, when the color subcarrier is shifted by ±1/ _2fH , the capacitor 24 is repeatedly charged and discharged every 1H, and the potential at point A is kept at a low level _. A level voltage is generated and the color gain control circuit 1 is stopped during the scanning period so that color noise does not appear on the screen and a high level voltage is not generated at the second output point _O2 , so the sweeper circuit 16 continues the sweeping operation. In this way, the color synchronization PLL is prevented from becoming locked. In the above explanation, the case where there is a deviation of ±1/2f _H was explained, but even in the case where there is a deviation of ±1/4f _H , the color burst demodulation output by the B-Y demodulator changes from positive → 0 → negative → 0 → at 1H intervals. Since the positive operation is repeated, locking of the PLL is similarly prevented, and color noise is also prevented from appearing on the screen. Also, exactly ±
Substantially the same operation is performed not only in the case of deviations of 1/2f _H and ±1/4f _H but also in the case of deviations near these values.

FIG. 6 is a concrete circuit diagram showing the color killer signal generation circuit of FIG. 2, and the color amplification circuit system and sweeper circuit controlled by it. The first output point O ₁ is connected to the bases of the transistors T ₆₀ and T ₆₁ , and is a transistor forming a killer nullifying means 9 that lowers the potential of the first output point O ₁ to ground only during the color burst period or the horizontal retrace period. Connected to the T ₆₄ collector. The composite color signal applied to the base of the transistor T ₅₁ via the bandpass circuit 26 is transmitted to the transistors T ₅₁ and T ₅₄ forming the first differential pair, the transistors T ₅₂ and T ₅₃ forming the second differential pair, An ACC amplifier 2 is formed through a color gain control circuit 1 composed of a constant current source transistor T ₅₅ , resistors R ₆₃ , R ₆₄ , R ₆₅ , R ₆₆ , R ₆₇ , R ₆₈ , R ₇₀ and a volumetric volume VR ₁ . From the emitters of the differential pair transistors T ₅₆ and T ₅₇ , through the collector of the transistor T ₅₆ , the transistor T ₆₅ forming the second color amplifier 3 and the emitter follower.
The signal is outputted to point F via T ₆₆ and applied to the RY demodulator 4 and the BY demodulator 6. When a high level voltage is generated at the first output point O ₁ of the color killer signal generation circuit 7, the transistors T ₆₀ and T ₆₁ are turned on and their emitter potential increases, so that the transistors T ₅₁ and T of the first differential pair are turned on. ₅₄ is turned off and the composite color signal applied to the base of transistor T ₅₁ is not output to the collector of transistor T ₅₄ . However, during the color burst period or the horizontal retrace period including the color burst, the first output point _O1 is forcibly clamped to the ground level as the transistor _T64 forming the killer nullifying means 9 is made conductive by the pulse _P2 . Since the first differential pair of transistors T ₅₁ and T ₅₄ do not become inactive during the color burst period, only the color burst signal is led to the collector of the transistor T ₅₄ and guided to the demodulators 4 and 6. The second differential pair transistors T ₅₂ and T ₅₃ are provided to suitably adjust the gain of the first differential pair transistors T ₅₁ and T ₅₄ using the volume VR ₁ .

ACC generated by ACC detection circuit 8 [Figure 1]
The signal is smoothed by an integrating circuit consisting of a resistor 27 and a capacitor 28, and then passed through the upper differential pair transistors T ₅₆ ,
Among _T57 , _T58 , and _T59 , it is applied to the bases of _T57 and _T59 , and is supplied to the emitters of transistors _T56 and _T57 from the collector of transistor _T54 , and the common connection point of the collectors of transistors _T56 and _T58 . The gain of the color composite signal that appears in the amplified form in G is automatically controlled. Similar to the transistor T ₆₄ forming the killer nullifying means 9, the transistor is supplied with a pulse P ₂ and conducts only during that pulse period.
T ₆₃ connects the base points of the second differential pair transistors T ₅₂ and T ₅₃ to ground during the pulse period, and
This removes the effects of VR ₁ , and this
The arrangement is such that the detection operation in the ACC detection circuit 8 is not influenced by the volume VR ₁ set by manual adjustment. The second output point _O2 of the color killer signal generation circuit 7 is connected to the base of the transistor _T42 of the sweeper circuit 16, and when the second output point _O2 is at a high level, the transistors _T42 and _T48 are connected.
is turned on, and turned off when it is at low level.
The sweeper circuit 16 receives the comparison output from the phase comparator 11 (Fig. 1) as shown by B in Fig. 7.
In order to eliminate the inconvenience of not reaching the stable potential E of 3.579545MHz, a sawtooth waveform [actually step-like] is superimposed on the comparison output B [color subcarrier and color burst beat signal]. This is a circuit that outputs a sweep voltage.

In FIG. 6, when capacitor Cc of low-pass filter 12 is not charged, if the potential at point K is _E1 , the potential at point L is _E1 -Vf (however, Vf
represents the base-emitter voltage when the transistor is conductive. Since capacitor Cc is not charging, the potential at point m is 0, and transistors T ₂₇ ,
T ₂₉ is cut off. In this case, finding the potential at point n, point K → R ₂₄ → R ₂₇ → R ₃₄ → T ₂₈ → R ₃₅
→A current flows through the earth path, and this current is D ₅ ,
Determined by D ₆ , D ₇ , T ₂₈ , R ₃₅ , i≒2Vf/R ₃₅
Therefore, the potential _E2 at point n is _E2 = _E1 -i( _R24 + _R27 )= _E1-2Vf / _R35 ( _R24 + _R27 ). Therefore, it is assumed that it is designed in advance so that E ₂ <B ₁ −Vf. Since E ₂ <E ₁ −Vf, T ₃₄ of the differential pair T ₃₄ and T ₃₅ is turned off and T ₃₅ is turned on. When T ₃₅ is on, current flows through resistor R ₄₁ and causes a voltage drop, turning on transistors T ₃₁ , T ₃₂ , and T ₄₀ . When the transistor T ₄₀ is turned on, current flows through the transistor T ₄₀ and the transistor T ₄₇
Since the transistor T ₄₇ is turned on by supplying base current to the transistor T 47, the collector potential of the transistor T ₄₂ becomes 0 V if the resistance between the collector and emitter is ignored, so no base current flows through the transistor T ₃₀ . Transistor T ₃₀ is cut off. As mentioned above, since the transistor _T31 is in the on state, a charging current flows into the capacitor Cc through the point m.

At this time, the transistor _T30 is in the cut-off state as described above, so the current flows through the transistor T30.
Does not flow to T ₃₀ . As capacitor Cc is charged, the potential at point m increases, and accordingly n
The potential at the point also increases. The transistor T ₃₁ ,
Since the transistor T ₃₂ is also in the on state as well as T ₄₀ , the potential difference generated across the resistor R ₄₆ increases, and the potential at point l also rises, but when E ₁ is exceeded,
Transistor T ₃₇ is turned off and transistor T ₃₉ is turned on instead, so the potential at point l is clamped to the value of E ₁ +Vf. When the n-point potential becomes higher than the l-point potential, the transistor T ₃₄ of the differential pair T ₃₄ and T ₃₅ turns on and the transistor T ₃₅ turns off. When T ₃₅ turns off, transistors T ₃₁ , T ₃₂ and T ₄₀ turn off. Then, since the transistor _T31 is turned off, no charging current flows to the capacitor Cc, so the capacitor Cc is not charged and starts discharging.
Since the transistor T ₄₀ is turned off, no base current is supplied to the transistor T ₄₇ , and the transistor T ₄₇ is also turned off. Therefore, a bias is applied to the base of the transistor _T30 , and the charge in the capacitor Cc is discharged along the path of point m→collector of _T30 →emitter of _T30 → _R36 . Transistor T ₃₂
is turned off, the potential at point l becomes E ₁ −Vf
decreases to When T ₃₄ of the differential pair is turned on, transistor T ₃₃ is turned on, and current flows from the power supply (+Vcc) to ground through resistors R ₄₃ and R ₄₄ and transistor T ₃₃ . This is when charging capacitor Cc (+Vcc) → R ₃₇ → T ₃₁ → point m → capacitor Cc
This is to prevent ripples from being added to the power supply (+Vcc) by flowing the same amount of current as the current flowing through the route.

When the capacitor Cc is discharged and the potential at point n becomes lower than the potential at point l, the above-described charging and discharging is repeated. In FIG. 8, X ₁ is the charging period of the capacitor Cc, and X ₂ is the discharging period. As far as the above explanation is concerned, the sweep voltage is just a sawtooth wave, but a pulse P ₃ with a frequency of f _H /16 is applied to the base of the transistor T ₃₀ during the falling period of the sweep waveform.
As a result, the transistor _T30 turns off and on, and the potential at point m and the potential at point q form a step waveform as shown in FIG. 9 during the falling period _X2 . That is, at the high level of pulse P ₃ , transistor T ₃₀ is in the on state [power supply (+Vcc) → R ₄₉ → R ₃₉ →
Since the base bias applied through the base path of T ₃₀ is not nullified, it is in the on state], and the charge of the capacitor Cc is discharged through the collector-emitter of the transistor T ₃₀ and the resistor R ₃₆ , so the potentials at points m and q are It descends [period t in Figure 9].

When the pulse _P3 is at a low level, the transistor _T30 is turned off, the discharging operation of the capacitor Cc by the transistor _T30 is stopped, and the potential drop at points m and q stops [period T in FIG. 9]. Then, in a period close to the stable potential E of this period T, the 10th
As shown in the figure, the output B of the phase comparator 11 is Z ₁ , Z ₂ ,
I was blessed with the opportunity to be locked to a stable potential E at _three points Z,
PLL color synchronization is locked.

At this time, the color killer signal generation circuit 7
The high level voltage applied from the second output point O ₂ turns on transistors T ₄₂ and T ₄₃ and sets transistors T ₃₀ and T ₃₆ to the cut-off state, so that the sweep operation of the sweeper circuit 16 is stopped.

The color killer circuit of the present invention distinguishes and detects three states: a state in which color synchronization is normal, a state in which a color burst signal of a predetermined strength or higher does not exist, and a state in which color synchronization is significantly deviated, and a state in which color synchronization is normal. Then, the integrating circuit for creating the color killer voltage is charged (or discharged), the charging and discharging of the integrating circuit is stopped in the absence of the burst signal, and the integrating circuit is discharged (or discharged) in the state where the color synchronization is greatly deviated. Therefore, even when switching from a channel in a normal color broadcast reception state to a channel in a weak electric field reception state where the color synchronization deviates significantly, the color killer signal obtained from the integration circuit is immediately followed. Therefore, it is possible to prevent color noise from occurring on the screen immediately after such channel switching.
Moreover, since the detection of the three states mentioned above is achieved by the first and second comparators that compare the magnitude of the outputs of the two color demodulators during the color burst period, their detection is not affected by noise. It is possible to perform the color killer operation accurately without being affected by the error, and therefore, it is possible to realize a color killer operation without any malfunction.

[Brief explanation of the drawing]

All drawings relate to the present invention,
Fig. 1 is a block diagram showing the color killer circuit together with related circuits, Fig. 2 is a specific circuit diagram of the color killer signal generation circuit, Figs. 3, 4, and 5 are explanatory diagrams of Fig. 2; Figure 6 is a circuit diagram showing the control system using the color killer circuit, Figures 7, 8, and 9.
10 are explanatory diagrams of FIG. 6. 1...Color gain control circuit, 4...R-
Y demodulator, 5... G-Y demodulator, 6... B-Y demodulator, 7... Color killer signal generation circuit, 9... Killer nullification means, 10... Burst gate, 11... Phase comparator, 12... Low pass filter, 13... Color subcarrier generator, 15... Phase shifter, 16... Sweeper circuit,
19... Amplitude comparator, 22... Current mirror circuit,
23...Integrator circuit, 25...Auxiliary circuit, _T77 ...First transistor, _T78 ...Second transistor, _T81 ...Third transistor, _T82 ...Fourth transistor.

Claims (1)

[Claims] 1 B-Y demodulator color burst period output and R
- Detect whether the color synchronization between the subcarrier signal input to the demodulator and the color burst signal is in a normal state by comparing the magnitude of the color burst period output of the Y demodulator or the G-Y demodulator. the subcarrier signal by comparing the magnitude of the color burst period output of the B-Y demodulator and the color burst period output of the R-Y demodulator or the G-Y demodulator with a first comparator that and a second comparator for detecting whether or not the color synchronization of the color burst signal is greatly deviated; and the output of the first and second comparators is obtained to charge the integrating circuit ( or discharging), and in a state where there is no color burst signal of a predetermined intensity or higher, charging and discharging of the integrating circuit is stopped, and in a state where the color synchronization is significantly deviated, controlling the integrating circuit to discharge (or charge). 1. A color killer circuit comprising: a color killer circuit, wherein the output voltage of the integrating circuit is used as a color killer signal.