JPS6253849B2 - - Google Patents

Description

[Detailed description of the invention]

[Technical Field] The present invention relates to a digitally controlled arbitrary waveform generation circuit. [Prior Art] Many dedicated circuits that can generate only specific waveforms have been known in the past, but it is clear that it would be extremely convenient if any different output waveforms could be obtained with the same circuit configuration. For example, in video game machines and the like, since it is required to generate a special sound for each model, conventionally, a dedicated sound generation circuit is designed and added to each model. However, in such devices that are produced in a wide variety of small quantities, it is very uneconomical to design and add a waveform generation circuit according to a dedicated sound generation circuit for each model, and it is difficult to produce a variety of different sounds with the same circuit. In addition, it has been desired to be able to generate multiple sounds simultaneously, and it has been desired to provide an arbitrary waveform generation circuit for this purpose. On the other hand, a function generator is conventionally known as a waveform generating circuit with this kind of degree of freedom, but the waveform that can be extracted as its output is a sawtooth waveform obtained as a triangular wave, square wave, sine wave, or a combination thereof. waves, ramp waves, exponential waves, etc., and are limited to specific waveforms. Therefore, in order to generate arbitrary waveforms other than those in the function generator router, a separate dedicated circuit must be set and added each time. [Object of the Invention] An object of the present invention is to provide a waveform generation circuit that can generate a waveform of any frequency and shape by reading out a desired type of waveform at a desired cycle from waveform data stored in advance in a waveform memory. It is about providing. Another object is to use the arbitrary waveform generating circuit of the present invention as a suspicious sound generating circuit to obtain different desired suspicious sounds using the same circuit. Further, according to the present invention, waveforms necessary to obtain a video signal for forming a desired image can be generated. In the present invention, a plurality of different waveforms for creating suspicious sounds or images are provided, and these waveforms are stored in advance as data in a waveform memory as corresponding digital waveforms. As is well known, a general waveform has three elements: waveform (shape), repetition frequency (period), and amplitude, and if any one of these is different, it will be a different waveform. It appears as a difference in pressure, and in the case of images, it appears as a difference in image shape. Note that the frequency also includes the initial phase, which determines the coordinate position of the image, especially in the case of an image. Corresponding to the above three elements, each element is arbitrarily designated in the waveform generation circuit of the present invention, and the waveform is determined by the selection of the waveform data type stored in the waveform memory, and the waveform is determined by the selection of the waveform data type stored in the waveform memory. The frequency (period and initial phase) is determined by setting the readout frequency division ratio of the data. After the waveform and frequency are set digitally, the amplitude is set. [Structure of the Invention] A characteristic feature of the present invention is that the selection of waveform data and the setting of the readout frequency division ratio are processed separately. It has the advantage that any frequency can be set simply by inputting it, and that a large number of waveforms can be generated even though the amount of data stored in the waveform memory is limited. That is, according to the present invention, by changing the readout period (readout address interval) for each waveform data, the data is appropriately thinned out or appropriately multiplexed and read out. The repetition frequency can be set. Further, in the present invention, it is preferable that the reading frequency is set by digitally adding the input frequency data every fixed cycle, and specifying the address of the waveform data based on the addition result. Further, in order to determine the initial phase of the readout frequency described above, it is preferable to input initial phase data separately from the frequency data and read this initial phase data at the time of the first addition. [Embodiment] A specific example of the arbitrary waveform generation circuit of the present invention will be described below with reference to the accompanying drawings, with reference to FIGS. 1 to 4. According to the circuit of this specific example, three waveforms can be obtained. Therefore, three predetermined waveforms are apparently superimposed and output, and for example, for a suspicious sound generation circuit, three waveforms are output.
It is possible to simultaneously output different kinds of sounds, and it is also possible to draw images of different waveforms or colors on a display for a video generation circuit. However, since the present invention is based on processing only a single waveform, hereinafter, only one waveform processing will be mainly explained, and other explanations will often be omitted. In the first embodiment, a waveform selection and division ratio setting circuit that selects a desired waveform from a waveform memory and digitally sets its repetition frequency includes multiplexers 1 and 2, a data register 3, an accumulator 4, and an adder. 5 and a latch 6. In Figure 1, 1 is a multiplexer whose input terminal A is connected to the address bus AB of the central processing unit CPU, and 2 is a multiplexer whose input terminal A is the data bus of the CPU.
It is a multiplexer connected to the DB. The output terminal Y of multiplexer 1 is connected to both address input terminals A of data register 3 and accumulator 4, and the output terminal Y of multiplexer 2 is connected to data register 3 and to both address input terminals A of accumulator 4.
and both data input terminals D of the accumulator 4. That is, multiplexers 1 and 2 are CPU
When writing data to the data register 3 and accumulator 4, it serves to connect the address bus AB and data bus DB of the CPU to the address and data inputs of the data register 3 and accumulator 4. In this embodiment, the data register 3 stores two sets of data consisting of 16-bit frequency data D and 4-bit amplitude data A, as well as 20-bit frequency data, as shown in the upper part of FIG. D and 4
A total of three sets of bit amplitude data A are held, and three different waveforms are processed in a time-division manner. However, the frequency data D is divided into 4 digits each having 4 bits, and the 20-bit frequency data is divided into 5 digits each having 4 bits. Partial frequency data obtained by division is expressed in Dnm. In this case, the subscript n represents the group to which the partial frequency data belongs, and m represents the weight of the digit. Frequency data D specifies the frequency of the output signal finally obtained (addressing cycle of waveform memory 7), and amplitude data An (n represents the group to which the data belongs) specifies the amplitude of the output signal. It is. On the other hand, the accumulator 4 is a type of register, and is a device in which input values are sequentially added to an initial setting value (including zero), and this operation result is replaced with the original value.
As shown in the lower part of the figure, 16-bit augend data C is used to set the initial phase of the waveform as necessary.
and 4-bit waveform selection data W as a group, and a total of 3 sets of data including 20-bit initial phase setting augend data C and 4-bit waveform data W as a group. ing. Here, the data initially set in the accumulator 4 sets the initial phase of the waveform. The augend data C is similarly divided into 4 or 5 digits of 4 bits each, and is represented by partial augend data Cnm corresponding to one digit. This partial addend data Cnm and target waveform selection data
As described above, the subscript n added to Wn represents the group to which these data belong, and the subscript m represents the digit position. Of the three groups of data above, each one group (e.g.
D ₁₀ to D ₁₃ , A ₁ , C ₁₀ to C ₁₃ ·W ₁ ) handle data related to one waveform (frequency data, amplitude data, initial phase data, waveform selection data). The symbols above each block in the upper and lower rows of FIG. 2 represent the address of each data section in hexadecimal notation. This address is designated by a synchronization signal SS from the control signal generator 11, which will be described below. The control signal generator 11 generates a synchronization signal SS and a control signal CS as shown in FIG. sync signal
SS is 4H (750KHz), 8H (375KHz), 16H
4 consisting of (187.5KHz) and 32H (93.75KHz)
It is a bit binary signal. The control signal CS is
Multiplexer switching signal MPX, accumulator write signal
WRO, data register write signal WR ₁ , first latch signal PCK, first latch clear signal CLR, and second latch signal TCK. However, WRO,
WR ₁ is a signal synthesized within the control signal generator 11 after receiving the write control signal WRC from the CPU. As can be seen from FIGS. 2 and 3, the switching signal MPX applied to the control input terminal S of the multiplexer 1 is at logic "1" in the latter half of each address section of the synchronizing signal SS. Therefore, the multiplexer 1 is switched to the input terminal B side each time. Therefore, the synchronization signal SS applied to the same input terminal is inputted to the data register 3 and the accumulator 4 through the multiplexer 1 to designate an address. Therefore, data from the designated addresses "0" to "F" are sequentially output from the data register 3 and the accumulator 4. The adder 5 adds the frequency data D output from the data register 3 and the augend (initial phase) data C output from the accumulator 4 in a bit parallel digit series format. In other words, for addresses “0” to “F” of the synchronization signal SS, partial data of the same digits
Addition result of Dnm and Cnm, i.e. sum (4 bits)
and carry data (1 bit) are output. However, this carry may or may not occur depending on the actual values of data Dnm and Cnm. The sum and carry data from the adder 5 are each sent to and latched into the latch 6.
This latch signal PCK is generated in about the first half of the logic "1" interval of the multiplexer switching signal MPX and inputted to the latch 6. The sum latched in latch 6 is passed from the output terminal of latch 6 through line 12 to input terminal B of multiplexer 2, through which it is input to accumulator 4. In this case, since the accumulator write signal WR is a pulse generated in the latter half of the logic "1" interval of the multiplexer switching signal MPX, the sum data from latch 6 is the pulse that is generated in the sum. is written to the address location of the augend data. For example data D ₁₀ and
The sum of _C10 is written to the address of data _C10 . On the other hand, when a carry occurs in the addition result, the carry data is sent from the output terminal of latch 6 through line 13 to input terminal C of adder 5. Therefore,
For example, if a carry occurs when adding data D ₁₀ and C ₁₀ , as a result, the next data D ₁₁ and C ₁₁
The addition with is performed by taking this digit data into consideration. In the present invention, the accumulator 4, adder 5 and latch 6 form adding means. Reference numeral 7 denotes a waveform memory in which a plurality of waveform data are stored, and the address input terminal of the lower 5 bits of this waveform memory 7 is connected to the latch 6 so that the upper 5 bits of the augend data C are input as frequency division ratio data. connected to the output terminal. The remaining upper three bit address input terminals are connected to the output terminal of the accumulator 4 so that the waveform selection data Wn is input. A latch 8 is connected to the 4-bit output terminal of the waveform memory 7, and a latch 9 forming an amplitude setting circuit is connected to the output terminal of the data register 3. Both latches 8 and 9 are latched by the second latch signal TCK. As can be seen from FIG. 3, this second latch signal TCK is generated in the interval (t=4, 9, F) in which the synchronizing signal SS specifies the addresses of the amplitude data An and the waveform selection data Wn. At this point, the accumulator 4 outputs waveform selection data Wn, and the data register 3 outputs amplitude data An. Therefore, the data latched in latch 8 is waveform selection data.
The upper address is specified by Wn, and the addition result latched in latch 6 is the data from waveform memory 7 whose lower register is specified as frequency division ratio data.Also, what is latched in latch 9 is amplitude data An. It is. Reference numeral 10 denotes a D/A converter that converts the digital signal from latch 8 into a corresponding analog voltage signal, and the gain of this converter is changed by amplitude data from latch 9 (amplitude setting circuit). A desired output waveform from this D/A converter 10 can be obtained. FIG. 4 is an example of the circuit indicated by the solid line in FIG. 1, and the same components are given the same reference numerals as in FIG. 1. Multiplexers 1 and 2 are Texas Instruments ICs SN74LS157 and SN74LS158.
The data register 3 and accumulator 4 are
ICSN7489, adder 5 is ICSN74LS283 of the same company
However, latch 6 uses the company's SN74LS174, and latches 8 and 9 use the company's ICSN74LS273, and the waveform memory 7 and control signal generator 11
The partial component 11' is manufactured by Intersil Corporation.
ICIM5623A is used. An example of the operation of the arbitrary waveform generating circuit of the present invention will be explained with reference to FIGS. 1 to 4. For convenience of explanation, let's consider a case where an arbitrary question sound is generated. As is well known, the type of sound is determined by the three elements of the signal applied to a speaker or the like: its frequency, amplitude, and waveform. Therefore, in order to obtain any desired sound, it is necessary to be able to freely and accurately set these three elements. Referring again to FIGS. 2 and 3, when the synchronization signal address t=0, the frequency data D ₁₀ is sent from the data register 3 and the initial phase data C ₁₀ is sent from the accumulator 4.
are output, adder 5 adds them, latch 6 latches the sum and carry output, and this sum is written to the original address of _C10 . When the address is t=1, D ₁₁ and C ₁₁ are output in the same way, and latch 6 latches the sum and carry output, and the sum is returned to the original.
Written to address C ₁₁ . address is t=2
When t=3, the same processing is performed for D ₁₂ and C ₁₂ , and when the address is t=3, the same processing is performed for D ₁₃ and C ₁₃ . During this period, if a carry output is generated in the adder 5, the carry data is added to the adder 5. This means that the timing when a logic "1" output actually appears in the upper 5 bits (dividing ratio data) of the augend data C, that is, the 4 bits of _C13 and the 1 bit of _C12 , is different from the time when the output of logic "1" actually appears on the frequency data D and the augend data. The larger the actual value of the addition (initial phase) data C is,
It means to arrive early. Next, when the address is t=4, the data register 3 outputs the amplitude data A ₁ and the accumulator 4 outputs the waveform selection data W ₁ . The latter waveform selection data W ₁ and the sum latched by the latch 6 at t=3 are separately stored in the upper 3 bits address (waveform selection data) and lower 5 bits address (frequency division ratio data) of the waveform memory 7, respectively. Added. Therefore, waveform data corresponding to these addresses are read from the waveform memory 7. The read waveform data and the amplitude data _A1 are simultaneously latched into latches 8 and 9, respectively, by the latch signal TCK. The above operation is performed sequentially for three data groups of n=1, 2, and 3, and three different types of waveform processing are performed in a time-sharing manner. Here, one process performed on each data group is defined as one cycle.
Addend data C and frequency data D are each 4
Since the bit partial data is serialized for 4 digits, the total 16-bit data is also the augend data C.
16-bit frequency data D is added only once per cycle. Table 2 shows the state of the augend data C, that is, the frequency division ratio data, accumulated for each cycle for one type of waveform, and an example of the waveform data output from the waveform memory 7. Sn(n=0,
1, 2, 3, 4...) represents the number of cycles, and WD-O in the waveform data column indicates the output waveform data based on Table 1 when the waveform selection data W ₁ = 0.
7 shows output waveform data based on Table 1 in the case of waveform selection data W ₁ =7. Table 1 shows an example of the contents of the waveform memory 7. Frequency data D in the initial state is D=0800H
Let us assume that the augend data C is C=0000H. The H at the end represents hexadecimal. In cycle S ₀ , the waveform selection data is OH, so the upper 3 bits of the waveform memory address are 000.
Since C=0000H, the upper 5 bits of the waveform memory address output from latch 6 are
00000, therefore, the waveform memory is designated with an address of 00000000, that is, 00H, and waveform data "7" is read from the waveform memory. Similarly, in cycle S ₁ , W=0H, C=
Since it is 0800H, the upper 3 bits and lower 5 bits of the waveform memory address are 000 and 00001, respectively, which is 01H.
Waveform data "9" is read out. In this way, since the frequency data D is added to the augend data C every cycle, the content of the augend data C changes as shown in Table 2 every time one cycle is completed. The waveform memory 7 stores seven different types of waveform data from "0" to "7" as shown in Table 1, so if the waveform selection data W ₁ is 0, the waveform data shown in Table 1 is Two stages of data are taken out, and they change as shown in the WD-0 column of Table 2 at the end of each cycle. In Figure 5, the horizontal axis represents the number of cycles Sn, and the vertical axis represents the analog quantity corresponding to the waveform data.
This represents the output waveform obtained from this waveform data. It can be seen from this that a sine waveform is obtained when W ₁ =0. On the other hand, if the waveform selection data _W1 is 7, the waveform data changes as shown in the column WD-7 of Table 2. This situation can be seen in the fifth
When expressed in the same manner as shown in the figure, it can be seen that a sawtooth wave as shown in FIG. 6 is obtained. In this way, depending on the value of the waveform selection data _W1 , it is possible to select the waveform data in the waveform memory 7 and, therefore, to select the output waveform. Therefore, by simply storing appropriate waveform data in the waveform memory 7, any waveform can be output. Next, let's consider frequency, one of the three elements of sound. Looking at the value of the augend data C in Table 2, the value of C at the initial state _S0 is equal to the value of C at the time of _S20 . This means that the value of C becomes the same as the initial state after 20 cycles from _S0 , and the address of waveform memory 7 returns to the initial state.
One wavelength will be output during 20 cycles.
Therefore, the section corresponding to this one wavelength is defined as "one period". In this embodiment, the value of the augend data C is
The period during which the value increases by 10000H is one cycle. However, the number of cycles required to obtain one cycle of the waveform varies depending on the value of the frequency data D. That is, if the waveform data read addressing period is short, a large number of cycles are required to obtain one period of the waveform, and if it is long, one period of the waveform can be obtained with a small number of cycles. If the number of cycles occurring during one period is N _s and the value of frequency data is D', then N _s = 10000H/D' (4-digit example) N _s = 100000H/D' (5-digit example) If the time taken for one cycle is ts, and the time taken for one period is Ts, then Ts=Ns・ts One wavelength is output per period, so if the frequency of the output waveform is F ₀ , then F ₀ = 1/Ts=1/ Ns・ts=D′/ts・1000
0H (1) Here, since ts is a constant determined by the synchronization signal SS, the frequency F ₀ is determined by the value D' of the frequency data. This shows that the frequency of the output waveform can be arbitrarily set depending on the value of the frequency data D. In Table 2, the waveform data changes every cycle, so Table 2 is an example of the case where the above-mentioned output frequency is the highest. However, if at the end of one cycle, the content of the augend data C is small and therefore the content of the upper five bits of the augend data C does not change, the waveform data output from the waveform memory 7 also does not change. Therefore, until the content of the upper five bits of the augend data C changes, a number of cycles pass (multiple reading is performed), and the output frequency becomes lower accordingly. By the way, if the time ts required for one cycle is similarly expressed as a frequency and is denoted by F _T , the above equation (1) becomes as follows. F ₀ =F _T・D'/10000H (2) Therefore, if we look at D'/10000H as the division ratio of F _T and F ₀ , this circuit has a variable division ratio for dividing F _T. It can be seen that it functions as a peripheral device. As is clear from the above description, in this embodiment, in order to generate three different waveforms, calculation processing is performed sequentially on three data groups during one cycle, and the cycle The first group is set at addresses t=0 to 4 of the signal SS, and the second group is set to addresses t=5 to 9.
The processing of the first group and the third group at t=A to F is performed by sequentially operating the same circuit. Therefore, the output waveforms are analog outputs based on the address waveform data corresponding to the calculation processing of the first, second, and third groups, respectively. Therefore, for example, the sine waveform 21 in FIG.
Assuming that a waveform 22, which is the same sine waveform as shown in the figure but has a frequency of 1/2, is obtained, and a sawtooth waveform 23 shown in Fig. 6 is obtained by processing in the third group, the output waveform obtained as a whole is as shown in Fig. 7. As shown, it is a composite of these. In this case, as shown in FIG. 7, when switching from one group to another, a switching signal component appears on the waveform. However, the time ts required for one cycle is 10.67 μs as shown in FIG. 3, and the frequency Fs of the switching signal is much higher than the highest human audible frequency. Therefore, when listening to the waveform in Fig. 7 as sound, the switching signal component is not audible, and it is heard as the average value of the waveform, that is, the same as the analog summation of the output waveforms based on the processing of each group, for example. It becomes possible to overlay game play sound on background sound in video games, etc. The manner in which the frequency, shape, and amplitude of the output waveform are set in the embodiments shown in FIGS. 1 and 4 has been described above. However, the present invention is not limited thereto, and various changes and modifications can be made within the spirit of the present invention. For example, the data configuration shown in FIG. 2 is an example, and by changing the timing of generation of the control signal CS from the control signal generation circuit 11, the number of bits of each data D, C, A, and W can be changed arbitrarily. be able to. Also, the reason why one digit was made into 4 bits was simply due to the relationship with the IC used. That is, the data configuration can be arbitrarily changed according to the required accuracy and resolution in each set value of frequency, waveform shape, and amplitude. For example, increasing the number of bits of data D and C increases the frequency resolution, and increasing the number of bits of data A increases the amplitude resolution.
In addition, the waveform memory 7
By increasing the number of data bits added to the address and the number of bits of the output of the waveform memory 7, the accuracy of waveform approximation increases. Since one sound can be produced by one data group, the number of sounds to be produced at the same time also changes depending on the number of data groups. It is sufficient to prepare as many data groups as the number of sounds required. The arbitrary waveform generation circuit of the present invention can generate arbitrary waveforms with different frequencies, waveform shapes, and amplitudes using the same circuit when only one data group is provided, and therefore can generate various different sounds. Alternatively, as already mentioned, it can be used as a frequency divider. Furthermore, when a plurality of data groups are provided, a plurality of the waveforms, etc. can be combined using the same circuit, and therefore more complex sounds can be output simultaneously. For example, while generating the driving sound of a moving object displayed on the screen of a video game machine, it is easily possible to generate score sounds as needed. Moreover, regardless of whether the data group is configured as one set or multiple sets, the following can be said in common:
Even if different sounds or multiple sounds can be produced simultaneously, there is no increase in the number of parts, and the circuit is suitable for mass production or IC implementation. The portion of the frequency dividing device with variable frequency division ratio in the above embodiment can also be realized by a circuit as shown in FIG. 8 or 9. FIG. 8 shows a circuit using a rate multiplier as a frequency divider. In FIG. 8, latch 30 holds rate input data D _R of rate multiplier 31. In FIG. Latch 32 holds waveform selection data and supplies the upper address of waveform memory 33. Latch 34 holds amplitude data. The waveform memory 33 stores waveform data. Counter 35 counts the output signal of the rate multiplier and supplies the lower address of waveform memory 33. D/A converter 36 converts the digital signal into an analog signal. Now, set the number of bits of rate multiplier 31 to 11.
bit, latch 30 and data D _R bit number to 11
The number of bits of the counter CT is 5 bits, the frequency of the clock signal of the rate multiplier is F _T , the frequency of the output signal of the rate multiplier 31 is F _R , and the frequency of the analog output signal is F ₀
Then, since the rate multiplier 31 is 11 bits, F _R =FT・D _R /800H Since the counter 35 is 5 bits, F ₀ =1/20H・F _R Therefore, F ₀ =F _T・D _R /10000H...(3) From equation (3), we find the frequency division ratio F _{R1.F R1 =} D _R /10000H...(4) It works as a frequency divider, and any frequency can be set. I understand. FIG. 9 is an example of a circuit using a programmable divider. In this circuit, the rate multiplier 31 shown in FIG.
Similarly, F _R and F ₀ are F _R =F _T ·1/800H−D _R F ₀ =1/20H· _FR . Therefore, F ₀ =F _T · 1/20H · 1/00H - D _R ... (5) Calculating the frequency division ratio F _R2 from this formula (5), F _R2 = 1/20H · 1/800H - D _R ... (6) works as a frequency divider. This has a different form from Equation (4), but if we compare the range of values of the frequency division ratio, we get the following. Since the data D _R of latch 30 is 11 bits,
OH≦D _R ≦7FFH, then from equation (4), 1/10000H≦F _R1 ≦1/20H From equation (6), 1/10000H≦F _R2 ≦1/20H, and the range of the dividing ratio value is It's becoming the same.
That is, it is possible to set frequencies in the same range in the circuit shown in FIG. 9 as in the circuit shown in FIG. As described above, the frequency dividing device with variable frequency division ratio can also be formed by a rate multiplier or a programmable divider. In the above embodiments, a circuit configuration that can also perform amplitude control was illustrated, but in reality, as a waveform generation circuit, it is almost sufficient to control the frequency and waveform shape, so amplitude control is not necessarily necessary. . Some of the uses of the above-mentioned circuits of the present invention have already been mentioned, but in addition to sound effect generation circuits,
As a signal generator or a function generator, by incorporating a voice waveform or a similar waveform into the waveform data, it can be used as a pseudo-voice generation circuit, and by incorporating it into the voice waveform or its similar waveform data, By adding a plurality of waveforms to the X and Y axes, the present invention can be applied to various applications such as a circuit for generating pseudo-voices, and a circuit for generating graphics for an X-Y _two- dimensional display.

【table】

【table】

【table】

【table】 [Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the arbitrary waveform generating circuit of the present invention, FIG. 2 is a diagram showing an example of the data structure of the data register and accumulator, and FIG. The illustrated diagram, Figure 4, is
FIG. 1 is a diagram showing a specific circuit of the embodiment, FIGS. 5 and 6 are diagrams illustrating the output waves obtained, and FIG. 7 is a diagram showing the synthesis of three types of waveforms obtained in this embodiment. 8 and 9 are diagrams respectively showing modifications of the frequency dividing device portion of FIG. 1 with a variable frequency division ratio. 1, 2...Multiplexer, 3...Data register, 4...Accumulator, 5...Adder, 6...Latch, 7...
Waveform memory, 8, 9...Latch, 10...D/A converter, 11...Control signal generator, D...Frequency data, C...Augend data, A...Amplitude data, W...
Waveform selection data.

Claims (1)

[Claims] 1. A waveform memory that stores and holds a plurality of different types of waveform data, waveform selection data that selects waveform data in the waveform memory, and frequency division ratio data that sets the read frequency of each selected waveform data. a waveform selection and frequency division ratio setting circuit that separately supplies the frequency division ratio data to the waveform memory, a circuit that converts the output of the waveform memory into an analog signal, and a control signal generation circuit that controls each part. An arbitrary waveform generation circuit that determines a read addressing cycle within selected waveform data of a waveform memory based on both input frequency data and initial phase data. 2. The arbitrary waveform generation circuit according to claim 1, wherein the waveform selection and frequency division ratio setting circuit includes a rate multiplier. 3. The arbitrary waveform generation circuit according to claim 1, wherein the waveform selection and frequency division ratio setting circuit includes a programmable divider. 4. An arbitrary waveform generation circuit according to any one of claims 1, 2, and 3, characterized in that it includes an amplitude setting circuit that sets a desired amplitude during analog conversion.