JPH074009Y2 - Ultrasonic diagnostic equipment - Google Patents

Description

[Detailed Description of the Invention] (a) Industrial field of application The present invention is a super-comprising image display memory that is formed by combining a plurality of memory blocks each configured by a dual port memory for displaying a diagnostic image. The present invention relates to an image display circuit of a sound wave diagnostic apparatus, and more particularly, to an improvement for realizing scroll display.

(B) Conventional technology and its problems Generally, in an ultrasonic diagnostic apparatus, an echo signal based on transmission and reception of ultrasonic waves is stored as image data in an image display memory, and this is read out in synchronization with TV scanning to be read by a TV monitor. Image is displayed on the screen. As a memory for displaying such an image, application of a dual port memory as shown in FIG. 3 can be considered. The basic configuration of this dual port memory is already well known (for example, refer to Japanese Patent Laid-Open No. 60-72020), but if further explanation is given, a RAM section for random access and a SAM section for serial access are provided. Is equipped with
Once the data in the RAM section has been transferred to the SAM section, the RAM section can perform access for drawing with the CRU, etc. while the data in the SAM section is being displayed, which enables high-speed access. Since the P / S conversion is executed in the chip, there is an advantage that the P / S conversion circuit which is conventionally attached externally becomes unnecessary.

Incidentally, in order to configure an image display memory using such a dual port memory, it may be necessary to combine a plurality of dual port memories due to the memory capacity. Even in that case, the image data is
It is desirable to transfer data from the RAM section of each dual-port memory to the SAM section at once during the blanking period of the TV horizontal sync signal in order to write as much time as possible in the section.

On the other hand, when scrolling an M-mode image or the like that displays the movement of the heart wall in time series, the correspondence relationship between the image area and the read address of the SAM portion of each memory block changes from moment to moment. For example, as shown in FIG.
One image display memory has three memory blocks A,
Assuming that each memory block is composed of B and C, in the case of non-scrolling, SA for each memory block A, B, and C.
The start address for reading data from the M section is 0. That is, in this case, since the display is a still image, the image area and each memory block A, B, C
The correspondence of the read start address of the SAM part of is fixed. On the other hand, when scrolling,
The start address for reading the data from the SAM section differs for each memory block A, B, and C. That is, in scroll display, since it is necessary to fetch the latest data while discarding the oldest data and update the data sequentially, the read start point specified as the column address changes with time according to the write address. , The column address of the memory sequentially shifts to the larger one (for example, from left to right).

For example, if the column address currently being written is n, the next column address n + 1 is set as the data read start point x. Therefore, each memory block A, B, C
The read start address of the SAM part of is not fixed and changes sequentially. For example, when reading is started from the second memory block B, the read start address of the second memory block B is the address x (x ≠ 0), but the first and third memory blocks are A,
The read start address of the SAM section in C is address 0.
Therefore, one row of data is transferred from the RAM section to the SAM section at once during the blanking period of the horizontal synchronization signal, and
In order to realize the scrolling function, it is necessary to individually specify the data read start address from the SAM section for each of the memory blocks A, B, and C.

Therefore, in the conventional device, for example, the configuration shown in FIG. 5 has been adopted. In this image display circuit, a dual port memory having a 256-bit SAM section is used as one memory block, and three blocks constitute an image display memory of one plane. Each memory block A, B,
Address bus b1, b2, b3 for reading data from C
Are individually connected.

The operation of this image display circuit will be described. First, from the read address generating section a, RA of each memory block A, B, C is described.
The row address required to transfer one row of data from the M section to the SAM section and the scroll start point x of the image area (the read start point when reading data from the image display memory to perform scroll display and The column addresses necessary for determining the column addresses (see FIG. 4) (the same applies hereinafter) are generated. In this case, the column address is, for example, 768 (= 256
× 3) If it is composed of dots, it starts from address 0 to 76.
It changes in the range of up to 7. The row address is directly input to the row / column address selection units c1, c2, c3, and the column address is input to the address conversion unit d and the timing generator f, respectively. Address conversion unit d
Converts the column address given from the read address generation unit a into a read start address (range 0 to 255) that determines the read start point of the SAM unit of each memory block A, B, and C and outputs it. For example, if the column address of the scroll start point x is address 400, the read start address for the SAM portion of the second memory block B is 400.
-256 = 144. On the other hand, the timing generator f generates each memory block A according to the contents of the column address,
Address switching signals s1, s2, s3 are provided to read start address selectors e1, e2, e3 provided corresponding to B and C, respectively.
Is output. This allows the read start address selection unit
e1, e2, and e3 perform the following operations. That is, if the column address that determines the scroll start point x is 0, 256, 512,
Since the read start address of the SAM section of each memory block A, B, C is 0, in that case, the read start address selection sections e1, e2, e3 are the address switching signals s1, s2, In response to s3, 0 is selected as the read start address of the SAM section. In other cases, the read start address converted by the address conversion unit d is selected for the memory block including the scroll start point x, and address 0 is selected for the remaining memory blocks. For example, in the above example, when the column address that determines the scroll start point x is address 400, the scroll start point x is in the second memory block B, so 144 is selected as the read address of the second memory block B. The address 0 is selected as the read start address of the other first and second memory blocks A and C. Then, each of these read start address selection units e
The read start address selected by 1, e2, e3 is input to the row / column address selection units c1, c2, c3. The row / column address selectors c1, c2, c3 respond to the switching signal R / C provided from the timing generator f to first select the row address from the read address generator a and then the read start address. The read start address from the selection units e1, e2, e3 is selected. In that case, as shown in FIG. 6, a gate circuit is provided during the blanking period of the TV horizontal synchronizing signal.
Since the read enable signal ▲ ▼ is commonly given to g1, g2, and g3 to open the gate, the row address and the read start address are respectively passed through the gate circuits g1, g2, g3 and the address buses b1, b2, b3. It is sent to each of the memory blocks A, B, and C individually. Further, since the timing generator f supplies ▲ ▼ and ▲ ▼ signals to the memory blocks A, B, and C in accordance with the timing, first, each memory block A,
One row of data is transferred from the B and C RAM sections to the SAM section (three memory blocks A, B, and C form one horizontal scan line of data), and then each SAM section is designated by the read start address designation. The starting point of the serial output of is determined. That is, in the above example, the address 0 in one memory block, the address 144 in the second memory block, and the address 0 in the third memory block are read start addresses in each SAM unit. Then, the data set in each SAM section is displayed on the TV.
It is serially output by a shift clock synchronized with scanning. In this example, in the state where the row addresses of the first to third memory blocks A to C are commonly designated, regarding the column address, first, the data corresponding to the column addresses 144 to 255 of the second memory block B is read. Issued, then the third
The data corresponding to the column addresses 0 to 255 of the memory block C is read, the data corresponding to the column addresses 0 to 255 of the first memory block A is read, and finally, the data of the second memory block B is read. The data corresponding to the column addresses 0 to 143 is read.

Therefore, on the display screen of the CRT, the data of the column address 144 at the read start point x (this is the oldest data) is at the left end, and the data of the column address 143 immediately before this column address (this is the latest data). Will be displayed on the right edge.

Then, when the column address that determines the scroll start point x output from the read address generator a changes sequentially,
Along with this, the read start address of each SAM section of each memory block A, B, C also changes, so that scroll display is realized. That is, as described above, on the CRT screen, the data of the column address of the read start point x (this is the oldest data) is at the left end, and the data of the column address immediately before this column address (this is (The latest data) will be displayed at the right end, but each time the column address at the read start point x changes sequentially, the oldest one-column data is rewritten to the latest one-column data. The scroll display is realized by sequentially updating the data.

Thus, in the conventional device, each memory block A, B,
The address buses b1, b2, b3 are independently connected for each C, and the addresses for data transfer of each memory block are simultaneously designated in each memory block unit during the blanking period of the TV horizontal synchronizing signal. Since the number of bus lines as a whole is large, various restrictions are imposed on the pattern design, and many switching elements e1 to e3, c1 to c3, g1 to
g3 etc. were required, and as a result, the circuit configuration became complicated.

The present invention has been made in view of such circumstances, and in the blanking period of the TV horizontal synchronization signal, data is transferred from the RAM section to the SAM section for all memory blocks, and the scroll function is provided. The purpose of this is to reduce the number of address bus lines as much as possible, simplify the circuit configuration, and facilitate pattern design.

(C) Means for Solving the Problems In order to achieve the above-mentioned object, the present invention is one memory composed of a dual port memory having a RAM part for random access and a SAM part for serial access. An ultrasonic diagnostic apparatus including an image display memory formed by combining a plurality of blocks has the following configuration.

That is, in the ultrasonic diagnostic apparatus of the present invention, the memory blocks are commonly connected by a single address bus,
During the blanking period of the TV horizontal sync signal, a transfer permission signal for permitting data transfer from the RAM section to the SAM section of each memory block is sequentially applied to each memory block in a time division manner via a single address bus. Transfer permission signal generating means,
When the data set in the SAM section of each memory block is read in synchronization with the transfer permission signal from the transfer permission signal generating means, the read start address of each memory block is sent to the single address bus side. The reading start address selecting means for sequentially selecting and outputting is included.

(D) Operation In the above configuration, the transfer permission signal generating means time-divisionally transfers the transfer permission signal for permitting data transfer from the RAM section of each memory block to the SAM section during the blanking period of the TV horizontal synchronizing signal. It is sequentially given to each memory block. Then, in synchronization with the transfer permission signal from the transfer permission signal generation means, the read start address selection means selects a read start address for each memory block when reading the data set in the SAM portion of each memory block. . Then, this read start address is individually output to each memory block via the common address bus.
As a result, during the blanking period of the TV horizontal sync signal,
As many data read / transfer cycles as the number of memory blocks are inserted, the RAM section of each memory block receives S
A row address for data transfer to the AM section and a read start address of data from the SAM section are sequentially transmitted to each memory block in a time division manner.

Therefore, the address bus for data read transfer to each memory block is shared.

(E) Embodiment FIG. 1 is a block diagram of essential parts including an image display memory of an image display circuit of an ultrasonic diagnostic apparatus and a data read control system for the memory. In the figure, reference numeral 1 denotes the entire image display circuit, 2 denotes an image display memory, and this image display memory 2 is a dual port memory having a random access RAM section and a serial access SAM section. The memory blocks 2a, 2b, 2c are composed of a plurality (three in this example) of memory blocks. Each memory block 2a, 2b, 2c is commonly connected to one address data bus 4, and this address data bus 4 is connected to one row / column address selection unit 8 via a gate circuit 6. There is. 10 is the first to third memory blocks 2a, 2b,
Row address and scroll start point x of the image area required to transfer one row of data from the RAM section of 2c to the SAM section
(See FIG. 4) The read address generating unit generates a column address (range from 0 to 767) necessary to determine the column address, and 12 indicates the column address given from the read address generating unit 10 in each memory. SA of blocks 2a, 2b, 2c
The address conversion unit converts the read start address (range 0 to 255) that determines the read start point of the M section and outputs the read start address. Further, 14 is a switching signal generator 22 which will be described later.
It is a read start address selecting section which selects and outputs the address output from the address converting section 12 and the address indicating the address 0 of the SAM section of the memory block in response to the switching signal from.

16 is a timing generator that generates various timing control signals for reading data. This timing generator 16 is a memory control signal generator.
18, a transfer permission signal generating means 20 and a switching signal generating section 22 are included. Then, the memory control generation unit 18
▲ ▼ signal to the image display memory 2, ▲
A signal, a row / column address selection signal R / C of the row / column address selection unit 8, and a write enable gate signal ▲ ▼ of the gate circuit 6 are output. Further, the transfer allowance signal generating means 20 is configured so that the RAM section of each memory block 2a, 2b, 2c can be used for SAM during the blanking period of the TV horizontal synchronizing signal.
Transfer permission signal that allows data transfer to
▼, ▲ ▼, ▲ ▼ are sequentially given to each memory block 2a, 2b, 2c in a time-division manner.
A transfer timing signal generator 24 for generating transfer timing signals ▲ ▼, ▲ ▼, ▲ ▼ based on the S signal and the TV horizontal synchronizing signal, and ▲ ▼ based on each transfer timing signal ▲ ▼, ▲ ▼, ▲ ▼ Modify the signal so that each memory block 2a, 2b,
Transfer permission signals ▲ ▼, ▲ ▼, ▲ that allow one row of data to be transferred from the RAM section of 2c to the SAM section
▼ is reproduced, and the signal reproducing section 26 is provided. Further, the switching signal generating section 22 inputs the column address that determines the scroll start point x given from the read address generating section 10, and based on the value of the column address, the transfer timing signal from the transfer timing signal generating section 24.
An address switching signal S synchronized with ▼, ▲ ▼ and ▲ ▼ is output. And the above-mentioned switching signal generator
Each memory block at the time of reading the data set in the SAM unit of each memory block 2a, 2b, 2c in synchronization with the transfer permission signal from the transfer permission signal generation means 20 by the 22 and the read start address selection unit 14. A read start address selecting means 28 for sequentially selecting and outputting individual read start addresses is configured.

Next, the scroll display operation of the image display circuit 1 having the above configuration will be described with reference to the timing chart shown in FIG.

First, from the read address generating section 10 to the SAM section from the RAM section of each memory block 2a, 2b, 2c of the image display memory 2
A row address required to transfer data for a row and a column address required to determine the scroll start point x of the image area are generated. In this case, the column address is, for example, 768 (= 256
× 3) If it is composed of dots, it starts from address 0 to 76.
It changes in the range of up to 7. Then, this row address is given to the row / column address selection unit 8 as it is, and
The column address is the dress converter 12 and the timing generator.
It is input to each of the 16 switching signal generators 22. The address conversion unit 12 converts the column address from the read address generation unit 10 into a read start address (range 0 to 255) that determines the read start point of the SAM unit of each memory block 2a, 2b, 2c and outputs it. To do. For example, when the column address of the scroll start point x is address 400, the read start address for the SAM portion of the second memory block B is 400-256 = 144.

On the other hand, the transfer timing signal generator 24 inputs the RAS signal and the TV horizontal synchronizing signal, and transfers the transfer timing signal based on the RAS signal during the blanking period of the TV horizontal synchronizing signal.
▼, ▲ ▼, ▲ ▼ are generated in a time division manner. Then, these transfer timing signals ▲
▼, ▲ ▼, and ▲ ▼ are given to the RAS signal reproducing section 26 and the switching signal generating section 22, respectively. The RAS signal reproducing unit 26 uses the above transfer timing signals ▲ ▼, ▲
Based on ▼ and ▲, the ▲ ▼ signal from the memory control generator 18 is modified to allow transfer of one row of data from the RAM of each memory block 2a, 2b, 2c to the SAM. Signal ▲ ▼, ▲
Play and output ▼ and ▲ ▼. And
These transfer permission signals ▲ ▼, ▲ ▼, ▲
▼ is sequentially given to each memory block 2a, 2b, 2c individually. Therefore, during the blanking period of the TV horizontal synchronizing signal, the number of data read / transfer cycles corresponding to the number of memory blocks 2a, 2b, 2c is time-divisionally inserted.

In addition, the switching signal generator 22 includes the read address generator 10
A column address for determining the scroll start point x given from is input, and the address switching signal S corresponding to the content of the column address is transmitted to the transfer timing signal ▲ ▼, ▲
Output in synchronization with ▼ and ▲ ▼. That is, if the column address that determines the scroll start point x is other than 0, 256, or 512, the data reading starts from an address in the middle of the SAM section, so the address of the memory block that includes the scroll start point x is the address. A low level address switching signal S for selecting the read start address converted by the conversion unit 12 is output, and a high level address switching signal S for selecting address 0 is output to the remaining memory blocks. Then, the read start address selection unit 14 selects the read start address of address 0 when the address switching signal is at the high level, and selects the address output from the address conversion unit 12 when it is at the low level. Therefore, for example, when the column address that determines the scroll start point x is 400 in the above example, the scroll start point x is included in the second memory block 2b, so that the read start address selection unit 14 transfers the first transfer data. Timing signal ▲
During the output period of ▼, the high level address switching signal S is given to select address 0 that determines the read start point of the first memory block 2a, and during the output period of the next transfer timing signal ▲ ▼, the low level address switching signal is output. S is given to select the address 144 which determines the reading start point of the second memory block 2b, and the high level address switching signal S is given during the output period of the next transfer timing signal ▲ ▼ to give the third memory block 2c Address 0 that determines the read start point is selected.

The read start address selected by the read start address selection unit 14 is given to the row / column address selection unit 8. The row / column address selection unit 8 includes a memory control generation unit 18
In response to the switching signal given from, the row address from the read address generator 10 is first selected, and then the read start address from the read start address selector 14 is selected. In addition, transfer timing signal ▲ ▼,
During the output period of ▲ ▼ and ▲ ▼, the read enable signal ▲ ▼ is output to the gate circuit 6 and the gate is opened. Therefore, each memory block 2a, 2b,
In 2c, a row address for transferring one row of data from the RAM section to the SAM section is commonly given via the address bus 4, and then a column for determining the start of reading data from the SAM section is provided. Addresses are sequentially applied to each memory block in a time division manner.

When a row address is sequentially given to each of the memory blocks 2a, 2b, 2c, the transfer permission signals ▲ ▼, ▲ from the ▲ ▼ signal reproducing section 26 are adjusted accordingly.
When ▼ and ▲ ▼ are added, and when the column address is given, the ▲ ▼ signal is added from the memory control generation unit 18 in accordance with this, so first, by specifying the row address, the RAM unit of each memory block A, B, C 1 row of data is transferred from the SAM section to the SAM section (three memory blocks 2a, 2b, and 2c form one horizontal scanning line of data), and then the read start address (column address) is designated for each SAM section. The starting point for serial output is determined. That is, in the above example, 0 is set in the first memory block.
The address, the address 144 in the second memory block, and the address 0 in the third memory block are designated as the read start address in each SAM unit. Subsequently, the data set in each SAM section is serially output by the shift clock synchronized with the TV scanning. In the above example, in the state where the row addresses of the first to third memory blocks A to C are commonly designated, regarding the column address, first, the data corresponding to the column addresses 144 to 255 of the second memory block 2b is stored. It is read and then the column address 0 to 255 of the third memory block 2c.
Data corresponding to column addresses 0-255 of the first memory block 2a are read, and finally, column address 0 of the second memory block 2b is read.
The data corresponding to ~ 143 is read.

Therefore, on the display screen of the CRT, the data of the column address 144 at the read start point x (this is the oldest data) is at the left end, and the data of the column address 143 immediately before this column address (this is the latest data). Will be displayed on the right edge.

Then, the read start point x designated as the column address
However, since the column address of the image display memory 2 sequentially shifts to the larger one (here, from left to right) in accordance with the change of the write address, the scroll start point x sequentially changes. In the image display memory 2, the oldest one-column data is rewritten to the latest one-column data, and the data is sequentially updated. As a result, scroll display is executed.

Although the image display memory is composed of three memory blocks in this embodiment, it is needless to say that it is not limited to this.

(F) Effect According to the present invention, scrolling is performed using an image display memory that is a combination of a plurality of one memory blocks configured by a dual port memory having a random access RAM unit and a serial access SAM unit. In the image display circuit of the ultrasonic diagnostic equipment that can display,
During the blanking period of the horizontal sync signal, the row address for data transfer from the RAM part of each memory block to the SAM part and the read start address of the data from the SAM part are sequentially sent to each memory block in a time division manner. Because I did
The address bus line can be made common as compared with the conventional one. Therefore, the number of bus lines is reduced and the number of switching elements is reduced, and as a result, excellent effects such as simplification of the circuit configuration and easy pattern design are exhibited.

[Brief description of drawings]

1 and 2 show an embodiment of the present invention, FIG. 1 is a block diagram showing a main part of an image display circuit of an ultrasonic diagnostic apparatus, and FIG. 2 explains a data read / transfer operation of the circuit. 3 is a timing chart for FIG. 3 is an explanatory diagram showing the configuration of the dual port memory, and FIG. 4 is an explanatory diagram showing the correspondence between the image areas and the memory blocks.
5 and 6 show a conventional example, FIG. 5 is a block diagram of an image display circuit of an ultrasonic diagnostic apparatus, and FIG. 6 is a timing chart for explaining a data read / transfer operation of the circuit. 1 ... Image display circuit of ultrasonic diagnostic apparatus, 2 ... Image display memory, 2a, 2b, 2c ... Memory block, 4 ... Address bus, 20 ... Transfer permission signal generating means, 28 ... Start reading Address selection means.

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical display location G06T 1/00 1/60 G09G 1/00 T 9060-5G 1/02 G 9060-5G

Claims (1)

[Scope of utility model registration request] 1. An ultrasonic diagnostic apparatus comprising an image display memory comprising a combination of a plurality of memory blocks each of which is composed of a dual port memory having a random access RAM section and a serial access SAM section. While connecting each of the memory blocks in common by a single address bus, during the blanking period of the TV horizontal sync signal, a transfer permission signal for permitting data transfer from the RAM section of each memory block to the SAM section, Transfer permission signal generation means for sequentially giving to each memory block in a time division manner via a single address bus, and set in the SAM section of each memory block in synchronization with the transfer permission signal from the transfer permission signal generation means. When reading the stored data, the read start address for each memory block is sequentially selected and output to the single address bus side. Ultrasonic diagnostic apparatus characterized by comprising a start address selecting means.