JPS6253086B2 - - Google Patents

Info

Publication number
JPS6253086B2
JPS6253086B2 JP57079083A JP7908382A JPS6253086B2 JP S6253086 B2 JPS6253086 B2 JP S6253086B2 JP 57079083 A JP57079083 A JP 57079083A JP 7908382 A JP7908382 A JP 7908382A JP S6253086 B2 JPS6253086 B2 JP S6253086B2
Authority
JP
Japan
Prior art keywords
gate
command signal
input terminal
circuit
clock signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57079083A
Other languages
English (en)
Japanese (ja)
Other versions
JPS57194636A (en
Inventor
Buronme Irumufuriito
Burunnaa Rainhoruto
Raimaa Haintsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of JPS57194636A publication Critical patent/JPS57194636A/ja
Publication of JPS6253086B2 publication Critical patent/JPS6253086B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Software Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Information Transfer Systems (AREA)
JP57079083A 1981-05-11 1982-05-11 Unitary information reader between asynchronous digital circuits Granted JPS57194636A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19813118621 DE3118621A1 (de) 1981-05-11 1981-05-11 Anordnung zum auslesen eindeutiger informationen aus einem digitalen schaltwerk bei zueinander asynchronen steuersignalen fuer das weiterschalten des schaltwerks und das uebernehmen der informationen

Publications (2)

Publication Number Publication Date
JPS57194636A JPS57194636A (en) 1982-11-30
JPS6253086B2 true JPS6253086B2 (US06486227-20021126-C00005.png) 1987-11-09

Family

ID=6131983

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57079083A Granted JPS57194636A (en) 1981-05-11 1982-05-11 Unitary information reader between asynchronous digital circuits

Country Status (4)

Country Link
US (1) US4511993A (US06486227-20021126-C00005.png)
EP (1) EP0064574B1 (US06486227-20021126-C00005.png)
JP (1) JPS57194636A (US06486227-20021126-C00005.png)
DE (2) DE3118621A1 (US06486227-20021126-C00005.png)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01150094U (US06486227-20021126-C00005.png) * 1988-03-31 1989-10-17

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59140559A (ja) * 1983-01-31 1984-08-11 Sony Corp バツフアレジスタ
JPS62173819A (ja) * 1986-01-27 1987-07-30 Advantest Corp 計数回路
JPS62203420A (ja) * 1986-03-03 1987-09-08 Fanuc Ltd カウンタ回路
DE69032851T2 (de) * 1989-09-29 1999-05-12 Fujitsu Ltd., Kawasaki, Kanagawa Integrierte Schaltung vom Josephson-Typ mit einer Ausgangsschnittstelle, welche die Ausgangsdaten mit reduzierter Taktfrequenz liefern kann
US5517638A (en) * 1993-05-13 1996-05-14 Texas Instruments Incorporated Dynamic clock switching circuitry and method
US6141765A (en) * 1997-05-19 2000-10-31 Gigabus, Inc. Low power, high speed communications bus
DE19755146C2 (de) * 1997-12-11 1999-10-28 Siemens Ag Kodierte Steuersignale zwischen asynchronen Baugruppen
US6981169B2 (en) * 2002-02-26 2005-12-27 Sun Microsystems, Inc. Modified glitch latch for use with power saving dynamic register file structures

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE627529A (US06486227-20021126-C00005.png) * 1962-02-01
US3406378A (en) * 1965-07-14 1968-10-15 Minnesota Mining & Mfg Digital data transfer system
US3411142A (en) * 1965-12-27 1968-11-12 Honeywell Inc Buffer storage system
US3699529A (en) * 1971-01-07 1972-10-17 Rca Corp Communication among computers
US3810103A (en) * 1972-04-03 1974-05-07 Hawlett Packard Co Data transfer control apparatus
US3909791A (en) * 1972-06-28 1975-09-30 Ibm Selectively settable frequency divider
US3916382A (en) * 1972-12-04 1975-10-28 Little Inc A Anticipatory tape rewind system
US4163291A (en) * 1975-10-15 1979-07-31 Tokyo Shibaura Electric Co., Ltd. Input-output control circuit for FIFO memory
SE390672B (sv) * 1975-12-22 1977-01-03 Ericsson Telefon Ab L M Sett att overfora asynkront forenderliga dataord samt anordning for utforande av settet
US4056851A (en) * 1976-09-20 1977-11-01 Rca Corporation Elastic buffer for serial data
SE399773B (sv) * 1977-03-01 1978-02-27 Ellemtel Utvecklings Ab Adress- och avbrottsignalgenerator
US4176400A (en) * 1977-08-10 1979-11-27 Teletype Corporation Buffer storage and control
US4159497A (en) * 1978-02-23 1979-06-26 The United States Of America As Represented By The Secretary Of The Air Force Switch debounce circuit
US4244018A (en) * 1978-05-15 1981-01-06 Gte Automatic Electric Laboratories Incorporated Interlock control of asynchronous data transmission between a host processor and a plurality of microprocessors through a common buffer
US4241398A (en) * 1978-09-29 1980-12-23 United Technologies Corporation Computer network, line protocol system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01150094U (US06486227-20021126-C00005.png) * 1988-03-31 1989-10-17

Also Published As

Publication number Publication date
DE3176734D1 (en) 1988-06-09
EP0064574A2 (de) 1982-11-17
EP0064574A3 (en) 1985-12-04
US4511993A (en) 1985-04-16
JPS57194636A (en) 1982-11-30
DE3118621A1 (de) 1982-11-25
EP0064574B1 (de) 1988-05-04

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