JPS6253007A - Bias circuit - Google Patents

Abstract

PURPOSE:To improve remarkably the leading time after application of power by connecting the 1st capacitor in parallel with the 2nd resistor in a bias circuit where the 1st resistor and the 2nd resistor are connected in series. CONSTITUTION:The 1st resistor 1 whose one terminal is connected to a power supply and the 2nd resistor 2 whose one terminal is connected to ground are connected in series and a DC voltage at the connection point is fed as a DC bias of an electronic circuit 4. In this case, the 1st capacitor 3 is connected in parallel with the 2nd resistor 2 and the 2nd capacitor 5 is connected in parallel with the 1st resistor 1. Then the bias voltage is R2/(R1+R2)XVcc with the condition of C1R1=C2R2 and the bias voltage rises quickly independently of a time (t).

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bias circuit for an electronic circuit, and more particularly to a bias circuit whose power source rises quickly.

[Conventional technology]

Various bias circuits are used in electronic circuits depending on their purpose, but the bias circuits treated here basically generate DC voltage and are limited to those that satisfy the condition of sufficiently low impedance for the AC signals handled. .

As such a bias circuit, a circuit as shown in FIG. 3 has conventionally been common and widely used. In FIG. 3, resistor 1, resistor 2. A bias circuit is configured by the capacitor 3, which divides the power supply voltage Vee at the power supply terminal 6 by a resistor 1 and a resistor 2, and supplies the resulting voltage to the electronic circuit 4 as a DC bias voltage.

Note that the capacitor 3 is used to lower the alternating current impedance seen from the electronic circuit 4 to the bias circuit.

FIG. 4 shows a specific example of the electronic circuit 4 shown in FIG. 3, in which an inverting amplifier using an operational amplifier 41 is used with one power supply. In this case, the bias circuit is
A capacitor 3 is used to supply a DC voltage of Vce, 4 to the positive phase input of the operational amplifier 41, and to provide a sufficiently low impedance to the AC signal being handled.

By the way, as a method of reducing the power consumption of an electronic circuit, a so-called power-down method has been used in the past, in which the supply of power to the circuit is stopped when the circuit is not in use. Therefore, it is desirable to adopt a power-down technique in the cases of FIGS. 3 and 4 as well to reduce the power consumption.

[Problem that the invention seeks to solve]

However, in the conventional bias circuit, if the resistance values of resistors 1 and 2 are RI+R1, and the capacitance of capacitor 3 is C1, then the time (charging time constant) τ for charging capacitor 3 after power is turned on is τ =C1R1Rt/(IJ+R1)...
・・・・・・・・・・・・・・・ (1) is required, which affects the rise time of the entire circuit, and has often caused problems.

The present invention has been made in view of the above-mentioned drawbacks, and it is an object of the present invention to provide a bias circuit in which the rise time from power-down to power-on is significantly shortened.

[Means for solving problems]

The bias circuit of the present invention includes a first
and a second resistor whose one end is connected to the ground are connected in series, and a DC voltage at the connection point is supplied as a DC bias to an electronic circuit. 1 capacitor is connected, and the first capacitor is connected.
This is characterized in that a second capacitor is connected in parallel with the resistor.

[Effect]

In the present invention, a power supply voltage is divided by a first resistor and a second resistor connected in series, and a first capacitor is connected to a second resistor of a bias circuit that supplies the DC voltage as a DC bias of an electronic circuit. By connecting them in parallel and further connecting a second capacitor with a predetermined capacity in parallel with the first resistor, it is possible to significantly shorten the rise time υ of the bias voltage after the power is turned on. can.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing a bias circuit according to an embodiment of the present invention.The difference in FIG. 1 from the conventional circuit shown in FIG. 3 is that the first resistor has one end connected to the power supply terminal 6. 1 and a second resistor 2 whose one end is connected to the ground (GND) are connected in series, and a first capacitor 3 is connected in parallel with this second resistor 2, and in parallel with the first resistor 1. This is because the second capacitor 5 is connected. In addition, in the figure,
The same reference numerals indicate the same items.

According to the configuration of the embodiment described above, the bias voltage Vmtnst after t seconds when the power source of the power source terminal 6 is turned on stepwise at i=o is given by the linear equation.

However, C1 is the capacitance of the capacitor 5, and the electronic circuit 4
The bias input impedance of the bias circuit is assumed to be sufficiently higher than the output impedance of the bias circuit. Therefore, from the above formula (2), C, R, = C R1...
・・・・・・・・・ 0), and the bias voltage V) quickly changes regardless of time t (actually, the power supply impedance is not completely zero, so it differs from equation (4)). I know it will stand up.

FIG. 2 shows the rise 9 characteristics of the conventional bias circuit and the rise 9 characteristics of the bias circuit according to the present invention calculated using specific parameters.

Here, as parameters, R,=R,=10, Ω, C
,=IOμF, and the value of C8 according to the present invention is C,=11μF (""/CIR,= 1.1)
, C,==α9). In Fig. 2, when C1Rt>CtRt (C,=ltμF), the rise characteristic I overshoots, and C,R,(C1R,
In the case of (C, = 9 μF), the rise characteristic ■ undershoots, and in the case of C, R, = C, R, (C, = 10 μF)
It can be seen that the rising characteristic (■) of F) rises instantaneously. Furthermore, even if C,R,=C,R, is not completely satisfied, it can be seen that the rise characteristic (2) of the conventional bias circuit is significantly improved.

〔Effect of the invention〕

As explained above, according to the present invention, the rise time after turning on the power can be significantly improved by simply adding one capacitor to the conventional circuit, which is a great effect.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a bias circuit according to an embodiment of the present invention, FIG. 2 is a characteristic diagram comparing the rise characteristics of the present invention and a conventional bias circuit, and FIG. 3 is a circuit diagram showing a conventional bias circuit. FIG. 4 is a bias circuit diagram showing a specific example of the conventional circuit. 1...Resistor, 2...Resistor, 3...Capacitor, 4...Electronic circuit, 5...Capacitor, 6...
...Power terminal.

Claims (2)

[Claims] (1) A bias in which a first resistor whose one end is connected to a power supply and a second resistor whose one end is connected to the ground are connected in series, and the DC voltage at the connection point is supplied as a DC bias to the electronic circuit. In the circuit, a first capacitor is connected in parallel with the second resistor, and a second capacitor is connected in parallel with the first resistor.
A bias circuit characterized by connecting a capacitor. (2) A patent characterized in that the product of the resistance value of the first resistor and the capacitance of the second capacitor is a constant such that it is equal to the product of the resistance value of the second resistor and the capacitance of the first capacitor. A bias circuit according to claim 1.