JPS6252607A - Program debugging device - Google Patents

Abstract

PURPOSE:To enable an efficient and speedy debugging work by switching an address space in a ROM storing an action program to the same address in an emulation RAM and correcting the contents. CONSTITUTION:When the action program stored in the ROM 6a of a controller 6 is corrected, an object CPU chip 7 is sampled, and a connector 8 is inserted. Next, the contents in the ROM 6a are written at the same address in the emulation RAM of a program debugging device 1. Afterwards, the contents in the emulation RAM are sequentially read out, written in the RAM of a program editing device 12 while an working machine 5 is operated, and are displayed. An operator recognizes the contents at each address on a display screen, and corrects them in necessary. After the corrected contents are temporarily stored in the RAM of the program editing device 12, they are sequentially written in a new ROM through a ROM writer.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is directed to an RO
The present invention relates to a program debugging device for debugging a part of a program stored in an M.

BACKGROUND TECHNOLOGY Conventionally, a control device for a work machine that operates under microcomputer control has a ROM that stores an operation program for performing a predetermined work, and the program in the ROM is The machine is configured to read necessary information such as various operating conditions and work positions from the RAM and to cause the work machine to perform a predetermined work. In this type of control device,
The operation program that operates the central control unit is stored in the ROM.
It is configured to be read and written by the OM writer,
The central control unit is configured to sequentially read out instructions written in this ROM.

Problems to be Solved by the Invention When a ROM writer writes an operating program into and out of the ROM, it is necessary to write the operating program from the beginning even if a part of the operating program is to be modified. After that, the work of actually driving the work equipment and checking the operating program must be repeated many times until a complete operating program is created, which is time consuming and extremely inefficient. There are some drawbacks such as:

Means for Solving the Problems The present invention aims to eliminate the above-mentioned drawbacks by arranging a central control unit with a CPU chip.

An emulation RAM is connected to this central control unit via a first buffer circuit, and this central control unit also includes a plurality of ROs in which programs for driving the work machine are stored.
A connector having the same connector bin as the target CPU chip in the control device having M is arranged via the second buffer circuit.

On the other hand, a program editing device is connected to the central FI control section via an interface. In addition, the first
The buffer circuit, the buffer circuit, and the second buffer circuit are controlled by a control logic section, and this control logic section switches the address of the target ROM and the address of the emulation RAM by switching between the first buffer circuit and the second buffer circuit. ROM and emulation RAM
The CPU is configured to operate according to the following.

Operation When modifying the program of a control device for a work machine having a plurality of ROMs, first remove the CPU chip and insert a connector in its position. Thereafter, the central control unit can write the contents stored in the ROM in the control device to the same address in the emulation RAM according to a command from the program editing device.

On the other hand, when debugging only the contents in the target ROM, specify the control logic section from the editing device in advance and select the first buffer circuit only for that address space, and select the second buffer circuit for addresses other than this address. select.

After that, when the program editing device sends an operation command to the central control section, the second buffer circuit is selected by the control logic section up to the above address, so the contents of the ROM in the control device are sequentially read out, and Then, the contents of the emulation RAM are sequentially read out, sent to the RAM in the program editing device, and displayed.

At the same time, the central control unit is operated according to the contents of the ROM up to the address, and according to the contents of the emulation RAM between the addresses to drive the work machine, and if there is a problem, the displayed contents can be checked. For each work name, check the contents of each address and modify the contents from the program editing device. Therefore, when modifying a program, the contents of each ROM to be modified can be debugged in the emulation RAM, and the program modification can be completed efficiently and quickly.

Thereafter, a ROM writer is connected to the program editing device, and the contents of the emulation RAM in the program editing device can be sequentially written into a new ROM inserted into the ROM writer.

EXAMPLE Hereinafter, an example will be described with reference to the drawings. In FIGS. 1 to 4, 1 is a program debugging device (hereinafter referred to as debugging device), which includes a CPU chip (not shown).
a first central control unit 2 having a first buffer circuit 4;
It has an emulation RAM 3 connected via a. The first central control unit 2 also has a connector 8 having the same connector pins 8a as the target CPU chip 7 in the control device 6, which includes a plurality of ROMs 6a in which programs for driving the work machine 5 are written. connected via the second buffer circuit 4b, and the first buffer circuit 4b.
a and the second buffer circuit 4b are configured to be alternately selected by the controller 1 to the roll logic section 9.

The control logic section 9 includes an external decoder 27 and an internal decoder 28 that specify the address space of each ROM.
The address space corresponding to the target ROM can be selected in response to a command from a program editing device 12, which will be described later. The control logic section 9 also has a latch section 2B connected to the data bus of the first central control section 2, and data applied to the latch section 28 via an external gate circuit 29 and an internal gate circuit 30. The configuration is such that either the output of the external decoder 26 or the internal decoder 27 is cut off, and one of the first buffer circuit 4a and the second buffer circuit 4b is arbitrarily selected. Therefore, this control logic unit 9 calls the same address in the emulation RAM 3 for each address space of an arbitrary ROM, or calls the 7 address of the ROM 6a in the target control device 6, and then calls the first central control unit 2. is configured to operate.

Furthermore, when the connector 8 is connected to a predetermined position of the control device 6, the control device 6 and the first central control section 2 are configured to be in a state where they can communicate.

Furthermore, the debug device 1 includes an ink face 11.
A program editing device 12 is connected via a,
It is configured to send various commands to the first central control unit 2.

The program editing device 12 includes a second central control section 13, a monitor ROM 14, and a RAM 15, as shown in FIG.
, a keyboard 16, a monitor 17, an external storage device 18, and a ROM writer 14. The keyboard 16, monitor 17, external storage device 18, and ROM writer 19 each have an interface llb 11c lid li.
It is connected to the second central control unit 13 via e.

The debugging device 1 also includes a break command generating section 21 connected to the first central control section 2 via a break control section 20. As shown in FIG.
It has a set address section 22 in which two predetermined addresses can be set, a match circuit 23 that checks the match with the read address in the emulation RAM 3, and a subtraction loop counter 24 that operates in response to this match signal. Further, this subtraction loop counter 24 is configured so that it can be set in the same manner as the address from the program editing device 12, and when it is desired to know the operating state of the first central control unit 2 at an arbitrary address, the program editing device 1
2 to set the address and the setting value of the subtraction loop counter 24.

Further, the break command generating section 21 has a manual switch 25, and is configured so that a break command can also be generated by operating this manual switch 25.

In the debugging device described above, a control device 6 in which an operation program for controlling the work machine 5 is written and written in a plurality of ROMs 6a.
First, the target CPU chip 7 in the control device 6 is extracted.

Thereafter, when the connector 8 is inserted, the initial program section 10 is activated, and the first central control section 2 and this control device 6 become ready for communication. From this state, as shown in FIG. 6, a command is sent from the program editing device 12 to the first central control section 2 to write the contents of the ROM 6a in the control device 6 into the same address of the emulation RAM 3. Also,
In advance, a signal is sent from the program editing device 12 to the internal decoder 27 of the controller 1 to the roll logic section 9 to designate an address space corresponding to the target ROM that needs to be debugged.

At the same time, No. 45 is also sent to the latch section 28, and the latch section 28 sends a signal to the internal circuit 30 for this address space, and uses its output to select the first circuit 7/circuit 4a). Second buffer circuit 4b except for addresses
is selected.

After that, from the program editing device 12 to the first central control unit 2
A command is sent to read while driving the working machine 5.

The central control unit 2 drives the work implement 5 according to the contents of the address of the ROM 6a in the target control device c via the second buffer circuit 4b until reaching the set address space of the target ROM. When the address reaches the address space of the target ROM, the contents of the address of the emulation RAM 3 are sequentially read out via the first buffer circuit 4a, and while the working machine 5 is operating, the contents are stored in the RAM 15 of the program editing device 12. It is written and displayed. Therefore, the operator checks the contents of each address using the machine command on the display and, if necessary, makes corrections in machine language using the program editing device 12. After temporarily storing this in the RAM 15 of the program editing device 12, the contents of this RAM 15 are sequentially written into a new ROM (not shown) inserted into this by the ROM writer 19.

As described in detail, the present invention switches the address space of a plurality of ROMs storing operating programs for a control device that drives a work machine to the same address of an emulation RAM for each ROM, and Since the content of the program is sent to the program editing device for modification, when modifying the operating program stored in the ROM, it is only necessary to rewrite the emulation RAM, which eliminates the need to rewrite the ROM many times. Not only is it not necessary to do this, but it is also possible to
Drive the work machine based on the operation program of M and read the target ROM.
When the address space of There must be advantages.

[Brief explanation of the drawing]

1 is a block diagram not showing the configuration of a logic control section according to the present invention; FIG. 2 is a block diagram not showing the configuration of a debugging device according to the present invention; FIG. 3 is an overall explanatory diagram of the present invention; 5 is a block diagram of a program editing device according to the present invention, FIG. 5 is a block diagram of a break control section according to the present invention, and FIG. 6 is a flowchart explaining the present invention in detail. 1 Program debug device, 2 First central control unit, 3 Emulation RAM. 4a first buffer circuit, 4b second buffer circuit, 5 working machine, 6 control device, 6a
ROM, 7 target CPU chip,
8 Connector, 8a Connector pin, 9
Control logic section, 10 Initial program section, 11a llb 11c lld lle interface, 12 Program editing device, 13 Second central control section, 14 Monitor ROM, 1S RAM, 16 Keyboard, 1
7 monitor, 18 external storage device, 1
9 ROM writer, 20 break control section, 21 break command generation section, 22 setting address section, 23 matching circuit, 24
Decreasing counter, 25 Manual switch, 26
External decoder, 27 Internal decoder, 28
Latch section, 29 External gate circuit, 30
internal gate circuit,

Claims (1)

[Claims] A first central control unit 2 having a CPU chip is disposed, and an emulation RAM 3 connected to the first central control unit 2 via a first buffer circuit 4a is disposed, and an operation program for driving the working machine 5 is stored. A target CPU chip 7 in a control device 6 having a plurality of ROMs 6a
In the program debugging device, a connector 8 having the same connector pin 8a as that of
A control logic section 9 for controlling the buffer circuit 4a and the second buffer circuit 4b is arranged, and the control logic section 9 controls the first buffer circuit 4a and the second buffer circuit 4b.
Switch the buffer circuit 4b to arbitrarily switch the address of the target ROM and the address of the emulation RAM 3,
A program debugging device characterized in that the first central control section 2 is operated by a predetermined ROM 6a and the emulation RAM 3.