JPS6251445U - - Google Patents

Info

Publication number
JPS6251445U
JPS6251445U JP14122985U JP14122985U JPS6251445U JP S6251445 U JPS6251445 U JP S6251445U JP 14122985 U JP14122985 U JP 14122985U JP 14122985 U JP14122985 U JP 14122985U JP S6251445 U JPS6251445 U JP S6251445U
Authority
JP
Japan
Prior art keywords
bus
masters
share
utility
scope
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14122985U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14122985U priority Critical patent/JPS6251445U/ja
Publication of JPS6251445U publication Critical patent/JPS6251445U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)

Description

【図面の簡単な説明】
第１図は本考案の実施例のブロツク図、第２図
は制御回路の配線図である。 図において、１はバス、２―１〜２―４はバス
マスタ、３は記憶回路（ＲＡＭ）を示す。

Claims (1)

    【実用新案登録請求の範囲】
  1. バス１と該バス１を共用する複数のバスマスタ
    （２―１〜２―ｎ）と前記各バスマスタからのバ
    ス要求信号に対する優先順位を格納する記憶回路
    ３とで構成したことを特徴とするバス駆動の優先
    回路。
JP14122985U 1985-09-13 1985-09-13 Pending JPS6251445U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14122985U JPS6251445U (ja) 1985-09-13 1985-09-13

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14122985U JPS6251445U (ja) 1985-09-13 1985-09-13

Publications (1)

Publication Number Publication Date
JPS6251445U true JPS6251445U (ja) 1987-03-31

Family

ID=31048822

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14122985U Pending JPS6251445U (ja) 1985-09-13 1985-09-13

Country Status (1)

Country Link
JP (1) JPS6251445U (ja)

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