JPS6251305A - Operational amplifier - Google Patents

Abstract

PURPOSE:To provide a large current drive capability, to reduce the current consumption at no load and to attain an output voltage over a wide range by connecting the 1st and 2nd conduction type MOSFETs in cascade so as to apply each output from the 1st and 2nd differential amplifier sections to each gate of the 1st and 2nd conduction type MOSFETs. CONSTITUTION:The entire circuit consists of two sets of differential amplifier sections 63, 64, an inverting type final stage amplifier section 65 and a bias power supply circuit section 66. When no potential difference exists at input terminal pairs 55, 56, a current flowing to the MOSFETs 51, 52 of a final stage amplifier section 65 depends on a current flowing to the MOSFETs 45, 46 acting like a constant current source, in other words, on only a voltage impressed to a bias voltage terminal 57 and the device size of the MOSFETs 45, 46 or the device size ratio of the MOSFETs 52, 50 or the device size ratio of the MOSFETs 51, 42. That is, in order to save at no signal or nondriving, the current flowing to the MOSFETs 45, 46 is suppressed lower or the device size of the MOSFETs 51 and 52 is decided not to be too much more than that of the MOSFETs 42, 50.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a complementary MOSFET operational amplifier that has a large current drive capability and consumes little current in a no-load state.

[Prior art] Recently, C has been developed which has a simple process and low power consumption.
- Digital e-analog devices using MOS process technology are attracting attention. An example of a conventional complementary MOSFET operational amplifier circuit of this type is shown in FIG.

In Figure 2, 1 to 7 are MOSFETs, 8.8 are positive and negative power supply lines, respectively, 10 and 11 are input terminal pairs supplied with inverting input VrN- and non-inverting input VIN+, respectively, and 12 is a bias voltage supply. terminal, 1
3 is an output terminal for taking out the output VO, and 14 and 15 are a capacitor and a resistor, respectively, for phase compensation.

The operational amplifier having such a configuration as shown in FIG. 1 performs class A operation. That is, in FIG. 1, since the bias voltage applied from the terminal 12 to one MOSFET 7 of the final stage amplifier is a constant voltage, this MSOFET
? forms a constant current circuit. In other words, regardless of whether a load exists and supplies current to the outside, the MOSFET
7 consumes constant current. Moreover, this MOSFET
The maximum drive current due to MOSFET 7 is equal to the constant bias current of MOSFET 7, so the final stage amplifier of this operational amplifier must be designed to supply a bias current equal to the maximum drive current even when there is no load. , therefore, it is disadvantageous in terms of current efficiency.

An example of an operational amplifier configured to overcome these drawbacks is the Roubik G
Article 11A Continuo by (regorian)
Usly Variable 5lope Adap
tive DeltaModulation Code
c System” (IEEE Journal of
d-state C1rcuits, Vol.
5C-18, No, 8゜Dece+l1ber 198
3. 14 (p, eae) of pp. 692-700). This operational amplifier is shown in FIG.
In the figure, 21 to 31 are MOSFETs, 32 and 33 are a pair of input terminals supplied with inputs Vm- and VIN+, respectively, 34 is an output terminal that takes out outputs vo and t, 35 is a terminal that supplies a bias voltage, and 36 and 3
7 are positive and negative power supply lines, respectively, and 38 and 39 are capacitors and resistors for phase compensation, respectively.

MOSFE that constitutes the output stage in the circuit shown in Figure 3
The input voltage difference applied to T 30.31 is the input voltage difference applied to M in the previous stage.
It is determined by OS, FET 27.28, and its value is V
TN ” VTP + A Teal * C: Te V Ding ++
+Vrp is each threshold voltage of MOSFET27, 28, and Δ is MOSFET27.

It is a voltage value determined by the current flowing through 28. In other words, in such an output stage, when there is no load, the MOSFE
T 30.31 is the distance between the input gates
is applied as an input, and Δ after subtracting the threshold voltage is the actual input gate voltage, so only a small amount of current is consumed.

However, when a load exists and current is supplied to this load, the voltage input to the output stage is a constant voltage difference -◆vy
Since the voltage level is shifted upward or downward while maintaining +Δ, one of Mo5FEr'f#&3o,at supplies a large current, but the other MOSFET is cut off. That is, the operational amplifier shown in FIG. 3 operates in a so-called quasi-class B operation.

However, due to the structure of the MOSFET 30.31 that constitutes the output stage buffer section of the circuit shown in FIG.
,,te, p-type MOSFET and N-type MOSFET (
7) Vss -VTP -Δ2 from Voo-VTN-Δ1 with each L3 value voltage as VTP and vTN
limited to. The reason is that the P-type MOSFET 31. which constitutes the output buffer section. In the N-type MOSFET 30, at a high output voltage, that is, at an output voltage near voo, the voltage between the gate and source of the transistor 3 is less than VTN, and it is cut off and does not function.
That is, the output voltage at the output stage is Vss + V
There is a problem that the range is limited from TP +Δ2 to VDD-VTN-Δ1.

Here, Δ1 and Δ2 are given by the following equations (1) and (2).

Here, COx is the gate-bulk capacitance, JJ-n+J
Lp is the carrier mobility, W is the gate width, L is the gate length, and in and ip are the currents flowing through the n-type MOSFET and the p-type MOSFET, respectively.

[Problems to be solved by the invention]: 1. Therefore, an object of the present invention is to provide a circuit configuration of an operational amplifier that has a large current drive capability that could not be achieved with the circuit configuration. □□. , 5
1. The object of the present invention is to provide an operational amplifier that operates over a wide range.

[Means for solving the problem] In order to achieve such an objective, one method of the present invention is to solve the problem.
;The amplifier includes a first differential amplifier section having a first conductivity type MOSFET as an input stage, and a second conductivity type MOSFET.
A second differential amplifying section having an ET as an input stage and having a circuit arrangement complementary to the first differential amplifying section, and MOSFETs of the first and second conductivity types are continuously connected. The present invention is characterized in that it includes an inverting type final stage amplification section in which each output from the first and second differential amplification sections is supplied to each gate of a two-conductivity type MOSFET.

For example, the operational amplifier of the present invention has a first differential amplifier section that uses an N-type MOSFET as an input MOSFET, a first differential amplifier section that uses an N-type MOSFET as an input MOSFET, and a P-type MOSFET that uses an input MOSFET.
Second differential amplifier section with T as input MOSFET, N type M
It has an inverting final stage amplification section consisting of an OSFET and a P-type MOSFET, with the gates of the MOSFETs as input terminals, and each output terminal of the first and second differential amplification sections and the inverting final stage amplification section The input terminals formed by the gates of N-type and P-type MO9FETs are connected to each other.

[Function] According to the present invention, since the final stage amplifier section is an inverting type consisting of an N-type MOSFET and a P-type MOSFET,
The output voltage range can operate over a wide range from positive power supply voltage to negative power supply voltage. And again.

Since the input bias voltage terminal of each MOSFET constituting the final stage amplifier is supplied from the output terminal of the differential amplifier, the no-load consumption current is When an input signal that drives a load is applied to this operational amplifier, the potential difference generated between the input terminal pair causes the output voltages of the two sets of differential amplifiers to shift in the same direction. Since the input MOSFETs are arranged in this manner, only one of the two final stage MOSFETs that receive the output of the differential amplifier section is in the on state, and the other MOSFETs are in the off state, causing the load to be unattended. A large current much larger than the bias current in the signal state can be supplied.

[Example] The present invention will be described in detail below with reference to the drawings.

An embodiment of an operational amplifier according to the present invention is shown in FIG.

In FIG. 1, 41 to 54 are MOSFETs, 55 and 5B are input terminal pairs supplied with inputs VXP4- and VrR+, respectively, 57 is a terminal that supplies a bias voltage, and 58 is an output V. Output terminals for taking out cod, 59 and 8
1 are the output terminals of the differential amplifiers 83 and 84, respectively;
0 and 62 are input terminals of the inverting final stage amplifier B5. Broadly speaking, this circuit consists of two sets of differential amplifier sections 83 and 64, an inverting final stage amplifier section 85, and a bias power supply circuit section 111B. 67 and 68 are positive and negative power supply lines, respectively. 89 and 70 are capacitors for phase compensation, and 71 and 72 are resistors for phase compensation.

Here, MOSFET 43,4? Each gate input terminal is commonly connected to the input terminal 55. MOSFET 4
4.48 gate input terminals are commonly connected to input terminal 5B.

Output terminal 58 of differential amplifier section 63 and inverting final stage amplifier section 8
5, and the output terminal 81 of the differential amplifier section 84 and the other input terminal 62 of the inverting final stage amplifier section 85 are connected.

The operation of the operational amplifier shown in FIG. 1 will be explained below.

First, a case will be described when there is no potential difference between the input terminal pair 55 and 56, that is, when there is no signal or when the output terminal is in an unloaded or undriven state. At this time, input terminal pair 55.
Since there is no potential difference between 58 and 58, >l09 of the final stage amplifier 65
The current flowing through the FET 51.52 is the current flowing through the MOSFET 45.48 which acts as a constant current source, in other words, the voltage applied to the bias voltage terminal 57 and the MOSFET 45.48 act as constant current sources.
SFET 45.4fl device size or MOS
Device size ratio of FET52 and 50 or MOSF
It is determined only by the device size ratio of ET51 and ET42. In other words, in order to save current consumption when there is no signal or no drive, the current flowing through MOSFET 45, 48 must be kept low, or MOSFET 51 and MOSFET
It is sufficient to set the device size of 52 so that it is not too larger than MOSFET 42.50.However, it is not preferable to make these values too small from the point of view of high-speed operation.Therefore, as the value of these device sizes, -Although it cannot be generalized, it should be selected using a value that is almost the same as that of the class A operational amplifier shown in FIG.
Consider the case where one of the ETs 51 and 52 consumes a large current. When such a load is driven, a slight voltage difference is generated between the input terminal pair 55 and 58 compared to when the load is not driven.For example, the terminal 56 has a smaller voltage v1.
Think of a time when an extra amount was added. At this time, the output voltage of the output terminal 58 of the first differential amplifier B3 is α
Only the IVIN will go down. Here, α1 is the voltage amplification factor of the differential amplifier section 63. Further, the output voltage of the output terminal 61 of the second differential amplifier section 64 is α2V compared to the balanced state.
It will fall by m. Here, α2 is the differential amplifier section 8
The voltage amplification factor is 4.

□ Here, connect 0SFE75 to the final stage amplification section.
Since the input voltage applied to the input gate BO of 1 decreases by αIVIN.

Assuming that the input voltage at equilibrium is Vpo, the source-drain current i flowing through the MOSFET 51 when a voltage difference VvN is applied to the input terminal pair is given by the following equation (3).

Here, Cow is the gate-to-bulk capacitance, R is the carrier mobility, Wp is the gate width, t and p are the gate lengths, and VTP is the threshold voltage of the MOSFET.

Regarding the value of Vpo, since the source/drain current is saved when there is no load, ids! As O, Vpo
m VOO-VTP. Therefore, the source voltage of MOSFET 51 when a voltage difference VIN exists between the input terminal pair.
The current flowing between the drains is given by the following equation (4), while the current between the source and drain of MOSFET 52 is given by the following equation (5).

Here, Cax is the gate-to-bulk capacitance, ILn is the carrier mobility, l1ln is the gate width, Ln is the gate length, and vT and I are the threshold voltages of the lll09FET.

Regarding the value of VnO, since the source/drain current when not driven is saved, 'J
n6 ta-+ VT)I. Therefore, input terminal 5
When the voltage difference between 5 and 5B is Vrt4 (1), MOSF
Since the voltage between the MOSFET 52 and the source becomes lower than the threshold voltage VTN, no current flows between the source and the drain, that is, the MOSFET 52 is cut off.

Next, consider a case where the sign of the voltage applied to the input terminal pair 55, 5G is reversed from the above case.

At this time, the output voltage of the output terminal 59 of the first differential amplifier section θ3 increases by αxVm compared to the balanced state. The output voltage of the output terminal 81 of the second differential amplifier section 64 increases by α2VDl compared to the balanced state. Therefore, contrary to the above case, MOSFET 51 is turned off, MOSFET 52 is turned on, and current flows according to the load.

As can be seen from the above, when a small voltage difference exists between the input terminal pair, the input voltage applied to the input terminals 80 and 82 of the final stage amplification section changes depending on the current driving the load. In other words, when consuming a small current, a small αI
When VIN or α2VIN consumes a large current, a large change of αIVm or α2VXN is required at the output terminal of the differential amplifier.
A displacement voltage VXN~ is applied to. Further, the final stage amplifying section 65 is composed of a P-type MOSFET 51 and an N-type MOS
Because of the inverting structure of FET 52, the voltage at output terminal 58 can be driven to the positive or negative supply voltage.

The capacitor 89.70 and the resistor 71.72 in FIG. 1 are internal phase compensation devices, and here they are provided individually corresponding to the two differential amplifier sections 83 and 84. This means that there is one extra pair compared to the case of . This makes it possible to ensure sufficient phase margin, thereby providing a stable operational amplifier. Note that the capacitance 70 and resistance 72 of this phase compensation device as well as the capacitance 8 and resistance 71
The positions of may be interchanged.

The present invention is not limited to the embodiment shown in FIG. 1; for example, in FIG. , and the output terminal 61 of the second differential amplification section 64 and the input terminal 80 of the final stage amplification section 65 may be connected. However, in this case, the signs of the input terminal pair will be interchanged.

In addition, in FIG.
．． An appropriate level thickness may be inserted between 82 and 82.

[Effects of the Invention] As is clear from the above, the present invention minimizes current consumption when not driven, has large current drive capability, and has a wide output voltage range from VSS to VD+. For example, looking at the bias current at the final stage, the class A operational amplifier shown in Figure 2 drives 100 IA with no load.
While it is necessary to consume LA current, the operational amplifier of the present invention only consumes 3 pA of current when not driven.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the operational amplifier of the present invention, and FIG. 2 is a circuit diagram showing an example of a conventional class A operational amplifier. FIG. 3 is a circuit diagram showing an example of a conventional class B operational amplifier. 1-7.21-31, 41-54...MOSFET
. 8.9.3B, 37.87, 138... Positive and negative power supply lines, 10.11, 32.33... Input terminal, 13.3
4...Output terminal, 55.5B...Vrt4-, V! N” input M child,
57...Bias terminal, 58...Vout output terminal, 59.81...Differential amplifier output terminal, flO, 82...
...Invert the final stage amplifier input terminal. 83.84...Differential amplifier section. 65... Inversion type final stage amplifier section, 66... Bias power supply circuit section. Diagram 2 of the circuit diagram

Claims (1)

[Claims] 1) A first differential amplifier section having a first conductivity type MOSFET as an input stage; and a second conductivity type MOSFET as an input stage; A second differential amplification section having a complementary circuit arrangement and first and second conductivity type MOSFETs are continuously connected to each gate of the first and second conductivity type MOSFETs. and an inverting final stage amplifier section to which each output from the differential amplifier section is supplied. 2) In the operational amplifier according to claim 1,
An operational amplifier characterized in that a capacitor and a resistor for phase compensation are connected in series between the output terminals of the first and second differential amplifier sections and the output terminal of the inverting final stage amplifier section.