JPS6251029B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a television signal processing device, and more particularly to a television signal processing device that captures an image of a to-be-characterized object with a television camera and detects the movement of the to-be-characterized object. Conventionally, this type of device used a television camera to capture images1.
Image signals for one field are stored in advance in one field memory, and changes in the font are detected by comparing the image signals stored in the memory with the image signal input from the television camera. All that was required was to newly write the image signal from the television camera into one field memory, read out the written image signal from the memory at the same time, and display it as a still image on the television monitor. Therefore, there is a drawback that it is difficult to tell which part has changed from a still image on a television monitor. In particular, when this television signal processing device is used for monitoring purposes, it is difficult to know what has changed in the screen displayed on the monitor compared to the previous screen unless one is paying close attention, and the person monitoring the In such cases, it is impossible to understand what has changed unless information is transmitted manually. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a television signal processing apparatus that eliminates the drawbacks of the conventional apparatus and that can reliably display changed portions on the screen and accurately grasp the changed portions. When a signal obtained by the television signal processing device according to the present invention is sent as a still image to a long distance through a narrowband transmission path, a boundary signal that reliably indicates a changed area is added to the intermittently sent still image. Therefore, the discrimination on the receiving side is reliable, which is a great advantage. According to the invention, at least one field of memory stores an input television signal, and comparison means for comparing the input television signal with a television signal read from said memory at least one frame before said input television signal. and a television screen change detection circuit that determines that the television screen has changed when the comparison result from the comparison means is larger than a predetermined amount;
a control circuit that causes the memory to perform a writing operation based on the output of the change detection circuit; a change area display signal generating means that generates a change area display signal representing a changed area on the television screen from the output of the change detection circuit; A television signal processing device is obtained, comprising an additional circuit that adds the change area display signal to a signal read from the memory. Next, the present invention will be described in detail with reference to the drawings showing embodiments of the present invention. FIG. 1 shows an embodiment of the present invention, in which an input signal terminal 1, an A/D converter 2,
field memory 3, subtraction circuit 4, change detection circuit 5, control circuit 6, change area display signal generation circuit 7,
It is composed of an additional circuit 8, a D/A converter 9, a clock generation circuit 10, and an output signal terminal 11. In FIG. 1, a signal from a television camera or the like is first input to an input signal terminal 1, A/D converted by an A/D converter 2, and stored in a field memory 3 as one field. A subtraction circuit 4 calculates the difference in each pixel between frames between the signal stored in the field memory 3 and the signal obtained by A/D converting the signal from the input terminal 1. In the change detection circuit 5, the difference signal from the subtraction circuit 4 is divided and calculated for each predetermined area of the screen, and an image change in at least one area is detected. When the changed area is detected, the control circuit 6 instructs the field memory 3 to write the image signal of the next frame. Then, store the new image signal in field memory 3.
When writing to the field, the image signal written in the field memory 3 is read out, the write signal and the read signal are subtracted by the subtraction circuit 4, and the change detection circuit 5 calculates the difference signal, and the image changes. Detect areas. Change area display signal generation circuit 7
Then, the changed area is stored, and a changed area display signal for displaying the changed area, in this embodiment, a boundary signal of the changed area, is generated from the stored changed area.
In the additional circuit 8, the signal from the changing area display signal generator 7 is added to the still image signal read out from the field memory 3, and in the D/A converter 9, the signal from the additional circuit 8 is D/A converted. , and is outputted as an analog signal from the output signal terminal 11 to a television monitor (not shown). The clock generation circuit 10 generates clocks or clocks necessary for the A/D converter 2, change detection circuit 5, change area display signal generation circuit 7, D/A conversion circuit 10, and control circuit 6, respectively, based on the signal from the terminal 1. Give timing. The control circuit 6 generates an address signal for the memory 3, and controls reading from the memory 3, writing to the memory 3 according to the output of the detection circuit 5, and writing to the memory in the changing area display signal generation circuit 7. . FIG. 2 is a block diagram showing the configuration of change detection circuit 5 in FIG. 1. FIG. 3 is a diagram showing an example in which a television screen is divided into predetermined areas. In this example, the screen is divided into M parts in the horizontal direction and N parts in the vertical direction. Here, vertical 1 divided into N
Let the number of lines included in the division be n. In Fig. 2, the difference taken pixel by pixel by the subtraction circuit 4 (Fig. 1) is compared with a certain threshold value in the comparator circuit 12, and when the difference is larger than the threshold value, it is determined that there has been a change in that pixel. be done. The threshold value is supplied from the threshold generation circuit 13 to the comparison circuit 12. The determination result for each pixel from the comparison circuit 12 is sent to a counter 14, and the number of changed pixels is counted every 1/M of one horizontal line. Therefore, a reset pulse having a period of 1/M of the horizontal period (Th) is supplied to the counter 14 from the clock pulse generating circuit 10 (FIG. 1). The output of the counter 14 is added to the other input in an adder circuit 15, and the result is sent to a shift register 16. The shift register 16 is divided into M stages, and stores the number of pixels that has changed for each area divided into M sections in the horizontal direction. shift register 1
The output of No. 6 is fed back to the adding circuit 15 via the switching circuit 17, and is added to the number of changed pixels for each M-divided area in the next line. where n
Across the line of the book, the number of pixels changing is added,
When the number of changed pixels in the nth line is counted, the area shown in Figure 3, ,...,
The number of changed pixels within the range is stored in each stage of the register 16. This area,
The number of changed pixels within , . When addition is performed over n lines, the switching circuit 17 sends the clear data from the clear data generating circuit 20 to the adding circuit 15 according to the timing signal from the clock pulse generating circuit 10 (FIG. 1), and transfers the clear data to the shift register. Clear the contents of 16 and move on to the next area.

【formula】

【formula】

【formula】

Provides for storing the number of pixels changing in [Formula]. Thereafter, changing regions are detected in the same manner. The output of the comparison circuit 19 is sent to the change area display signal generation circuit 7 (FIG. 1). FIG. 4 shows the change area display signal generation circuit 7 (first
In this embodiment, a boundary signal is generated. In the figure, changed area data from a comparator circuit 19 (FIG. 2) is stored in a changed area memory 21 in response to a write command signal from a control circuit 6. The memory 21 uses RAM, and its capacity is m
×525/2n bits. The clock from the clock generator 8 (FIG. 1) is converted to a frequency M times the horizontal scanning frequency f _H by the frequency divider 22, and the clock is sent to the counter 23.
sent to. The counter 23 is a counter with a count value M, and the count value is used as a horizontal address signal for the memory 21. On the other hand, the overflow output of frequency f _H obtained from the counter 23 is sent to the counter 24 to create a vertical address signal, and the latch circuits 25 and 2
Sent to 6. The address signal from the counter 24 changes line by line, but since the capacity of the memory 21 is only the capacity of n lines combined into one, the lower bits of the address signal are abstracted and connected in the memory 21. Further, the address signal from the counter 24 is sent to the address selector 27 as it is, or sent to the data selector 27 after passing through latch circuits 25 and 26 with a delay of two lines. A switching signal of frequency _MfH is applied to the address selector 27 from the frequency divider 22, and one vertical address is selected according to the polarity of the switching signal. Therefore, two types of vertical addresses are stored in memory 2 within one area in the horizontal direction shown in FIG.
1 will be supplied. When the memory 21 is in the write state, only one of these two types of vertical addresses is selected, so that the write signal from the control circuit 6 has a frequency of Mf _H , and this write signal is divided into one line per n line. Supplied in proportion. Here, the write signal from the control circuit 6 is
Mf When the signal does not have an _H component, the frequency divider 22
All you have to do is gate the signal from the write signal with the write signal. In the case of reading from the variable area memory 21, the horizontal address is supplied by the address signal from the counter 26 and from the vertical address selector 27, so that two types of address signals that change within one area are supplied. Further, the memory 21 is constantly being read out. The output from the memory 21 is supplied to one input terminal of the exclusive OR circuit 32 via latch circuits 28 and 29, and at the same time, the output of the memory 21 is supplied to the other input terminal of the exclusive OR circuit 32 via the latch circuit 31. be done. The latch circuit 28 is supplied with the Mf _H latch timing signal from the frequency divider 22, and the latch circuits 29 and 31 are supplied with the Mf _H latch timing signal from the counter 22 via the inverter 30, so the exclusive OR circuit is supplied. In 32, the states of two parts of the same part divided into M equal parts in the horizontal direction, but shifted by two lines in the vertical direction, are compared, and the boundary signal is generated only when the two states are different. Get out. As mentioned above, in reality, the vertical address supplied to the memory 21 does not change line by line, but changes every n lines, and as a result, the output of the exclusive OR circuit 32 shows the state of the area being compared. If they are different, a change area boundary signal is generated across two lines. Next, the generation of vertical changing area boundary signals for each area will be explained. The output of the latch circuit 31 is supplied to one input terminal of the exclusive OR circuit 35, and the output of the latch circuit 31 is simultaneously supplied to the latch circuit 33,
34 and is supplied to the other input terminal of the exclusive OR circuit 35. The latch circuits 33 and 34 receive an A/D video signal from the clock pulse generation circuit 10 (FIG. 1) as a signal that determines the latch timing.
Since a clock signal having a frequency equal to the sampling frequency at the time of the clock is supplied, the exclusive OR circuit 35 compares the states on the lines with a width of two clock cycles, and if the states are different, The change area boundary signal is generated for two clock cycles. This boundary signal appears on the screen as a vertical boundary signal. The outputs of the exclusive OR circuits 32 and 35 are supplied to the boundary line addition circuit 8 via an OR circuit 36. In the addition circuit 8, the changing area boundary signal is added to the signal read out from the memory 3. For example, if the signal from the memory 3 is quantized with 8 bits, the changing area boundary signal is added to the MSB. Alternatively, all 8-bit binary data may be set to "1" or "0" when a change area boundary signal occurs. FIG. 5a shows an example of a changed area among the areas divided as shown in FIG. 3, and FIG. 5b shows an example of a changed area boundary signal display indicating that part. In order to change the width of the border line on the screen, the number of stages of the latches in the latch section corresponding to the latch circuits 25, 26 and 33, 40 shown in FIG. 4 can be changed. As described above, according to the present invention, when the transmitted image signal changes, this is detected and the changed image signal is written into the memory, and a changed area display line indicating the changed area is added to the changed image and displayed. A television signal processing device capable of processing is obtained. The present invention is particularly effective when monitoring intruders and moving objects. Furthermore, when transmitting a still image for monitoring to a distant place using a narrowband transmission path such as a telephone line, it is possible to reliably identify the changed parts by transmitting the still image signal obtained from the television signal processing device of the present invention. It has the advantage of being displayed in

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing one embodiment of the present invention, and FIG.
This figure shows the configuration of the change detection circuit 5 in FIG. 1, FIG. 3 shows the division of the screen when detecting a change area, and FIG. 4 shows the configuration of the change area display signal generation circuit 7 in FIG. FIG. 5a is a diagram showing an example of the changing area, and FIG. 5b is a diagram showing an example of the changing area boundary signal corresponding to FIG. 5a being displayed on the screen. In the figure, 2... ...A/D converter, 3...1 field memory, 4...Subtraction circuit, 5...Change detection circuit, 6...Control circuit, 7...Change area display signal generation circuit, 8...Border line addition Circuit, 9...D/
A conversion circuit, 10... clock generation circuit, 12,
19... Comparison circuit, 13, 18... Value generation circuit,
14...Counter, 15...Addition circuit, 16...
Shift register, 17...Switching circuit, 20...Clear data generation circuit, 21...Change area storage memory, 22...Frequency divider, 23, 24...Counter,
25, 26, 28, 29, 31, 33, 34...
Latch circuit, 27...Address selector, 30...
...Impark, 32, 35...Exclusive OR circuit,
36...OR circuit.

Claims (1)

[Claims] 1 an A/D conversion circuit that converts an input television signal into a digital signal; a memory that stores at least one field of the output of the A/D converter and constantly reads the output of the A/D converter; television signal comparing means for comparing the output read from the memory with a difference of at least one frame; and dividing the television screen into a plurality of areas and determining whether or not there is a screen change in each area based on the output of the comparing means. a change detection circuit for detecting a change, and a display signal generating means for generating a change area display signal surrounding a changed area among a plurality of areas on a television screen based on the output of the change detection circuit;
a control circuit that causes the memory to perform a write operation based on the output of the change detection circuit; an additional circuit that adds the area display signal to the output read from the memory; and a D/D converter that converts the output of the additional circuit into an analog signal. A television signal processing device comprising: an A conversion circuit.