JPS6251008A - Data writing circuit - Google Patents

Abstract

PURPOSE:To prevent the reading unable fault by having comparison of output between a shift register and a timing correction circuit and detecting the malfunction of the timing correction circuit. CONSTITUTION:The output of one of FF 1 constituting a shift register of a record timing correction circuit 106 is always compared with the data output of the circuit 106. Then the result of this comparison is set to an error register by means of the timing with which a clock is set to the circuit 106. In such a constitution, the result of comparison has discordance when the circuit 106 has a malfunction. This enables the detection of a trouble. Each timing of the signal is decided by obtaining the output of an FF of the same timing out of the FF constituting the shift register based on the data output and delaying the timing of the clock to be set to the circuit 106.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a data writing circuit, and in particular, in a magnetic recording device or the like, the pattern peak shift that occurs when reproducing data recorded on a recording medium is The present invention relates to a data write circuit having a means for correcting time.

[Background of the invention]

A data write operation in a conventional magnetic disk device will be explained with reference to FIG. The 1-by-1 write data transferred from the computer 101 is converted into 1-bit serial data by the parallel-to-serial converter 104 of the control device 102, and further converted into code words such as MFM and RLL by the modulation circuit 105. be done. The output of the modulation circuit 105 is corrected for a pattern peak shift that occurs when reading data in a recording timing correction circuit 106, and then sent to a read/write circuit 107 of the magnetic disk device 103. magnetic head 10
8 and is recorded on a recording medium (magnetic disk) 109.

On the other hand, when reading data, the data recorded on the recording medium 109 is read by the magnetic head 108, and the read/V
The input circuit 107 is transferred to the computer device 101 through the readout circuit 110. The recording timing correction circuit 106 consists of a shift register, a pattern identification circuit, a timing correction circuit, etc. In high-density recording, the position of magnetization reversal of data recorded on the recording medium is called pattern peak shift, and the magnetization reversal interval is long during reproduction. Since there is a phenomenon of shifting in the direction, there is a function to shift in the opposite direction to the shifting direction in advance when writing data. Further, the readout circuit 110 has functions of performing phase synchronization, data discrimination, encoder inverse conversion, and serial-parallel conversion to convert data into 1-byte units, but the details thereof are omitted.

In the data write operation, the 1 by 1 unit write data transferred from the computer device 101 has a parity bit, but the parity bits 1 to 1 are removed by the parallel-to-serial converter 104 and are instead sent to the ECC circuit (
(not shown) is generated, and immediately after the data is recorded on the recording medium 109 through the modulation circuit 105 and the recording timing correction circuit 106. Therefore, when reading data, by the read data and FCC byte,
Error detection and limited correction are possible. However, since it does not have a read-after-write function like a magnetic tape device, there is a problem that when writing data, if erroneous data is recorded due to a failure in the circuit where the parity bit is not present, it cannot be detected.

For this reason, conventionally, the shift registers of the parallel-serial converter 104, the modulation circuit 105, and the recording timing correction circuit 106 each count the number of N 1 gH of input data and output data, and after the write operation is completed, the number of N 1 gH is calculated. It was detected whether writing was performed correctly by comparing the coincidence of the numbers of g.However, in the pattern identification circuit and timing correction circuit of the write timing correction circuit 106, for example, Kaisho 5
As shown in No. 9-77607, consideration was not given. Therefore, in the TC constituting each of the circuits, write data may be incorrect due to a failure, and in the case of high-speed data transfer of 3 megabytes/second, timing correction is performed in about 0.5 microseconds to several microseconds. ICs that make up the circuit
If there is a defect in AC characteristics, it is difficult to detect the failure, and it is difficult to perform preventive maintenance by running a diagnostic program or to find the cause of the failure.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to enable detection of malfunction of a data write circuit having means for correcting pattern bit shift.

[Summary of the invention]

The present invention is based on the recording timing correction circuit 10 in FIG.
The data output of the recording timing correction circuit is constantly compared with the output of one of the FFs (flip-flow knob circuits) constituting the shift register No. 6, and the data output of the recording timing correction circuit is
The comparison result is stored in the error register using the clock timing of -. As a result, if the recording timing correction circuit malfunctions, the comparison results will be inconsistent, making it possible to detect a failure. The timing of each of the signals is determined by delaying the clock timing set in the timing correction circuit to compare the outputs of the FFs having the same timing with those of the FFs constituting the shift register, using the data output as a reference. .

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a timing chart 1- for explaining its operation.

In FIG. 1, 1 is a shift register consisting of FFs 12-18, 2 is a pattern identification circuit consisting of AND circuits 21-24, and 3 is a delay circuit 31-33°FFs 36-39. The timing correction circuit includes an OR circuit 41, which corresponds to the recording timing correction circuit 106 in FIG. 8 is an AND circuit 25, a delay circuit 34. This is a write guarantee circuit consisting of a FOR (exclusive OR) circuit 35 and an error register 40.

Data input 5, which is the output of modulation circuit 105 in FIG. 3, is sequentially shifted from FF18 to FF12 of shift register 1 at the timing of clock 4. FF12 and FF
15 is 1″' and FF18 is 1107, the output of the AND circuit 21 is set to the FF 36 at the timing of the clock 6.The clock 6 is the clock Ga, 6b, whose timing is sequentially delayed through the delay circuits 31 to 34. 6c, 6
get d. Each delay value of the delay circuits 31 to 34 is approximately 5 to 30% of the period T of the clocks 4 and 6. clock 6
When a is a normal timing N, the clock 6 is an early timing E, and the clocks 6a and 6C are late timings L and LL, respectively.

When FF15 is ``1'' and FF12 and 18 are ``0''.

The output of the AND circuit 22 is F at the timing of the clock 6a.
It is cented to F37. FF12, 15 and 18 are 17
In the case of 11+, the output of the AND circuit 23 is set to the FF 38 at the timing of the clock 6b. FF15 and 1
When 8 is "BI'" and FF12 is II OII, the output of the AND circuit 24 is set to FF39 at the timing of clock 6C.FF1 set to each FF36 to 39
The output of 5 passes through an OR circuit 41 and becomes a data output.

The write data of the data output cuff is read/written by the read/write circuit 10.
7 and recorded on the recording medium 109.

On the other hand, the data output cuff is FOR along with the output of FF14.
35 and is compared, and passed through the AND circuit 25 at the timing of the clock 6d, which is the output of the delay circuit 34.
It is set in the error register 40. If the contents of the data output and the output of the FF 14 do not match at the timing of the clock 6d, the error output 10, which is the output of the error register 40, is set to 1-. The broken line in FIG. 2 indicates this.

The error output 10 is held until the recent signal 9 is output.

〔Effect of the invention〕

According to the present invention, it is possible to detect errors in write data bits due to malfunctions of the write timing correction circuit when writing data, so that read failures can be prevented. Particularly in magnetic disk drives that do not have a read-after-write function, it is important to ensure that writing is performed accurately. Incidentally, the EC and functions employed in magnetic disk drives are intended for limited correction by detecting errors in read data, and do not guarantee the contents of written data.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of FIG. 1, and FIG. 3 is a schematic block diagram of a data writing system in a magnetic disk device. ■・Shift register, 2...Pattern identification circuit,
3...Timing correction circuit, 8...Write guarantee circuit, 12-18.36-39...Flip-flop, 21-25...AND circuit. 31-34...Delay circuit, 35...Exclusive OR circuit, 40...Error register, 106
Recording timing correction circuit, 109... Recording medium. /-1, Representative Patent Attorney Katsuo Ogawa. Figure 1 Figure 2 Mountain Figure 3

Claims (1)

[Claims] (1) A data writing circuit for a magnetic recording device, etc., which includes a shift register, a pattern identification circuit, and a timing correction circuit to correct pattern peak shifts that occur when reproducing data recorded on a recording medium during data writing. 1. A data write circuit comprising means for comparing outputs of a shift register and a timing correction circuit to detect malfunction of the timing correction circuit.