RU2040050C1 - Device for checking quality of magnetic carrier - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: device has pulse generator, first and second counters, unit of counters, first and second multiplexers, first and second flip-flops, reading unit, unit of modulo two adders, first and second AND gates, first and second delay gates. In addition device has microcontroller, read-only memory unit, third counter, initializing unit, unit for data transfer to system bus, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth, sixteenth flip-flops, second, third, fourth AND gates, first, second NAND gates, first, second, third inverted AND gates, first, second, third fourth fifth sixth seventh eighth ninth, tenth, eleventh OR gates, first second NOR gates, third fourth fifth sixth seventh delay gates, modulo-two adder and LC- circuits. EFFECT: increased functional capabilities. 9 dwg

Description

 The invention relates to computing, and in particular to devices for storing information on a magnetic medium, and can be used to control the surface quality of magnetic disks.

 A device for controlling the quality of a magnetic medium [1] is known, which contains a master oscillator, a frequency divider, recording and reproducing units with the same magnetic heads, a register block, a pulse counter and a register polling unit, which consists of a band-pass filter, an amplitude discriminator for the positive and negative playback signal , zero-transition detector, trigger, inhibit element, amplifier, delay line, D-trigger, pulse counters ny, a signal addition unit and an extremum shaper for each half-wave of the response of the reproduced signal. The disadvantage of this device is the narrow scope and low accuracy of control of the magnetic medium.

 A device for controlling the quality of a magnetic medium [2] is known, which contains a master oscillator, a first assembly circuit and a signal drop counter, as well as an amplifier and amplitude discriminator, a register block installed in each playback unit, the number of registers equal to the number of playback units, the second assembly scheme, and a common trigger , pulse distributor, band-pass filter, zero-transition detector, one-shot, inhibit circuit. The disadvantage of this device is the narrow scope and low accuracy of control of the magnetic medium.

 The closest in technical essence and the achieved result to the proposed solution is a device for controlling the quality of a magnetic medium [3] containing a master oscillator, a frequency divider, recording units connected by the outputs to the recording magnetic heads, a magnetic medium, a transportation mechanism, a register unit, which is composed of shift registers, first pulse counter, register polling unit, first line of delay elements, pre-memory block, consisting of a second group of counters, block a composition containing an amplifier, a bandpass filter, a zero-transition detector, a single-shot, a prohibition element, an amplitude discriminator for a positive playback signal, an amplitude discriminator for a negative playback signal, an addition unit, an impulse generator for the extremum for each half-wave of the response of the reproduced signal, the first trigger, the second D trigger The device also includes a switch, an additional block of registers containing shift registers, a histogram display unit, a selection and group error counting unit, consisting of a group of AND elements and a third group of counters, a second delay line, a scale grid former, and an adder.

 The input of the amplifier is connected to the input of the playback unit, the output of the amplifier through a band-pass filter is connected to the input of the amplitude discriminator by a positive playback signal, and through series-connected zero-transition detector and one-shot to the setup input of the second trigger, the input of the inhibit element and the clock output of the playback unit. The output of the prohibition element is connected to the information output of the playback unit. The input of the pulse shaper at an extremum for each half-wave of the response of the reproduced signal is connected to the inputs of the amplitude discriminator of the signal by a negative playback signal, the outputs of which are connected via the addition block to the “Reset” input of the first trigger. The output of the first trigger is connected to the D-input of the second trigger, the C-input of which is connected to the output of the pulse shaper at an extremum for each half-wave of the response of the reproduced signal. The output of the second trigger is connected to the second input of the inhibit element. In the device, the master oscillator is connected by an output to the first input of the register polling unit, and also through a frequency divider with the inputs of the recording blocks.

 The first output of the register polling unit is connected to the first control input of the register block, while the number of shift registers in the register block corresponds to the number of pulse counters of dropout signals in the pre-memory block, the number of which corresponds to the number of playback blocks. The first control inputs of the shift registers are combined and connected to the first control input of the register block. The second control inputs of the shift registers are combined and connected to the second control input of the register block. The serial code output of the previous shift register is connected to the serial code input of the subsequent shift register. The serial code output of the last shift register is connected to the output of the register block. The inputs of the parallel code of the shift registers are connected to the corresponding bit inputs of the block of registers, which are connected bitwise to the outputs of the corresponding counters of the second group of pulse counters of the signals of falling out of the preliminary memory block. The information inputs of the second group of pulse counters of the dropout signals are bitwise connected to the information outputs of the playback units. The installation inputs of the second group of pulse counters of the dropout signals are combined and connected through the first delay line to the output of the first pulse counter, to the second control input of the register block and the second input of the register polling unit. The input of the first pulse counter is connected to the clock output of one of the playback units.

 The switch is connected by inputs to the information and clock outputs of the playback unit, an additional register block is connected by the control input to the first output of the register reset unit, the histogram display unit is connected by the first input to the output of the first pulse counter, the group error selection and counting unit is connected by the control input to the first delay line. The scaler former is connected by the first input to the output of the second delay line and connected by the second input to one of the outputs of the switch connected to the inputs of the adder. The adder output is connected to the input of the second delay line and to the information inputs of the group error selection and counting unit, connected by other information inputs to the outputs of the scaler former and connected to the outputs of the additional inputs of the register block and other inputs of the histogram display unit. In this case, the output of the register block, the output of the additional register block and other outputs of the register polling unit coincide with the output buses intended for connection with the display and digital printing unit. The inputs of the group of elements and the outputs of the third group of dropout signal counters coincide respectively with the inputs and outputs of the block for counting and selecting errors. The first inputs of the third group of dropout signal counters are connected to the outputs of the group of AND elements, and their second inputs coincide with the control input of the selection and error counting unit. The inputs of the parallel code of the shift registers coincide with the bit inputs of the additional block of registers. The first and second control inputs of the shift registers coincide with the first and second control inputs of the additional block of registers, respectively. The output of the serial code of the previous shift register is connected to the input of the subsequent shift register. The output of the serial code of the last shift register coincides with the output of an additional block of registers.

 The disadvantage of this device is the narrow scope and low accuracy of control of the magnetic medium.

 The narrow scope is due to the fact that the device cannot control the quality of the surface of the magnetic disk, since it does not provide for fixing the moment of the beginning of the control cycle of the rotating carrier and there is no system for generating synchronization sequences for decoding the MFM signals of the magnetic head.

 The low accuracy of control of the magnetic medium is explained by the fact that the device gives an average characteristic of defects of the magnetic medium in the form of a histogram and cannot strictly fix the location of the defective surface area. At the same time, the device does not provide for the possibility of certification of defective sections of the magnetic medium for the purpose of indicating them during further operation. The low accuracy of control is also due to the fact that the result of a single run of the magnetic medium in the device is the result of a single run, which can lead to an erroneous conclusion about the defect of the medium due to the influence of external factors (dust particles entering the gap between the medium and the read head, spark and vibration disturbances, etc. .).

 The problem solved by the invention is that in a device for controlling the quality of a magnetic medium containing a pulse generator, a first and second counters, a counter block, a first and second multiplexer, a first and a second trigger, a playback block, an adder block modulo two, the first element And, the first and second delay elements, and the output of the first counter is connected to the counting input of the second counter and to the first input of the pulse counter block, the output of the pulse generator is connected to the clock input of the first trigger, direct to the course of the first trigger is connected to the second input of the first element And, and the inverse output of the first trigger is connected to its information input, the output of the first element And is the output of the device's write signal, the direct output of the first multiplexer is connected to the input of the first delay element and the first input of the second multiplexer, the output of the first the delay element is connected to the second input of the second multiplexer, the output of the second multiplexer is connected to the input of the second delay element, the output of the second delay element is connected to w to the first input of the first multiplexer, the group of read inputs of the device is connected to the group of inputs of the playback unit, the group of outputs of which is connected to the group of inputs of the summing unit modulo two, the first group of outputs of which is connected to the encoder, the group of outputs of which is connected to the first group of inputs of the data transfer unit to the system a bus, the group of outputs of which are information outputs of the device, an additional microcontroller, a read-only memory unit, a third counter, an initialization unit, data transfer unit to the system bus, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth, sixteenth triggers, second, third, fourth elements And, first, second elements And NOT, first, second, third AND elements with an inverse input, first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh elements OR, first, second element OR-NOT, third, fourth, fifth , sixth, seventh delay elements, modulo two adder, LC-ce kidney, and the output of the device is connected to the first input of the first NAND element, the group of address inputs of the device is connected to the group of address inputs of the read-only memory block, the output of the device is connected to the first input of the second NAND element, the first output of the permanent memory block is connected to the second input of the first AND-NOT element, the fourth output of the read-only memory block is connected to the second input of the second AND-NOT element, the output of the first AND-NOT element is connected to the first input of the first OR element, the output of the second AND-NOT element is connected to the first input of the second of the first OR element, the output of the device is connected to the second input of the first OR element with the second input of the second OR element, the output of the first OR element is connected to the first input of the operation initialization block, the output of the operation initialization block is connected to the third input of the microcontroller, the first output of the LC circuit is connected to the first the input of the microcontroller, the second output of the LC-chain is connected to the second input of the microcontroller, the output of the second OR element is connected to the clock input of the third counter and to the first input of the first element And with inverse by running and with the first input of the second AND element with an inverse input, the first output of the third counter is connected to the second input of the first AND element with an inverse input, the second output of the third counter is connected to the second input of the second AND element with an inverse input and with the third delay element, the output of the first element And with an inverse input connected to the first input of the data transfer unit to the system bus, the output of the second element And with an inverse input connected to the second input of the data transfer unit to the system bus, the output of the third delay element is connected with the first input of the first OR-NOT element, the output of the first OR-NOT element is connected to the reset input of the third trigger and with the reset input of the third counter, the output of the sixteenth trigger is connected to the clock input of the second trigger and to the seventh delay element, the inverse output of the sixteenth trigger is connected to the first input the fifth OR element and to the third input of the data transmission unit to the system bus, the seventh output of the microcontroller is connected to the second input of the fifth OR element, the output of the fifth OR element is connected to the sync input of the third trigger RA, the output of the third trigger is connected to the input of the device, the first output of the microcontroller is connected to the fourth input of the data transfer unit to the system bus, the group of outputs of the microcontroller is connected to the second group of inputs of the data transfer unit to the system bus, the group of outputs of the second counter is connected to the third group of inputs of the transfer unit data to the system bus, the output of the pulse counter block is connected to the clock input of the second trigger and to the first input of the second element AND, the transfer output of the second counter is connected to the clock ohm of the fourth trigger, the inverse output of the fourth trigger is connected to the fourth input of the microcontroller, the direct output of the fourth trigger is connected to the first input of the second element OR NOT, the fourth output of the microcontroller is connected to the information input of the sixth trigger and to the Zap input of the device, the sixth output of the microcontroller is connected to the information input of the seventh trigger and with the input "Read" of the device, the output "Indus" of the device is connected to the clock input of the sixth trigger and the clock input of the seventh trigger, the output of the second reset element and the seventh trigger, the output of the sixth trigger is connected to the first input of the third OR element to the reset input of the first trigger and to the first input of the first AND element, the output of the seventh trigger is connected to the second input of the third OR element and the reset input of the eighth trigger and to the reset input of the ninth trigger and with the reset input of the tenth trigger and with the reset input of the eleventh trigger and the reset input of the fourteenth trigger and with the information input of the fourteenth trigger, the output of the third element OR is connected to the second input of the second element nta And, with the first input of the fourth OR element, with the reset input of the second counter, with the reset input of the fourth trigger, the output of the second AND element is connected to the second input of the pulse counter unit, the output of the first counter is connected to the second input of the fourth, OR element, the output of the fourth OR element connected to the reset input of the first counter, the output of the pulse generator is connected to the clock input of the first counter, the direct output of the fifth trigger is connected to the second input of the first OR-NOT element, with the second input of the second OR-NOT element, with the second input ohm of the operation initialization unit, with the first input of the ninth OR element, with the first input of the tenth OR element, the inverse output of the fifth trigger is connected to the fourth delay element, the output of the fourth delay element is connected to the reset input of the fifth trigger, the generator output is connected to the clock input of the eighth trigger, direct output the eighth trigger is connected to the first output of the first multiplexer, the inverse output of the eighth trigger is connected to the information input of the eighth trigger, the direct output of the ninth trigger is connected to the address during the first multiplexer, the inverse output of the ninth trigger is connected to the first input of the fourth element And, the inverse output of the first multiplexer is connected to the first and second inputs of the third element And, with the second input of the fourth element And and with the clock input of the twelfth trigger and the output of the thirteenth trigger, the output of the third element And connected to the sync input of the tenth trigger, the output of the fourth element And connected to the sync input of the eleventh trigger, the output of the playback unit is connected to the information input ten of the trigger and to the information input of the eleventh trigger, the output of the tenth trigger is connected to the first input of the adder modulo two, the output of the eleventh trigger is connected to the second input of the adder modulo two, the output of the adder modulo two is connected to the address input of the second multiplexer, with the fourteenth trigger input and with the first input of the third AND element with an inverse input and with the first input of the sixth OR element and with the first input of the eighth OR element, the output of the twelfth trigger is connected to the input of the fifth element LCD and with the first input of the seventh OR element, the output of the thirteenth trigger is connected to the input of the sixth delay element and with the second input of the seventh OR element, the output of the fifth delay element is connected to the second input of the sixth OR element, the output of the sixth OR element is connected to the reset input of the twelfth trigger, output the sixth delay element is connected to the second input of the eighth OR element, the output of the eighth OR element is connected to the reset input of the thirteenth trigger, the output of the seventh OR element is connected to the first input of the playback unit and with the second input of the third element And with an inverse input and with a synchro input of the fifteenth trigger, the output of the fourteenth trigger is connected to the reset input of the fifteenth trigger and with the second input of the playback unit, the direct output of the fifteenth trigger is connected to the input of the adder block modulo two, the inverse output of the fifteenth trigger connected to the information input of the fifteenth trigger, the output of the third element And with an inverse input is connected to the clock input of the sixteenth trigger, the output of the seventh delay element is connected to the second input of the ninth OR element, the eighth output of the microcontroller is connected to the second input of the tenth OR element, the output of the ninth element is connected to the reset input of the sixteenth trigger, the output of the tenth OR element is connected to the reset input of the second trigger, the output of the second trigger is connected to the eighth input of the microcontroller, the second group modulo two outputs of the adder block are connected to the input group of the eleventh OR element, the output of the eleventh OR element is connected to the information input of the sixteenth trigger, the second the microcontroller’s stroke is connected to the device’s “Napr” input, the third microcontroller output is connected to the “Step” input of the device, the fourth microcontroller output is connected to the device’s “Zap” input, the fifth microcontroller output is connected to the device’s utz input, the sixth microcontroller output is connected to the “ The synth of the device, the output “Got” of the device is connected to the fifth input of the microcontroller, the output “Set.” Of the device is connected to the sixth input of the microcontroller, the output is “Dor.” "0" device is connected to the seventh input of the microcontroller.

 The essence of the invention consists in expanding the scope by providing the possibility of fixing the moment of the beginning of the control cycle of a rotating carrier; providing synchronization for decoding the MFM signals of the magnetic head by ensuring the recording and subsequent reading of the synchronization zone, as well as the choice of a control code that provides stable adjustment of the phase of the synchronizer.

 The invention also consists in increasing the accuracy of control of the magnetic medium by automatically localizing the defective portion of the magnetic medium by converting its location to the intended address, consisting of the numbers of the zone (sector) and track, followed by fixing these data in the form of a table when an error is detected on the surface of the magnetic medium an 8-fold recording-reading on the surface of a defective track of a given sector is performed, which makes it most likely to draw a conclusion about the quality of the surface awn magnetic media.

 The introduction of a read-only memory block enables decoding of the addresses of input-output ports and allows addressing of input-output ports. The introduction of the microcontroller ensures the autonomy of the device. The introduction of the first counter is used to extract from the current stream of read (written down information the moment of passing the byte of information. The introduction of the second counter is intended to form the number of the current sector.

 The introduction of the third counter is intended to perform the clock counting in order to transfer information to the bus system of 2 bytes in size.

 The introduction of the first trigger serves to form the recorded data into the device during the MFM.

 The introduction of the second trigger is intended to signal the control circuit about a failure during testing and the necessary repeated testing of the track.

 The introduction of the third trigger provides the formation of an interrupt request in the PC; An interrupt request is sent to the PC in case of errors during reading, as well as after testing.

 The introduction of the fourth trigger provides a signal to the microcontroller about the end of the data recorded (read) on the track.

 The introduction of the fifth trigger ensures the start of the initialization unit and the initial reset of the second, third, sixth, seventh, sixteenth triggers. The introduction of the sixth trigger provides the formation of a signal to start recording.

 The introduction of the seventh trigger provides the formation of a read start signal. The introduction of the eighth trigger provides a division of the 5 MHz clock frequency in half in order to provide a synchronization session. The introduction of the ninth trigger serves to provide a synchronization session.

 The introduction of the tenth trigger is intended to be set to a state corresponding to the state on the 4th reading channel. The introduction of the eleventh trigger serves as a reference for the phasing of clock pulses.

 The introduction of the twelfth and thirteenth triggers provides a doubling of the frequency of the phased clock from 2.5 to 5 MHz.

 The introduction of the fourteenth trigger ensures that the triggers in the playback unit are reset to zero at the end of the phasing of the clock pulses. The introduction of the fifteenth trigger provides the formation of a control data signal.

 The introduction of the sixteenth trigger is intended to generate an error signal upon failure. The introduction of the first multiplexer is used to transmit phased clock pulses to the twelfth and thirteenth triggers, and in the case of a mismatch of the phase of the clock pulses with the phase of the data being read, the transmission of clock pulses to the phase shift circuit.

 The introduction of the second multiplexer provides a phase shift of the pulses relative to the phase of the read data. The introduction of the first AND-NOT element provides a command to start testing the device.

 The introduction of the second AND-NOT element provides the transmission of a read command on the system bus, which ensures the transmission by the PC of information about the number of the head, track and sector on which the failure occurred.

 The introduction of the first NAND element with an inverse input provides a control signal for the first buffer register. The introduction of the second AND-NOT element with an inverse input provides the formation of a control signal for the second buffer register.

 The introduction of the third AND-NOT element with an inverse input forms a time interval equal to the duration of the clock pulse.

 The introduction of the first element And provides a record of information during the MFM on all cylinders of the device.

 The introduction of the second element And provides the formation of a control signal for the pulse counter block. The introduction of the third element And provides the transmission of the clock clock to the tenth trigger clock inputs.

 The introduction of the fourth element And provides the transmission of the first clock pulse to the clock input of the eleventh trigger. The introduction of the first OR element is used to transmit a control signal at the beginning of testing to the operation initialization unit.

 The introduction of the second OR element provides the transmission of the control signal for the third counter with the aim of push-pull information transfer to the system bus.

 The introduction of the third OR element provides a reset of the first, second counters and the formation of a signal to reset the counters of the pulse counter block when signals arrive at the beginning of recording or the beginning of reading from the outputs of the sixth and seventh triggers, respectively.

 The introduction of the fourth OR element provides the transmission of the initial reset signal from the output of the third OR element to the R-input of the first counter, as well as setting the conversion factor of the first counter.

 The introduction of the fifth OR element transfers the control signal to the sync input of the third trigger in order to provide an interrupt request in case of a failure on the track or at the end of the test.

 The introduction of the sixth and eighth elements of OR provides a signal with a duration of half the duration of the signal supplied to the synchro inputs of the twelfth and thirteenth triggers.

 The introduction of the seventh element OR provides the transmission of phased clock pulses. The introduction of the ninth OR element transfers the initial reset signal to the sixteenth trigger R input. The introduction of the tenth OR element transfers the second trigger to the R-input.

 The introduction of the eleventh OR element transfers the information signal from the group of outputs of the adder block modulo 2 to the information input of the sixteenth trigger.

 The introduction of the first element OR-NOT provides the control signal of the initial reset from the output of the fifth trigger to the R-input of the third trigger.

 The introduction of the second element OR-NOT provides the control signal of the initial reset from the output of the fifth trigger to the R-input of the sixth and seventh triggers.

 The introduction of the operation initialization block provides the formation of the microcontroller signal at the beginning of the program written in the microcontroller ROM.

 The introduction of a data transmission unit to the system bus provides the formation of two bytes of information about the track number, sector and head. The introduction of a pulse counter block provides a count of the number of bytes in a sector.

 The introduction of the playback unit provides playback of the read data. The introduction of an adder block modulo two provides the addition of control information with information read from the track on each channel.

 The introduction of the encoder provides encoding in binary code the number of the surface on which the error occurred, and the transmission of this information to the data transfer unit to the system bus.

 The introduction of a clock generator provides the formation of a sequence of pulses of a given frequency of 5 MHz. The introduction of an inductive resonator provides a frequency of internal synchronization of the microcontroller equal to 6 MHz. The introduction of an adder modulo two provides tracking of the moment when the phasing of the clock occurs.

 The proposed system meets the criterion of "significant differences" because the systems [1, 2] and the prototype system [3] did not solve the problem of expanding the scope by introducing the sixth and seventh triggers by providing the possibility of fixing the moment of the start of the control cycle, the rotating carrier created physically at the stage of production of the magnetic medium, and providing synchronization for decoding in the MFM the signals of the magnetic head by introducing the first and second multiplexers, the sixth, seventh, eighth, the ninth, tenth, eleventh, twelfth, thirteenth triggers, the third, fourth elements AND, the adder modulo two, sixth, seventh, eighth elements OR, the first, second, fifth, sixth delay elements, improving the accuracy of control of the magnetic medium by automatically localizing the defective area by introducing a data transfer unit into the system bus, a pulse counter unit, a first, second, third counter, a third, fourth trigger, a first, second, third, fourth, fifth OR element, the second AND element, the microcontroller, the first, second AND elements, the first, second AND elements with an inverse input, the first, second OR elements, the third, fourth delay elements, as well as by eightfold write-read when an error is detected on the surface of the magnetic media by introducing a playback unit, adder unit modulo two, fourteenth, fifteenth, sixteenth triggers, ninth, tenth, eleventh elements OR, third element AND with inverse input, seventh delay element .

 Thus, the analysis of the prior art for this type of device shows that at the present time devices are not identical to the claimed execution and solving the same problem.

 Figure 1-9 shows a diagram of the proposed device.

 The Winchester NMD disk-head system control stand contains a permanent memory block 1, a microcontroller 2, the first 3, the second 4, the third 5 counters, the first 6, the second 7, the third 8, the fourth 9, the fifth 10, the sixth 11, the seventh 12, the eighth 13 , ninth 14, tenth 15, eleventh 16, twelfth 17, thirteenth 18, fourteenth 19, fifteenth 20, sixteenth 21 triggers, first 22, second 23 multiplexers, first 24, second 25 NAND elements, first 26, second 27, third 28 AND-NOT elements with an inverse input, first 29, second 30, third 31, fourth 32 elements AND, first 33, second 34, t 35 minutes, fourth 36, fifth 37, sixth 38, seventh 39, eighth 40, the ninth 41, 42 the tenth, eleventh or elements 43, the first 44, second 45 OR-NO elements; initialization unit 46, data transmission unit 47 to the system bus, pulse counter unit 48, playback unit 49, modulo two adders 50, encoder 51, clock pulses generator 52, inductive resonator 53, modulo adder 54, modulo two, first 55, second 56, third 57, fourth 58, fifth 59, sixth 60, seventh 61 delay elements.

 In the device, the output of the first counter 3 is connected to the counting input of the second counter 4 and to the first input of the pulse counter unit 48. The output of the pulse generator 52 is connected to the clock input of the first trigger 6. The direct output of the first trigger 6 is connected to the second input of the first element And 29, and the inverse output of the first trigger 6 is connected to its information input. The output of the sixth trigger 11 is connected to the reset input of the first trigger 6 and to the first input of the first element And 29. The output of the first element And 29 are the outputs of the recording signal of the device. The direct output of the first multiplexer 22 is connected to the input of the first delay element 55 and the first input of the second multiplexer 23. The output of the first delay element 55 is connected to the second input of the second multiplexer 23, the output of the second multiplexer 23 is connected to the input of the second delay element 56. The output of the second delay element 56 is connected to the second input of the first multiplexer 22. The group of readout inputs of the device is connected to the group of inputs of block 49 of playback, the group of readout outputs of the device is connected to the group of inputs of block 50 of adders modulo two, the first group of outputs of which is connected to the group of inputs of the encoder 51 , the group of outputs of the encoder 51 is connected to the unit 47 for transmitting data to the system bus, the group of outputs of which are the information outputs of the device, characterized in that, in order to expand the function optional capabilities by automated search and fixing of defective sections of the magnetic medium, a microcontroller, a permanent memory unit, a third counter, an initialization unit, a data transfer unit to the system bus, a third, fourth, fifth, sixth, seventh, eighth, ninth, are additionally introduced into it; tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth, sixteenth triggers, second, third, fourth elements AND, first, second elements AND NOT, first, second, third elements AND with an inverse input, ne first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh OR elements, first, second OR-NOT element, third, fourth, fifth, sixth, seventh delay elements, modulo adder two, LC -chain, and the output IOW (62) of the device is connected to the first input of the first element AND-NOT 24. The group of address inputs of the device 63 is connected to the group of address inputs of the block 1 of read-only memory. The output IOR 64 of the device is connected to the first input of the second AND-NOT 25 element. The first output of the permanent memory block is connected to the second input of the first AND-NOT 24 element. The fourth output of the permanent memory block 1 is connected to the second input of the second AND-NOT 25 element. AND-NOT element 24 is connected to the first input of the first OR element 33. The output of the second AND-NOT element 25 is connected to the first input of the second OR element 34. The output AEN 65 of the device is connected to the second input of the first OR element 33 and to the second input of the second OR element 34 The output of the first element OR 33 pr and connected to the first input of operation initialization block 46. The output 80 of the initialization unit is connected to the third input 83 of the microcontroller 2. The first output of the LC circuit 53 is connected to the first input 67 of the microcontroller 2. The second output of the LC chain is connected to the second input 82 of the microcontroller 2. The output of the second element OR 34 is connected to the clock input of the third counter 5 and with the first input of the first element And 26 with an inverse input and with the first input of the second element And 27 with an inverse input. The first output of the third counter 5 is connected to the second input of the first element And 26 with an inverse input. The second output of the third counter 5 is connected to the second input of the second element And 27 with an inverse input and to the third delay element 57. The output of the first element And 26 with an inverse input is connected to the first input 69 of the block 47 for transmitting data to the system bus. The output of the second element And 27 with an inverse input is connected to the second input 68 of the unit 47 for transmitting data to the system bus. The output of the third delay element 57 is connected to the first input of the first OR-NOT 44 element. The output of the first OR-NOT 44 element is connected to the reset input of the third trigger 8 and to the reset input of the third counter 5. The output of the sixteenth trigger 21 is connected to the clock input of the second trigger 7, to to the seventh delay element 61, the inverse output of the sixteenth trigger 21 is connected to the input of the fifth OR element 37 and to the third input 70 of the data transmission unit 47 to the system bus, the seventh output 98 of the microcontroller 2 is connected to the second input of the fifth OR element 37. The output of the heel second OR gate 37 is connected to the clock terminal of the third flip-flop 8. The output of the third flip-flop 8 is connected to an input device 66 IRQG. The first output 91 of the microcontroller is connected to the fourth input 71 of the unit 47 for transmitting data to the system bus. The group of outputs 87 of the microcontroller 2 is connected to the second group of inputs 72 of the data transmission unit to the system bus. The group of outputs of the second counter 4 is connected to the third group of inputs 73 of the data transmission unit in the system bus. The output 77 of the pulse counter unit 48 is connected to the clock input of the second counter 4 and to the first input of the second element And 30. The output of the second counter 4 is connected to the clock input of the fourth trigger 9. The inverse output of the fourth trigger 9 is connected to the fourth input 86 of the microcontroller 2. Direct output of the fourth trigger 9 connected to the first input of the second element OR NOT 45. The fourth output 94 of the microcontroller 2 is connected to the information input of the sixth trigger 11, with the input 114 of the device. The sixth output 96 of the microcontroller 2 is connected to the information input of the seventh trigger 12 and to the input 116 of the device. The output 120 of the device is connected to the clock input of the sixth trigger 11 and to the clock input of the seventh trigger 12. The output of the sixth trigger 11 is connected to the first input of the third element OR 35, to the reset input of the first trigger 6 and to the first input of the first element And 29. The output of the seventh trigger 12 is connected to the second input of the third element OR 35 and with the reset input of the eighth trigger 13, with the reset input of the ninth trigger 14 and with the reset input of the tenth trigger 15 and with the reset input of the eleventh trigger 16 and with the reset input of the fourteenth trigger 19 and with information the fourteenth trigger 19. The output of the third element OR 35 is connected to the second input of the second element And 30, with the first input of the fourth element OR 36, with the reset input of the second counter 4, with the reset input of the fourth trigger 9. The output of the second element And 30 is connected to the second input 76 block 48 pulse counter. The output of the first counter 3 is connected to the second input of the fourth element OR 36.

 The output of the fourth OR element 36 is connected to the reset input of the first counter 3. The output of the generator 52 is connected to the clock input of the first counter 3. The direct output of the fifth trigger 10 is connected to the second input of the second OR-NOT 45 element, with the second input of the first OR-NOT 44 element, with the second input 79 of the initialization unit 46, with the first input of the ninth OR element 41, with the first input of the tenth OR element 42. The inverse input of the fifth trigger 10 is connected to the fourth delay element 58. The output of the fourth delay element 58 is connected to the reset input of the fifth trigger 10. The output of the generator 52 is connected to the clock input of the eighth trigger 13. The direct output of the eighth trigger 13 is connected to the first input of the first multiplexer 22 and to the clock input of the ninth trigger 14. The inverse output of the eighth trigger 13 is connected to the information the input of the eighth trigger 13. The direct output of the ninth trigger 14 is connected to the address input of the first multiplexer 22. The inverse output of the ninth trigger 14 is connected to the first input of the fourth element And 32. Inverse output q the first multiplexer 22 is connected to the first and second inputs of the third element And 31 and the second input of the fourth element And 32 and the clock input of the twelfth trigger 17 and the clock input of the thirteenth trigger 18. The output of the third element And 31 is connected to the clock input of the tenth trigger 15. The output of the fourth element And 32 is connected to the clock input of the eleventh trigger 16. The output 122 of the playback unit 49 is connected to the information input of the tenth trigger 15 and to the information input of the eleventh trigger 16. The output of the tenth trigger 15 is connected to the th input of the adder 54 modulo two. The output of the eleventh trigger 16 is connected to the second input of the adder block 54 modulo two, the output of which is connected to the address input of the second multiplexer 23, with the clock input of the fourteenth trigger 19 with the first input of the third element AND 28 with an inverse input, with the first input of the sixth element OR 38, and with the first input of the eighth OR element 40. The output of the twelfth trigger 17 is connected to the input of the fifth delay element 59 and with the first input of the seventh OR element 39. The output of the thirteenth trigger 18 is connected to the input of the sixth delay element 60 and with the second the seventh OR element 39. The output of the fifth delay element 59 is connected to the second input of the sixth OR element 38. The output of the sixth element OR 38 is connected to the reset input of the twelfth trigger 17. The output of the sixth delay element 60 is connected to the second input of the eighth element OR 40. The output of the eighth element OR 40 is connected to the reset input of the thirteenth trigger 18. The output of the eighth element OR 40 is connected to the reset input of the thirteenth trigger 18. The output of the seventh OR 39 is connected to the first input 104 of the playback unit 49, with the second input of the third AND gate 28 with an inverted input and a clock terminal flip-flop 20. The output of the fifteenth fourteenth flip-flop 19 is connected to the reset input of flip-flop 20 and the fifteenth to the second input 105 of the rendering unit 49. The direct output of the fifteenth trigger 20 is connected to the input 110 of the block 50 adders modulo two. The inverse output of the fifteenth trigger 20 is connected to the information input of the fifteenth trigger 20. The output of the third AND element 28 with an inverse input is connected to the clock input of the sixteenth trigger 21. The output of the seventh delay element 61 is connected to the second input of the ninth OR 41. The eighth output 98 of the microcontroller 2 is connected to the second the input of the tenth element OR 42. The output of the ninth element OR 41 is connected to the reset input of the sixteenth trigger 21. The output of the tenth element OR 42 is connected to the reset input of the second trigger 7. The output of the second trigger and 7 is connected to the eighth input 102 of the microcontroller 2. The second output 92 of the microcontroller 2 is connected to the input 112 of the device. The third output 93 of the microcontroller 2 is connected to the input 113 of the device, the fifth output 97 of the microcontroller is connected to the input 115 of the device. The output 117 of the device is connected to the sixth input 100 of the microcontroller 2. The output 119 of the device is connected to the seventh input 102 of the microcontroller 2. The group of outputs 109 of the adder block modulo two is connected to the group of inputs of the eleventh element 43. The output of the eleventh element 43 is connected to the information input of the sixteenth trigger 21.

 Consider the purpose of the elements of the device.

Block 1 of read-only memory provides decoding of the addresses of the input / output ports of the device. Two addresses are allocated from the reserve of I / O port addresses of the device: 3FO ₁₆ for the command port and 3F1 ₁₆ for the data port. The command port is intended for receiving a command to initialize the operation of the control stand from the central processor of the device and is available only by appointment. The data port is designed to transmit data about failures during testing to the central processor of the device. This port is read-only. Ten address inputs of block 1 of read-only memory allow addressing of input-output ports, and four-bit words contain control signals for the corresponding port. Therefore, the cell with the address 3FO ₁₆ must contain 0001 ₂ , and the cell with the address 3F1 ₁₆ 1000 ₂ . The remaining cells of the read-only memory block must contain 000 ₂ . The low-order output of the read-only memory block is connected to the second input of the first AND-NOT 24 element and activates the command port, and the high-order output is connected to the second input of the second AND-NOT element and activates the data port.

Microcontroller 2 is designed to control the operation of the stand and device management. The initial reset of the microcontroller 2 is carried out by a signal from the output of the operation initialization block 46, according to which the address 0000 _{8 is} recorded in the instruction counter of the microcontroller 2, the input / output port registers are set to code 377 ₈ , the PSW register is reset to zero. The first and second outputs of the inductive resonator 53 are connected to the first and second inputs of the microcontroller 2.

As soon as the entire track is recorded / read, the interrupt request signal is sent to the fourth input 86 INT of microcontroller 2 from the inverse output of the fourth trigger 7. In this case, the external interrupt processing routine starts working, which is located in the ROM at the address written to the cells with address 03 ₁₆ . The group of outputs 87 of the microcontroller 2 is used to transmit to the second group of inputs 72 of the block 47 for transmitting data to the system bus of the binary code of the track number. The microcontroller 2 generates control signals: the output 91 of the strobe write data to the external RAM is supplied to the fourth input 71 of the data transfer unit 47 to the system bus, the output 92 when the signal is zero controls the movement of the heads of the HDD to the center, with a unit from the center of the disk, output 93 or zero steps, output 94, the write signal arriving at the device, output 95, the signal for decreasing the write current arrives at the device when the track number exceeds 128, output 96, the read signal arriving at the device, output 97, the reset pulse of trigger 2 for repeating after Nia retest the failed path is supplied to a second input of the tenth OR gate 42, the output 98 trigger setting request pulse 6 interrupt after testing closure device enters the second input of the fifth OR gate 35.

 The input 99 receives the interface control signal “Got” of the device’s readiness, the input 100 the signal “Installation is complete” signaling that the heads are positioned on the rear track, the signal 101 sets the heads on the zero track, input 102 receives a signal from the output of the second trigger 21, signaling additional testing of a bad track.

 The first counter 3 serves to extract from the current stream of read (written) information the moment of passage of the byte of information. Each clock pulse of the generator 52 corresponds to one bit of information read or written to the track, increments the contents of the first counter 3. Before starting to write or read, the first counter 3 is reset to a single signal at the R-input, and also is reset every eight clock cycles due to feedback from the senior the discharge of the counter 3 and the R-input, which provides a conversion factor equal to 8. The change in the state of the counter 3 is provided by applying counting pulses to the counting input from the output of the generator 52. Switching the count tchika occurs on the rising edge of the count pulses. The output of the first counter is connected to the incremental input of the second counter 4, as well as to the first input of the pulse counter unit 48.

 The second counter 4 serves as a sector counter, which contains four information bits, since the number of sectors on track 16. Before recording or reading, the second counter 4 is reset to a single signal at the R input. The counter is switched when a single signal appears from the output 77 of the pulse counter unit 48 and from the output of the first counter 3. When a single signal appears in the transfer category of the trigger 7 of the end of the track, it is set to a single state, which corresponds to the recording (reading) of information from the track. The group of outputs of the second counter 4 is connected to the third group of inputs 73 of the data transmission unit to the system bus. In the event of a failure or error, the binary code of the sector number is recorded in the second buffer register 47 for transmitting data to the system bus.

The third counter 5 is used to control the transfer of two bytes in two cycles to the system bus of the device through the group of outputs 67. Before starting the device, the third counter 5 is reset by a single signal from the output of the fifth trigger 10. When the first command reads the input data rate to the group of inputs 63 of the block code 3F1 ₁₆ is supplied to the read-only memory; unit potential is supplied to line 64 from the output of the IOR device. In this case, the third counter 5 is set to a single state. Switching the counter occurs by the decline of the pulse on the sync inputs. The signal from the output of the least significant bit is fed to the first input 69 of the unit 47 for transmitting data to the system bus. When a second read command is received from the device, the contents of the counter increase by one. The signal from the output of the second category of the counter 5 is fed to the second input 68 of the data transmission unit 47 to the system bus. Through the third delay element 57, this signal resets the third counter 5 to zero.

 The first trigger 6 serves to generate the recorded data in the code using the modified frequency modulation method. During testing, the information written to the disk consists of zeros. The zero sequence is provided by clock pulses coming from the output of the generator 52 with a clock frequency of 5 MHz to the clock input of the first trigger 6, which corresponds to pulses of the zero sequence of the MFM code. Feedback inverse output of the trigger 6 with the information input provides a zero sequence in the serial code. The initial reset of the trigger is carried out according to the recording start signal coming from the output of the sixth trigger 11 to the R-input of the first trigger.

 The second trigger 7 is designed to provide retesting of the track in the event of a failure. The output of the sixteenth trigger 21 is connected to the clock input of the second trigger 7. This ensures that in the case of a single signal at the output of the sixteenth trigger 21, the second trigger 7 is switched to a single state along the signal edge. The appearance of a single potential at the output of the second trigger 7 signals the microcontroller 2 about the need to retest the track on which the failure occurred. The initial reset of the trigger is carried out by the initial reset signal coming from the output of the fifth trigger 10, or by the reset signal of the repeat trigger coming from the output 87 of the microcontroller 2, a single potential is constantly supplied to the information input of the second trigger.

 The third trigger 8 is designed to generate an interrupt request in the PC; When a signal arrives from the output of the sixteenth trigger 21 with a malfunction during testing of the device, the third trigger 8 is set to a single state at the pulse edge, which is fed from the output of the fifth element OR to the sync input of the third trigger 8. From the output of the third trigger 8, the IROG signal is fed to the corresponding input 66 system bus PPEVM. At the same time, the corresponding interrupt must be masked in the interrupt controller of the PCM. Trigger 8 can also be set to a single state by the signal of the end of testing, which is generated at output 98 of microcontroller 2. The initial reset of trigger 8 is carried out by the initial reset signal from the output of the fifth trigger 10 to the R-input of the third trigger 8. During testing, reset the trigger 8 is implemented 500 ns after the transmission of the second byte of information to the system bus. This is achieved by connecting the second output of the third counter 5 through the third delay element 57 to the R-input of the third trigger 6.

 The fourth trigger 9 provides a signal to the microcontroller 2 about the end of the data recorded (read) on the track. When the counter overflows 4 sectors, the fourth trigger is set to a single state. From the direct output, a single signal is supplied to the R-input of the sixth 11 and seventh 12 triggers, and the inverse output is connected to the inverse input 86 of the microcontroller 2. The trigger 9 is reset to zero by the signals of the beginning of recording or the beginning of reading coming from the output of the sixth 11 and seventh 12 triggers respectively on the R-input of the fourth trigger 9.

 The fifth trigger 10 enables the start-up unit 48 to start and the initial reset of the second 7, third 8, sixth 11, seventh 12 and sixteenth 21 triggers. When you click "Finish", the fifth trigger 10 goes into a single state. This is due to connecting the inverse S-input to zero potential. At the trigger output, a single initial reset signal is generated, which is reset 50 ms after you click Finish. This is achieved by connecting the inverse output of the fifth trigger through the fourth delay element 58 to its R input.

 The sixth trigger 11 is designed to generate a signal to start recording. A single output signal is generated when a recording signal is output from the output of the trigger 11 of the microcontroller 2 to the information input of the trigger 11, and the index marker pulse is output from the output of the device 86. The initial state is set by the initial reset signal from the output of the fifth trigger 10 to the R-input of the sixth trigger 11.

 When recording is finished on the track, the sixth trigger is reset.

 The seventh trigger 12 is designed to generate a read start signal. The initial state is set by the initial reset signal from the output of the fifth trigger 10 to the R-input of the seventh trigger 12. Upon completion of reading information from the track with the signal "End of track" from the direct output of the fourth trigger 9, the seventh trigger 12 is reset to the initial zero state. A single signal at the output of the seventh flip-flop 12 is generated when a read signal is received at the information input of the flip-flop 12 from the output 96 of the microcontroller 2, and to the sync input pulse of the index marker from the output 120 of the device.

 The eighth trigger 13 provides division of the clock frequency. The initial state of the trigger 13 is set to zero potential from the output of the seventh trigger 12 to the R-input of the eighth trigger. Upon receipt of a unit potential from the output of the seventh trigger 12 to the R-input of the eighth trigger 13, the latter goes into a ready state. The inverse output of the eighth trigger 13 is connected to its information input, which ensures the division of the 5 MHz clock frequency of the signals from the output of the generator 52 to the trigger input of the trigger 13. Pulses with a frequency of 2.5 MHz are generated at the output of the trigger.

 The ninth trigger 14 serves to provide a synchronization session. The trailing edge of the first pulse at the output of the eighth trigger 13, arriving at the synchro input of the ninth trigger 14, puts it in a single state in which it will remain until the end of the synchronization session. The initial state of the ninth trigger 14 is set to zero potential from the output of the seventh trigger 12 to the R-input of the ninth trigger 14. The single state of the ninth trigger provides the passage of the first pulse from the output of the eighth trigger along the circuit: the first input of the first multiplexer 22, the first delay element 1 ns long, the second the input of which is a multiplexer 23, the second delay element lasting 180 ns. This process will continue cyclically, with each cycle the phase of the pulses will be shifted relative to the phase of the data being read by 2 ns.

 The tenth trigger 15 is intended to be set to a state corresponding to the state on the 4th reading channel. After the clock pulse passes through the first multiplexer 22, the state of the 4th channel is read out by supplying a signal from the inverse output of the multiplexer 22 to the tenth trigger 15 clock input, and to the signal transmission information input from the output of the playback unit 44. The initial state of the tenth trigger 15 is set to zero potential from the output of the seventh trigger 12 to the R-input of the tenth trigger 15.

 The eleventh trigger 16 is used as a reference for phasing clock pulses. The first drop at the output of the first multiplexer 22 will set the trigger 16 in a state that will correspond to the state of the fourth read channel at the moment. After setting the ninth trigger 14 to a single state, the fourth AND element is closed and the state of the eleventh trigger 16 remains unchanged until the end of the synchronization session.

 The twelfth 17th and thirteenth 18 triggers provide a doubling of the frequency of the phased clock. The inverse output of the first multiplexer 22 is connected to the sync inputs of the twelfth 17th and thirteenth 18 triggers. On the front of this pulse, the triggers 17 and 18 go into a single state. In this case, the first pulse is formed at the output of the seventh element OR 39. Thanks to the fifth 59th and sixth 60th delay and feedback elements of the sixth 38th and eighth 40th OR elements, a second pulse is generated 100 ns after the first pulse on the R-input of the triggers. Thus, the pulse repetition rate will be equal to 5 MHz (T = 200 ns).

 The fourteenth trigger 19 provides a reset of the triggers in the block 48 of the playback in the zero state at the end of the formation of the clock pulses. The initial reset of the trigger 19 is carried out by zero potential at the output of the seventh trigger 12, which is supplied to the trigger input of the trigger 19. When a single potential appears, the read at the output of the seventh trigger 12, the fourteenth trigger 19 becomes ready for operation. By the decline of the signal P3L from the output of the adder 54 modulo two trigger 19 goes into a single state and provides reading information on each channel in block 49 playback.

 The fifteenth trigger 20 provides the formation of a signal of control data. The initial state is the zero state, which is provided by the zero potential at the output of the fourteenth trigger 19, supplied to the R-input of the trigger 19. When a single potential appears at the output of the trigger 19, the trigger 20 is ready for operation. By the decline of each clock pulse coming from the output of the seventh OR element to the trigger input of trigger 20, a level identical to the level at the information input is formed at the output. Moreover, the pulse repetition rate of the control data is two times less than the clock frequency, which is provided by feedback of the inverse output of the trigger 20 with the information input.

 The sixteenth trigger 21 is designed to generate an error signal in case of failure. The initial state of the trigger 21, the zero state, is provided by the initial reset signal coming from the output of the fifth trigger 10 through the ninth element OR 41 to the R-input of the trigger 21. Upon the decline of each pulse coming from the output of the seventh element OR 39 through the third element And 28 with the inverse input, the trigger 21 is set to a state corresponding to the potential at the information input. Trigger 21 is set to a single state, which corresponds to an error during testing. Reset is carried out by applying through the seventh delay element 56 and the ninth element OR unit potential to the R-input of the trigger 21.

 The first multiplexer 22 is designed to transmit phased clock pulses to the twelfth 17 and thirteenth 18 triggers, and in case of a mismatch of the phase of the clock pulses with the data reading phase, the transfer of clock pulses to the base shift circuit. The second multiplexer 23 is designed to phase shift the pulses relative to the phase of the read data. From the output of the eighth trigger 13, the signal is supplied to the first input of the first multiplexer 22. Thus, before the ninth trigger 14 is set to a single state, the multiplexer 22 passes the first clock pulse. In this case, a single potential will arrive at the address input, which will connect its second input to the output of the multiplexer 22. Thus, the pulse from the output of the eighth trigger 13 will cycle through the circuit: the output of the multiplexer 22, the first delay element 59, the second input of the second multiplexer 23, the second delay element 60, the second input of the first multiplexer 22. The total delay of the elements of this circuit will be 201 ns, therefore , pulse duration 402 ns. With each cycle, the phase of the pulses will shift relative to the phase of the data being read by 2 ns. Since the data recorded on the track contains 104 bits in the synchrozone, this gives guaranteed phasing of the clock pulses.

 The AND-NOT 24 element is used to transmit a command to start testing the device to the first input of the operation initialization unit 46 from the output 62 of the device.

 The AND-NOT element 25 serves to transmit the IOR read command to the system bus, which provides the PCM with information about the number of the track head and the synthesis where the failure occurred.

 Element And 26 with an inverse input generates a control signal for the first buffer register O block 47 of the data transfer to the system bus.

 The AND element 27 with an inverse input generates a control signal for the second buffer register O of the data transmission unit 47 to the system bus.

 Element And 28 with an inverse input forms a time potential equal to the duration of the clock pulse.

 Element And 29 is used to record information in the MFM code from the output of the first trigger 6 to all heads of the device.

 Element And 30 is used to generate a control signal for block 48 of the pulse counter in order to reset to zero all the counters of block 48 of the pulse counters.

 Element And 31 is used to transmit a clock clock to the tenth 15 sync input from the output of the first multiplexer 22.

 Element And 32 is used to transmit the first clock pulse from the output of the first multiplexer 22 to the clock input of the eleventh 16 of the trigger in order to set the trigger 16 in the state corresponding to the fourth channel.

 The OR element 33 is used to transmit a control signal at the beginning of testing in block 46 of the initialization of work.

 The OR 34 element serves as a control signal for the third counter 5 with the aim of push-pull transmission of information to the system bus.

 The OR 35 element is used to reset the first 3, second 4 counters and generate a signal to reset the counter of unit 48 pulse counters when signals arrive at the beginning of recording or the beginning of reading from the outputs of the sixth 11 and seventh 12 triggers, respectively. The OR 36 element is used to transmit the initial reset signal from the output of the third OR 35 element to the R-input of the first counter 3, and also to set the conversion factor of the first counter 3 equal to 8, by applying a pulse from the output of counter 3 to its R-input.

 The OR element 37 is used to transmit a control signal to the sync input of the third trigger 8 in order to provide an interrupt request in case of a failure on the track or the end of testing.

 OR elements 38 and 40 are used to form a time interval with a duration of two times less than the interval arriving at the synchro inputs of the twelfth 17th and thirteenth 18 triggers.

 The OR element 38 serves for the formation of phased clock signals.

 The OR element 41 is used to transmit the initial reset signal to the R-input of the sixteenth trigger 21 or to reset this trigger to the zero state 50 ns after its transition to the single state.

 The OR element 42 is used to transmit the initial reset signal from the output of the fifth 10 trigger to the R-input of the second trigger 7 or to transfer the control signal of the reset trigger 7 of the repeat to zero by supplying a signal from the output of the microcontroller 2 to the R-input of the second trigger 7.

 The OR element 43 is used to generate an information signal from the group of outputs 109 of the block 50 summation modulo two to the information input of the sixteenth trigger 21.

 The OR-NOT 44 element is used to transmit the control signal of the initial reset from the output of the fifth trigger 10 to the R-input of the third trigger 8, as well as to transmit the signal from the output of the delay element 57 to the R-input of the third trigger 8.

 The OR-NOT element 45 is used to transmit the control signal of the initial reset from the output of the fifth trigger 10 to the R input of the sixth 11 and seventh 12 triggers, as well as to transmit the signal from the output of the fourth trigger 9 to the R inputs of the sixth 11 and seventh 12 triggers to reset them to zero state.

 Block 46 of the initialization of operation is intended to generate a signal to the microcontroller 2 at the beginning of the program recorded in the ROM of the microcontrollers.

 The operation initialization block 46 consists of a trigger 123, a time delay element 124, an OR-NOT 125 element, and is shown in FIG. The initial reset of the trigger 123 is carried out by the initial reset signal from the output of the fifth trigger 10 to the input 79 of the block 46 initialization of work. When a negative pulse occurs at input 78, trigger 123 is set to a single state in which it is 12.5 μs, just such a duration that a pulse is needed for the initial reset and initialization of the operation of microcontroller 2. This pulse comes from the output of block 80 to the input of 83 of microcontroller 2.

 Block 47 data transmission to the system bus is used to generate two bytes of information about the track number, sector and head. Block 47 consists of two registers 126 and 127, two eight-bit bus drivers 128 and 129. A negative pulse from the output of 91 microcontroller 2 to the input 71 of data transfer unit 47 to the system bus connects the group of outputs 87 of the microcontroller 2 to the group of inputs of 72 blocks and records register 127 numbers of the faulty track. When the sixteenth trigger 20 is set to a single state, the group of outputs 111 of the encoder 130 of the second counter 4 is connected to the input group 73 of the data transfer unit 47 in the system bus and the sector number and head number are recorded in the register 126, where the failure occurred. Data is transmitted to the system bus using two bus shapers 128 and 129. When low potential is supplied from the output of the first AND 26 element with an inverse input to input 69 of block 47, information about the number of the faulty track is transmitted to the system bus, then to input 69 block 47 receives a high potential, and the input 68 low, which ensures the transmission of the second byte of information about the number of the head and sector in which the failure occurred. The block diagram of the unit 47 for transmitting data to the system bus is shown in Fig.5.

 Block 48 of the pulse counter is used to count the number of bytes in the sector. It consists, as shown in FIG. 6, of three counters 131-133 and a four-input element And 134. The pulse counter unit 48 has a conversion factor of 609, exactly as many bytes in one sector. At a high potential at input 76, the counters are reset to zero. The conversion factor block 48 of the pulse counter can have only using a combinational circuit. A high potential at the output of the block 77 is possible if there is a high potential at the first output of the counter 133, at the second and third outputs of the counter 132, and at the second output of the counter 131.

 The playback unit 49 serves to reproduce the read data. The playback unit is shown in Fig.7 and contains four formers 135 read data and four flip-flops 136, corresponding to reading on each channel. In each cycle, the shapers form a zero or one potential and, according to the clock pulse from the seventh OR 39 output to the trigger input 136, set them to a state corresponding to the reading information on each read channel.

 Block 50 adders modulo two is used to add control information with information read from the track for each channel. Block 50 is shown in Fig. 8 and consists of four adders 137 modulo two. This asynchronous combinational circuit generates an error signal in the presence of at least one unit potential at the output of the adders 137 and the code of the surface on which the error occurred.

 The encoder 51 is used to encode in binary code the number of the surface on which the error occurred, and transmit this information to the data transfer unit 47 on the system bus.

 The clock generator 52 generates a pulse train of a given frequency equal to 5 MHz.

 The inductive resonator 53 sets the internal synchronization frequency of the microcontroller 2 to 6 MHz, and is connected to the inputs 81 and 82 of the microcontroller 2.

 An adder 54 modulo two is used to track when the phasing of the clock will occur. The output of the adder 54 modulo two is the address input of the second multiplexer 23. The single potential at the output of the adder 54 indicates that phasing has not yet occurred, and ensures that the first delay element 55 is included in the circuit: the first multiplexer 22, the second multiplexer 23, the second delay element 56 . The zero potential at the output of the adder 54 eliminates the first delay element AND 55.

 A device for controlling the quality of a magnetic medium operates as follows.

 The initial state of the channel device circuit elements: the memory cell with the address 3FOH of the permanent memory block 1 should contain 0001V, the memory cell with the address 3F1H of the permanent memory block 1 should contain 1000V, the remaining cells of the permanent memory block 1 should contain 0000V, the first 3, the second 4, the third 5 counters are set to the initial state, all device triggers are set to zero, the program of the device’s work is recorded in the ROM of the microcontroller 2. Initial reset circuits are shown in FIG. 9.

 The initial reset signal from the output of the fifth trigger 10 is supplied to the operation initialization block 46, to the R-input of the interrupt request trigger 8, the triggers for starting recording 11 and the beginning of reading 12, the trigger 21 for the error, the trigger 7 for retry. After that, the device enters the standby state 80 of the submission of the command PCM to start testing. Based on the signal to the inputs 62, 63 of the device, the initialization unit 46 generates an initial reset pulse and initializes the operation of microcontroller 2. Later, the program is stored in the ROM of the microcontroller 2. The drive is ready to test for input 99 to the microcontroller 2, and the signal is analyzed for input 101 of microcontroller 2. If there is no zero track signal, then pulses are sent to outputs 112 and 113 of the device until a pulse appears on input 101 of microcontroller 2 from output 119 of the drive. Upon receipt of a signal from the output 118 of the device to the input 100 of the microcontroller 2, the contents of the counter of the microcontroller 2 are output through the group of outputs 87 of the microcontroller 2 to the input 72 of the data transmission unit 47 to the system bus. If the cylinder number is less than 128, then the high potential is supplied from the output 95 to the input 114 and to the information input of the sixth flip-flop 11, otherwise the high potential of the output 95 is fed to the input 114, to the information input of the sixth flip-flop 112 and from the output 96 to the device input 115. Upon receipt of the pulse of the index marker from the output 120 of the device to the sync input of the sixth trigger 11, the trigger 11 goes into a single state. Clock pulses from the output of the generator 52 are fed to the sync input of the first trigger 6, which generates a zero sequence of rectangular pulses in the MFM code recorded on the track through all recording channels. In this case, the first counter 3 counts the bits in a byte, the counter 4 counts the number of sectors, and the pulse counter unit 48 counts the number of bytes in the sector. Upon receipt of the transfer pulse from the output of the second counter 4, the fourth trigger 9 is set to a single state. A negative pulse from the inverse output of the trigger 9 is fed to the input 86 of the microcontroller 2 and signals the end of the track. The pulse from the direct output of the trigger resets the trigger 11 to zero. In this case, a high potential is reset at the outputs 95, 96 of the microcontroller 2, and at the output 97, a high potential is established, which is fed to the input 116 of the device and to the information input of the seventh trigger 12. When a pulse of the index marker from the output 120 of the device to the trigger input 12 of the last goes into a single state. Thus from the output of the generator 52 clock pulses to the clock input of the eighth trigger 13 receives clock pulses. The trailing edge of the first pulse at the output of the trigger 13 enters the sync input of the trigger 14 and puts it in a single state, in which it will remain until the end of the synchronization session. The output of the trigger 14 is connected to the address input of the first multiplexer 22. The multiplexer has the output level of its first input, if the trigger 14 is set to zero, and the level of the second input, if the trigger 14 is set to a single state. At the first input of multiplexer 22, a signal is output from the output of trigger 13. Prior to setting the ninth trigger 14 to a single state, the first multiplexer 22 passes the first clock pulse. From the inverse output of the first information multiplexer 22 through the third 31 and fourth 32 elements And the pulse is fed to the sync inputs of the tenth 15 and eleventh 16 triggers. The first decay of the pulse at the output of the first multiplexer 22 will set the triggers 15 and 16 to a state corresponding to the state of the fourth read channel at a given time. When the ninth trigger 14 transitions to a single state, the fourth AND element 32 closes and the state of the eleventh trigger 16 remains unchanged until the end of the synchronization session. The first pulse will cycle through the circuit: the direct output of the first multiplexer 22, the time delay element 55, the second input of the second multiplexer 23, the time delay element 56, the second input of the first multiplexer 29. With each clock cycle, the phase of the pulses will shift relative to the data being read. Reading 104 bits of the zeros of the synchrozone gives guaranteed phasing of the sync pulses. On the trailing edge of the clock, trigger 15 in each cycle is set to the state corresponding to the state on the 4th reading channel at a given time. When the contents of the tenth and eleventh triggers 15 and 16 become different, then at the output of the adder 54 modulo two will be set to a logical "0". When a potential of zero appears at the output of the adder 54 modulo two, the time delay element 55 is excluded from the cyclic circuit. Phased clock pulses through the frequency doubling circuit allocated to the twelfth 17th, thirteenth 18th flip-flops, fifth 59th, sixth 50th delay elements, sixth 38th, seventh 39th, eighth 40th OR elements, are input to the playback unit 49 49, trigger 20 of the control data and trigger 21 mistakes. The read information through a group of inputs 138 is fed to the block 49 playback. On the trailing edge of each clock pulse, the triggers 136 are set to a state corresponding to the state at the outputs of the formers 135. Upon receipt of information from the group of outputs 106 of the playback unit 49 to the group of inputs 107 of the adder unit 50 modulo two, the read information is added to the control bit. In the event of a potential of logical "1" at least on one read channel at the output of the eleventh element OR 43, a high potential appears, which transfers the sixteenth trigger 21 to a single state. Upon receipt of a pulse from the output of the sixteenth trigger 21 to the synchro input of the third trigger 8, it goes into a single state and generates a request for interruption in the PCM with high potential from the output of the third trigger 8 to the input 66 of the device.

 Upon receipt of a pulse from the output of the sixteenth trigger 21 to the synchro input of the second trigger 7, it is set to a single state and a high potential is applied to the input 102 of the microcontroller 2, which indicates the need to retest the track. By the permission command to read data at the input 64 of the device, two bytes are transferred from the data transmission unit 47 via the group of outputs 67 to the system bus via the third counter 5, the first 26 and the second 27 AND elements with an inverse input. Upon receipt of high potential from the output of the second trigger 7 to the input 102 of the microcontroller 2, the output 96 gives a high potential at the beginning of repeated testing.

 In this case, the third trigger 6, the second trigger 7, the sixteenth trigger 21 are reset. In the absence of a high potential at the output of the eleventh element OR 43, the microcontroller 2 resets the high potential at the output 96, increases the counter by one and generates a pulse from the output 93 to the input 113 of the device. And then the next track is tested.

If the last track was tested, then the output from the group of outputs 87 of the microcontroller 2 to the group of inputs 72 of the data transmission unit in the system bus 47 of the FF ₁₆ byte occurs and the output 98 of the microcontroller 2 is set to logical "1". By this signal, the third trigger 8 is set to a single state and, due to its high potential, at the output 66, it requests an interrupt in the PCM regarding the end of testing.

Claims (1)

 A device for monitoring the quality of a magnetic medium, comprising a pulse generator, first and second counters, a counter block, a first and second multiplexer, a first and second trigger, a playback block, an adder block modulo two, the first element And, the first and second delay elements, and the output the first counter is connected to the counting input of the second counter and to the first input of the pulse counter block, the output of the pulse generator is connected to the clock input of the first trigger, the direct output of the first trigger is connected to the second input of the first about the And element, and the inverse output of the first trigger is connected to its information input, the output of the first And element is the output of the device recording signal, the direct output of the first multiplexer is connected to the input of the first delay element and the first input of the second multiplexer, the output of the first delay element is connected to the second input of the second multiplexer, the output of the second multiplexer is connected to the input of the second delay element, the output of the second delay element is connected to the second input of the first multiplexer, the group of outputs the washing device is connected to the input block group of the playback unit, the output group of which is connected to the input group of the summing unit modulo two, the first output group of which is connected to the input group of the encoder, the output group of which is connected to the input group of the data transmission unit to the system bus, the output group of which is information inputs of the device, characterized in that a microcontroller, a read-only memory unit, a third counter, an initialization unit, a data transmission unit to the system bus, thiy, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth, sixteenth triggers, second, third, fourth elements AND, two elements AND NOT, three elements AND with inverse input, eleven OR elements, two elements OR NOT, the third, fourth, fifth, sixth, seventh delay elements, an adder modulo two, and an LC chain, with the IOW output of the device connected to the first input of the first element AND NOT, the group of address inputs of the device is connected to group of address inputs of the pos block memory, output "IOR" of the device is connected to the first input of the second element AND NOT, the first output of the permanent memory unit is connected to the second input of the first element AND NOT, the fourth output of the permanent memory unit is connected to the second input of the second element AND NOT, the output of the first element AND NOT connected to the first input of the first OR element, the output of the second AND element is NOT connected to the first input of the second OR element, the output "AEN" of the device is connected to the second input of the first OR element and to the second input of the second OR element, the output of the first OR element it is connected to the first input of the operation initialization unit, the output of which is connected to the third input of the microcontroller, the first output of the LC circuit is connected to the first input of the microcontroller, the second output of the LC chain is connected to the second input of the microcontroller, the output of the second OR element is connected to the clock input of the third counter and to the first input of the first element And with an inverse input and with the first input of the second element And with an inverse input, the first output of the third counter is connected to the second input of the first element And with an inverse input, the second output is third its counter is connected to the second input of the second element And with an inverse input and with a third delay element, the output of the first element And with an inverse input is connected to the first input of the data transfer unit to the system bus, the output of the second element And with an inverse input is connected to the second input of the data transfer unit to the system bus, the output of the third delay element is connected to the first input of the first element OR NOT, the output of the first element OR NOT connected to the reset input of the third trigger and to the reset input of the third counter, the output of the sixteenth trigger An era is connected to the sync input of the second trigger and to the seventh delay element, the inverse output of the sixteenth trigger is connected to the first input of the fifth OR element and to the third input of the data transfer unit to the system bus, the seventh output of the microcontroller is connected to the second input of the fifth OR element, the output of the fifth OR element is connected with the sync input of the third trigger, the output of the third trigger is connected to the IRQG input of the device, the first output of the microcontroller is connected to the fourth input of the data transfer unit to the system bus, group output The microcontroller is connected to the second group of inputs of the data transfer unit to the system bus, the group of outputs of the second counter is connected to the third group of inputs of the data transfer unit to the system bus, the output of the pulse counter unit is connected to the clock input of the second trigger and to the first input of the second element And, the transfer output of the second the counter is connected to the sync input of the fourth trigger, the inverse output of the fourth trigger is connected to the fourth input of the microcontroller, the direct output of the fourth trigger is connected to the first input of the second element OR NOT, the fourth output of the microcontroller is connected to the information input of the sixth trigger and to the input "ZAP" of the device, the sixth output of the microcontroller is connected to the information input of the seventh trigger and to the input "ACCOUNT" of the device, the output "IND" of the device is connected to the sync input of the sixth trigger and by the input of the seventh trigger, the output of the second OR element is NOT connected to the reset input of the sixth trigger and to the reset input of the seventh trigger, the output of the sixth trigger is connected to the first input of the third OR element and to the reset input of the first of the first trigger and to the first input of the first AND element, the output of the seventh trigger is connected to the second input of the third OR element and to the reset input of the eighth trigger, and to the reset input of the ninth trigger, and to the reset input of the tenth trigger, and to the reset input of the eleventh trigger, and with the reset input of the fourteenth trigger, and with the information input of the fourteenth trigger, the output of the third OR element is connected to the second input of the AND element, with the first input of the fourth OR element, with the reset input of the second counter, with the reset input of the fourth trigger , the output of the second AND element is connected to the second input of the pulse counter unit, the output of the first counter is connected to the second input of the fourth OR element, the output of the fourth OR element is connected to the reset input of the first counter, the output of the pulse generator is connected to the clock input of the first counter, the direct output of the fifth trigger is connected to the second input of the first element OR NOT, with the second input of the second element OR NOT, to the second input of the initialization block with the first input of the ninth OR element, with the first input of the tenth OR element, inverse the output of the fifth trigger is connected to the fourth delay element, the output of the fourth delay element is connected to the reset input of the fifth trigger, the output of the generator is connected to the clock input of the eighth trigger, the direct output of the eighth trigger is connected to the first output of the first multiplexer, the inverse output of the eighth trigger is connected to the information input of the eighth trigger and the direct output of the ninth trigger is connected to the address input of the first multiplexer, the inverse output of the ninth trigger is connected to the first input of the fourth element And, in The output of the first multiplexer is connected to the first and second inputs of the third element And, and to the second input of the fourth element And, and to the synchro input of the twelfth trigger, the output of the third element And is connected to the synchro input of the tenth trigger, the output of the fourth element And is connected to clock input of the eleventh trigger, the output of the playback unit is connected to the information input of the tenth trigger and to the information input of the eleventh trigger, the output of the tenth trigger is connected to the first input adder modulo two, the output of the eleventh trigger is connected to the second input of the adder modulo two, the output of the adder modulo two is connected to the address input of the second multiplexer, with the clock input of the fourteenth trigger, and with the first input of the third element And with an inverse input, and with the first input of the sixth OR element, and with the first input of the eighth OR element, the output of the twelfth trigger is connected to the input of the fifth delay element and with the first input of the seventh OR element, the output of the thirteenth trigger is connected to the input of the sixth back element and with the second input of the seventh OR element, the output of the fifth delay element is connected to the second input of the sixth OR element, the output of the sixth OR element is connected to the reset input of the twelfth trigger, the output of the sixth delay element is connected to the second input of the eighth OR element, the output of the eighth OR element is connected to reset input of the thirteenth trigger, the output of the seventh OR element is connected to the first input of the playback unit and to the second input of the third AND element with an inverse input and with the sync input of the fifteenth trigger, the output of four of the fifteenth trigger is connected to the reset input of the fifteenth trigger and with the second input of the playback unit, the direct output of the fifteenth trigger is connected to the input of the adder unit modulo two, the inverse output of the fifteenth trigger is connected to the information input of the fifteenth trigger, the output of the third element And with the inverse input is connected to the sixteenth input of the sixteenth trigger trigger, the output of the seventh delay element is connected to the second input of the ninth element OR, the eighth output of the microcontroller is connected to the second input of the tenth element LI, the output of the ninth OR element is connected to the reset input of the sixteenth trigger, the output of the tenth OR element is connected to the reset input of the second trigger, the output of the second trigger is connected to the eighth input of the microcontroller, the second group of outputs of the adder block modulo two is connected to the group of inputs of the eleventh OR, the second the output of the microcontroller is connected to the input "NAP" of the device, the third output of the microcontroller is connected to the input "STEP" of the device, the fourth output of the microcontroller is connected to the input "ZAP" of the device, the fifth output the microcontroller is connected to the input "UTZ" of the device, the sixth output of the microcontroller is connected to the input "SYNT" of the device, the output "GOT" of the device is connected to the fifth input of the microcontroller, the output is "SET. ZAV "device is connected to the sixth input of the microcontroller, the output" DOR "O" of the device is connected to the seventh input of the microcontroller, the output of the eleventh element OR is connected to the information input of the sixteenth trigger.

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