JPS6249631A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To eradicate the generation of crystal defects by gettering the back of a silicon substrate which contains oxygen before a heat treatment process. CONSTITUTION:A semiconductor device is obtained by the heat treatment of a semiconductor substrate. In this case, a silicon substrate which contains oxygen of 5X10<15>-1X10<18> atoms/cm<3> is used for the semiconductor substrate. The back of the silicon substrate is gettered before the heat treatment process. As a result, such as the characteristics of noise, a leakage current, switching, the storage characteristics of a CCD, etc., are drastically improved.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor devices such as diodes, transistors, and ICs.

CZ crystals and FZ crystals are used in the manufacture of conventional semiconductor devices. These crystals are used depending on the type of device and the manufacturing conditions of the device, but each has its own advantages and disadvantages.

That is, first of all, let's talk about CZ crystal.This crystal usually has 1
01' order, for example 1.3 x 10+s atoms/c
It contains a high concentration of oxygen, about rt+3. However, if a CZ crystal is heat-treated at, for example, 1100°C, the oxygen solid solubility limit (4X10" atoms/cI113
), the excess oxygen grows as precipitates, and stacking faults and dislocations also occur from these precipitates. These crystal defects deteriorate the characteristics of the device. However, oxygen and its precipitates have a so-called pinning effect, which prevents dislocations generated at the periphery or back surface of the semiconductor wafer from propagating to the entire wafer.

On the other hand, since FZ crystals usually contain less than 5X1015 atoms/crn'' (e.g. 10'' atoms/cm3) of oxygen, the above-mentioned defects seen in CZ crystals do not occur, but the oxygen concentration is low. Therefore, there is no pinning effect as described above, and many dislocations from the periphery and back surface of the wafer propagate during heat treatment.

The present invention aims to correct the above-mentioned drawbacks.In a method for manufacturing a semiconductor device including a heat treatment step for a semiconductor substrate, a silicon substrate containing 5 x 1015 to 1X10''atoms/cm' of oxygen is provided. The present invention relates to a method for manufacturing a semiconductor device, characterized in that the silicon substrate is used as the semiconductor substrate, and the back surface gettering is performed on the silicon substrate before the heat treatment step. It is possible to provide a device that eliminates the occurrence of crystal defects while taking advantage of the respective advantages of C2 crystal and FZ crystal.

In general, when it comes to the crystal used as a starting material in the manufacture of semiconductor devices, there has been a debate on whether to use a CZ crystal or an FZ crystal, but the essential point, the oxygen concentration, has not been considered at all. There wasn't. The present invention fundamentally changes the conventional way of thinking, and increases the oxygen concentration in the crystal to 5 x 10" atoms 7 cm3 or more, which is higher than the conventional FZ crystal, to provide the above-mentioned pinning effect, which was not present in the FZ crystal, and to increase the oxygen concentration. The growth of precipitates due to excess oxygen was prevented by setting lXl0'' atoms to 7 cm3 or less, which is below the solid solubility limit at various heat treatment temperatures.

The oxygen solid solubility limit at each heat treatment temperature is as shown below.

Heat treatment temperature ('C) Oxygen solid solubility limit (atoms/cm') 9
00 1xlO” 1000 2xlO” 1100 4X10” 1200 7X10” 1300 1.3X10” 1400 1.8X10” In the present invention, the lower limit of oxygen concentration is 5X10” atoms/cm”
If the upper limit is IX 10"atoms/cm' or less, it is possible to take advantage of the advantages of the FZ crystal while eliminating its drawbacks, and also to maintain the oxygen concentration below the solid solubility limit of the order of 10" at the maximum temperature. below 1300-1400℃,
Particularly in the practical temperature range of 1000-1200°C, oxygen precipitation can be effectively prevented and defects can be eliminated.

As a result, noise characteristics, leakage current characteristics, switching characteristics, storage characteristics of CCD, etc. can be dramatically improved.

Next, the present invention will be explained in detail with reference to examples.

First, as a sample, the oxygen concentration is ~1018 atoms/cm3
(CZ wafer: sample 1), ~1017 atoms/cmj (
Sample 2), ~10'6 atoms/cm3 (Sample 3), ~10
15 atoms/cm" (FZ wafer: sample 4). Four types of silicon wafers were used.
10'7 or ~10'6 atoms/cm' wafer (Sample 2
and 3) is called an EZ wafer, and is obtained by growing an ingot obtained by the CZ method into a crystal by the FZ method while reducing the oxygen concentration, and cutting out the grown crystal.

Then, in order to evaluate device characteristics, MOS capacitors (not shown) are manufactured using each of the above wafers. Each wafer is P type with 20 to 30 Ω-cffl and no dislocation, and the surface is mechanically and chemically polished.
The back side is finished by chemical etching. To manufacture a MOS capacitor, the following steps are performed.

0 process: A process of thermal oxidation at high temperature for a long time (1100°C, drying 02, 100 hours) so that the influence of oxygen is noticeable on the generation of crystal defects and the characteristics of the device.

P step: In order to clarify whether crystal defects can be removed by back surface gettering, phosphorus is attached to the back surface at 1100° C. for 1 hour and diffused.

M process: A process of forming an electrode on a thermal oxide film to fabricate a normal MO3 element.

Three types of MOS capacitors were manufactured by combining these steps in three ways. That is, (1), when manufacturing in the order of O process - P process - M process (hereinafter referred to as 0 → PM process). (2), P process → 0 process → M process (hereinafter P → O → M
It is called a process. ) when manufacturing in the following order. (3) There were three cases where manufacturing was performed in the order of 0 process-M process (hereinafter referred to as 0-M process).

First, a voltage is applied stepwise to the MOS capacitor to generate a depletion layer under the electrode, and the recovery time t f (gen
generation time) was measured. Thereafter, in order to observe defects generated during the process, the electrodes and oxide film on the front surface and the damaged layer due to diffusion existing on the back surface were removed. The distribution of dislocation within the wafer was observed by X-ray traverse topography, and the distribution of defects in the depth direction from the surface was observed by X-ray sexist topography. In addition, small crystal defects that could not be imaged by X-ray topography were observed using an optical microscope after the wafer surface was subjected to corrosion treatment to expose the defects.

(a) Propagation of dislocation from the periphery of the wafer The propagation range of dislocation is clearly related to the oxygen concentration, and almost no propagation was observed in sample 1 with an oxygen concentration of ~10 ra atoms/cII13. In addition, the dislocation density in the entire wafer is sample 1 (oxygen concentration ~ 1Q18 atoms/cm3) - sample 2 (oxygen concentration ~ 101
7 atoms/cm3) - Sample 3 (M elemental concentration ~ 101b atoms/cI113) - Sample 4 (Oxygen concentration ~ lO's atoms/
cm3), and it was found that the dislocation propagation range became wider in this order.

(b), Defect distribution within the wafer cross section In sample 1, many precipitates and stacking faults grew uniformly, but in samples 2 and 3 (EZ wafer) and sample 4 (FZ wafer), precipitates and stacking faults grew uniformly. There was no generator. However, even in these wafers, in the devices manufactured by the P-O-M process, the dislocation caused by the P process became easy to move in the O process, and the dislocation propagated from the periphery or back surface of the wafer and was distributed over the entire wafer.

(C) Observation of defects on the wafer surface In sample 1, many primary stacking defects (generated in step 0) and dislocations were observed regardless of the processing method. In samples 2.3 and 4, the occurrence of defects depended on the wafer processing method. That is, wafers processed in the O-P-M process have almost no defects, but wafers processed in the P-0-M process have many dislocations.

Also.

-Secondary stacking faults (minor stacking faults generated in the M process) were observed in the wafers processed in the M process.

The above results are shown in the table below.

From this table, the dislocation density is: - In the P-M process and O-M process, there are very few secondary stacking faults, O-
It was found that the oxygen concentration was very low in the P-M process and P-0-M process, and the oxygen concentration in these processes was 1oIf.
It can be seen that as the number of atoms/c atoms decreases, the -order stacking fault density decreases significantly.

There are two possible causes of dislocation. First, in a CZ wafer (oxygen concentration 10'' atoms/cm3), dislocation is punched out from the precipitates growing inside the wafer during the O process, and those coming out of the precipitates near the surface easily reach the surface. EZ wafer (oxygen concentration 1
0'7 or 1016 atoms/cm3) or FZ wafers (oxygen concentration 10'5 atoms/cm3), the oxidation temperature is 1100°C.
Precipitates do not grow and therefore dislocation is significantly reduced due to the solid solubility limit of 4 x 10" atoms/cm3). On the other hand, for wafers processed in the P-0-M process, as mentioned above, The misfit dislocation caused by the P process propagates to the surface during the O process. This kind of propagation is almost absent in CZ wafers due to the above-mentioned pinning effect. The propagation of misfit dislocation in EZ wafers is more pronounced than in FZ wafers. The reason why this is unlikely to occur is considered to be due to the pinning effect of oxygen atoms or clusters thereof.

Although the -order stacking faults were observed only in the CZ wafer and were hardly observed in other wafers, the primary stacking faults in the CZ wafer are thought to be caused by strain related to oxygen inside the wafer. Secondary stacking faults are caused by minute defects formed by excessive metal impurities and the like that are generated near the surface during the cooling process in which the wafer is pulled out of the furnace after long-term oxidation.

The reason why such micro defects did not occur in the op-M and P-0-M processes is that misfit dislocation (lattice strain) caused by P diffusion absorbs excess metal impurities and causes micro defects. This seems to be due to the prevention of occurrence.

In addition, in the O-M process, the oxygen concentration is 1017 or lOI''
The reason why the value of atoms/cm' is smaller than that of 1015 atoms/cI113 is due to the interaction between oxygen and metal impurities, etc.
This is thought to be because the generation of micro defects that would have grown at the 5t-5iO□ interface was prevented to some extent. In CZ wafer,
- Since secondary stacking faults and precipitates have the function of absorbing excess metal impurities, etc., there is no growth of micro defects, which are the nucleus of their generation, and the generation of secondary stacking faults is eliminated.

(d) Relationship between recovery time and defects Generally, the density of crystal defects generated during the process is inversely proportional to the above-mentioned recovery time tf, and the smaller the defect density, the larger tr. FIG. 1 shows the results obtained when each of the wafers described above was processed in three different steps. According to this, in any process, the oxygen concentration of the wafer is 10" (actually 5 x 10") atoms 701112 or more and 101s atoms/c+++" or less, that is, the recovery time tf for EZ wafers.
It turns out that it is large and desirable.

In particular, EZ wafers with an oxygen concentration of 10'6 to 7xlQ
I? Atom/cII+'' is more desirable from the viewpoint of long recovery time and practicality, and in that range, oxygen concentration is large and close to the solid solubility limit is more likely to prevent dislocation movement. Desirable.
- In the case of M process, 7×101S to 1017 atoms/cI
An oxygen concentration of l13 gives good results.

To explain the results in more detail in the drawings, in the device produced by the P-0-M process, misfit dislocation mainly due to P diffusion dominates the device characteristics, but because of the large gettering effect on the back surface, the dislocation is decorated by impurities. The effect on characteristics is relatively small. Furthermore, the characteristics of the device produced by the O-M process are the worst.
It is thought that decorated stacking faults are the cause. Furthermore, it is believed that the device produced by the O-P-M process exhibits the best characteristics because it has fewer dislocations and stacking faults.

As explained above, the wafer according to this example can prevent the generation or growth of crystal defects that may occur due to heat treatment. Therefore, when elements such as diodes and transistors are formed in a wafer using a conventionally known method, since crystal defects do not appear at this process temperature, the noise characteristics, leakage current characteristics, etc. during device operation can be significantly affected. It can be improved.

Note that the thermal oxide film grown on the wafer surface by the above-described heat treatment may be removed, or may be left as is and used as a diffusion mask as is conventionally known.

Although the present invention has been described above based on an embodiment, it will be understood that this embodiment can be further modified based on the technical idea of the present invention. For example, various semiconductor elements may be formed, and the present invention can of course be applied to ICs and CODs.

[Brief explanation of drawings]

The drawing is a graph showing the relationship between the capacitance recovery time tr and oxygen concentration of a MOS capacitor manufactured using a wafer according to an embodiment of the present invention.

Claims (1)

[Claims] In a method for manufacturing a semiconductor device including a heat treatment step for a semiconductor substrate, a silicon substrate containing 5×10^1^5 to 1×10^1^8 atoms/cm^3 of oxygen is used as the semiconductor substrate, and the heat treatment A method for manufacturing a semiconductor device, characterized in that backside gettering is performed on the silicon substrate before the step.