JPS6249549A - Magnetic disk controller - Google Patents

Abstract

PURPOSE:To share a cache memory by registering the corresponding directory information to the entry of the corresponding directory memory in response to a searching result and a read/write commands. CONSTITUTION:A magnetic disk controller 10 contains a direct memory 45 having entries corresponding to each cache block of a cache memory 43. The directory information showing the using state of the corresponding cache block is registered to each entry. For the register level of the directory information within the memory 45, the area of the memory 43 can be allocated to any of magnetic disk drivers 20-23. Thus the memory 43 can be shared effectively in response to the access frequencies of the drivers 20-23.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a magnetic disk control device equipped with a cache memory that can be shared by a plurality of magnetic disk drives.

[Technical background of the invention and its problems] In this type of magnetic disk control device, the cache memory is
Multiple, for example, four magnetic disk drives DKO-DK
3, as shown in FIG. 5, it is common to fixedly allocate a cache memory area to each drive DKO-DK3 and prepare a corresponding directory memory.

However, in the above method, since a limited area of the cache memory is divided, the cache capacity allocated to each magnetic disk drive becomes small, resulting in a decrease in the cash hit rate. Furthermore, if the access frequency differs from drive to drive, the frequency of use of the cache memory area corresponding to the drive with low access frequency becomes low, and the use efficiency of the entire cache memory decreases.

[Purpose of the Invention] This invention was made in view of the above circumstances, and its purpose is to provide a magnetic disk control device that can efficiently share cache memory without depending on a plurality of magnetic disk drives or their number. be.

[Summary of the Invention] According to the present invention, a magnetic disk control device is provided that includes a cache memory that can be shared by a plurality of magnetic disk drives. This magnetic disk control device is provided with a directory memory having entries corresponding to each cache block of the cache memory. Directory information indicating the usage status of the corresponding cache block is registered in each entry of the directory memory. This directory information includes a disk block address indicating the address of the disk block stored in the corresponding cache block and a disk drive identifier indicating the corresponding magnetic disk drive. Further, the magnetic disk control device is provided with a directory search means for searching a directory memory in response to a read/write command including a disk drive identifier and a disk logical address, and a directory information registration means. This registration method is based on the search results of the directory search method and the lead/lead information.
In response to the write command, corresponding directory information is registered in the directory memory entry corresponding to the cache block to be replaced.

[Embodiments of the invention] An embodiment of the present invention is shown in FIG. 1(a) below.

This will be explained with reference to FIGS. 4(b) to 4.

FIG. 1(a) shows the configuration of a magnetic disk subsystem according to an embodiment of the present invention, where 10 is a magnetic disk control device. The magnetic disk control device 10 includes a plurality of
For example, 4 magnetic disk drives (DKO to DK3)
It has a hard disk control circuit (hereinafter referred to as IDC) 31 that controls the hard disk drives 20 to 23. HD C3
1 is a first bus 34 consisting of a data line 32 and a control line 33, and a driver/receiver (hereinafter referred to as D/receiver).
(referred to as R) 35 via a host system (not shown).
is connected to. The HDC 31 is also connected to a second bus 36. The bus 36 includes a magnetic disk controller lO.
Microprocessor 37 that controls the whole, a control program for the microprocessor 37 (microprogram)
A program memory 38 that stores 5 self-storing data, a work memory 39 that forms a work area for the microprocessor 37, and a buffer memory 40 that absorbs the difference in transfer speed between the magnetic disk drives 20 to 23 and the host system are connected. has been done.

41 is the third bus. Bus 41 is connected to second bus 36 via D/R (driver/receiver) 42 . Connected to the bus 41 are a cache control circuit 44 that mainly performs data transfer control including control of the cache memory 4.3, and a directory memory 45 in which directory information indicating the usage status of cache blocks of the cache memory 43 is registered. ing. In this embodiment, one sector of the magnetic disk is 256 bytes, one block (cache block) of the cache memory 43 is 16 bytes (64 sectors), and therefore one block of the disk (disk block) is also 16K.
bytes (64 sectors), ■ The mapping method of the cache memory 43 is the set associative method, ■ The cache block replacement method is the LRU method, ■ The number of levels (number of entries) of the directory memory 45 is 16 per column
, ■ The capacity of the cache memory 43 is 512 bytes.

FIG. 1(b) shows the format of directory information. Directory information consists of 4 bytes consisting of the 1st to 4th bytes.
This is byte information. The first byte is a 3-bit drive number LUN (Lo
) and the upper 5 bits of the 15-bit disk block address (address U). The second byte consists of address U followed by 8 bits of the disk block address (address M). The third byte contains the remaining (lower) 2 bits of the disk block address (address L), 4 bits of all “θ” data, 1 bit of error flag ERR, and 1
It consists of a bit valid display flag VB.

The fourth byte is an 8-bit LRU (LeastR
eeently U sed ) value. The above directory information is generated based on, for example, the drive number LUN and disk logical address included in the read/write command.

FIG. 2 shows the format of the read/write command. The read/write command is a 6-byte instruction including a command code specifying operations such as read/write, drive number LUN, disk logical address, data block number, and cache control bits cc2 to ccO. The drive number LUN consists of 3 bits and specifies one of the magnetic disk drives 20-23. In this example, the most significant bit of drive number LUN is always “
The disk logical address indicates the sector number of the disk specified by the drive number LUN, and consists of a total of 21 bits: 5-bit logical address 2.8-bit logical address 1.0.1. In this example, where the block (disk block) is 16 bytes, the upper 15 bits of the disk logical address (
Bits 6 to 20) indicate the disk block address. Further, in this example, since the capacity of the cache memory 43 is 512 bytes and one cache block is 16 bytes as described above, the number of columns is 2 (column 0 and column 1). Therefore, bit 6 of the disk logical address indicates the column number.

FIG. 3 shows the structure of the directory memory 45.

The capacity of the directory memory 45 is 128 bytes,
It consists of a column 0 area (64 bytes) starting from address 000 (hexadecimal expression) and a column 1 area (64 bytes) starting from address 040 (hexadecimal expression). column 0
．． Each area of 1 is divided into 16 levels (entries),
The label consists of 4 bytes, and allows the directory information shown in FIG. 1(b) to be registered.

Referring again to FIG. 1(a), the third bus 41 includes:
An LRU counter (hereinafter referred to as
The input of a driver 46 (referred to as CLRU) and the output of a driver 47 are also connected. The output of CLRU 4B and the input of driver 47 are connected to cache control circuit 44. Also, on the bus 41, there is a register file 4.
8 manpower ports and 8 manpower of comparator 49 are also connected. The register file 48 is RTCAO-RTCA
It consists of four registers 51 to 53 of 3. The output port of register file 48 is connected to the A input of comparator 49, and the output port of comparator 49 is connected to cache control circuit 44. The cache control circuit 44 outputs C from the driver 47 onto the bus 41.
Register file 48 of LRU4B contents (LRU value)
The register file 48 is connected to control the input to the register file 48.

, the output of a directory memory address counter (hereinafter referred to as CDMA) 54 that specifies the address of the directory memory 45 is connected to the address port A of the directory memory 45, and the input of the CDMA 54 is connected to the second lotus 36. . CDMA54 output is register file 5
The output port of the register file 55 is also connected to the second bus 36 . Further, a control circuit 44 is connected to the register file 55 so that the cache control circuit 44 can control the register file 55 .

The register file 55 includes 3 of RCGAO to RCGA2.
It consists of two registers 60-62.

Next, the operation of one embodiment of the present invention will be explained.

Read/write commands (see Figure 2), which are disk access requests from the host system, are handled by D/R35,
The information is transmitted to the HDC 31 via the bus 34, and the HDC 31
is held in a command register (not shown) within.

The read/write command in the command register is read by the microprocessor 37 and stored in a predetermined area of the work memory 39. When the microprocessor 37 stores the read/write command (from the host system) in the work memory 39, it issues a seek command and sets it in the HDC 31 in accordance with the request. This allows HD
C31 controls a designated drive of the magnetic disk drives 20 to 23 to seek a designated track.

Further, the microprocessor 37 first checks bit 6 of the disk logical address in order to check whether the disk block address including the disk logical address in the read/write command is registered in the directory memory 45. If bit 6 is “0”, the column 0 area of the directory memory 45 is the target of the directory search, so the microprocessor 37
00 as the directory start address in DMA54
Set to 0. On the other hand, if bit 6 is "1#", the microprocessor 37 sets 040 in the CDMA 54 because the column 1 area of the directory memory 45 is the target of the directory search.

Next, the microprocessor 37 sets the drive number LUN in the read/write command and the first byte consisting of bits 16 to 20 of the disk logical address to the RTCAO register 50 in the register file 48, and sets bit 8 of the disk logical address to the RTCAO register 50 in the register file 48. The second byte consisting of .about.15 is set in the RTCA register 51. The microprocessor 37 also controls bit 6 of the disk logical address.
．． 7.4-bit all “0° data”, error flag ERR with value “0”, and valid display flag V with value “1”
The third byte consisting of B is set in the RTCA2 register 52, and the fourth byte consisting of an LRU value of 0 (minimum LRU value) is set in the RTCA3 register 53. That is, the microprocessor 37 generates target information for directory search based on the drive number LUN and disk logical address in the read/write command, and sets it in the register file 48.

After completing the above setup, the microprocessor 37 activates the cache control circuit 44 to start a directory search. As a result, the directory search cycle shown below is repeated 16 times.

In this directory search cycle, first CDIvl
The (directory memory) address indicated by A54 is set in the RCGAO register 60 in the register file 55. Also, CDMA54 is counted up sequentially.

As a result, the directory memory 45 indicated by the CDMA 54
The level (entry) directory information is read out in byte units sequentially from the first byte to the lotus 41, and the comparator 49
is fed to the B input of In addition, in synchronization with this, the target information set in the register file 48 is taken out in byte units starting from the first byte and is supplied to the A input of the comparator 39. A comparator 39 compares the input contents of A and B. The comparison result of the comparator 49, that is, the register file 38
The results of the byte-by-byte comparison between the target information from the directory memory 35 and the directory information from the directory memory 35 are sequentially notified to the cache control circuit 44. Further, the LRU value of the directory information supplied from the directory memory 45 to the B input of the comparator 49 via the bus 41 is loaded into the CLRU 4B and incremented by +1.

The cache control circuit 44 first determines whether or not a cache hit has been made based on the first to third byte comparison results of the comparator 49. If there is a cache hit, the cache control circuit 44 sends a hit flag indicating the cache hit to the (directory memory) address (address indicating the start position of the corresponding level of the current directory search cycle) set in the RCGAO register 80 in the register file 55. RCG by adding
Set in AI register 61.

Next, based on the LRU value comparison result of the comparator 49, the cache control circuit 44 controls the directory memory 45 corresponding to the replacement target cache block at that time.
level). If the LRU value from the directory memory 45 is greater than or equal to the LRU value from the register file 48, the cache control circuit 44 temporarily determines that the cache block corresponding to the corresponding level (entry) is the replacement target cache block. In this case, the cache control circuit 44 sets the (directory memory) address set in the RCGAO register 60 in the register file 55 in the RCGAO register 62. In addition, the cache control circuit 44 causes the driver 47 to output the LRU value indicated by the CLRU 46 (+1) onto the bus 41, and changes the LRU value set in the RTCA3 register 53 in the register file 48 to the LRU value on the bus 41. Update.

Furthermore, cache control circuit 44 writes the LRU value on bus 41 (from CLRU 46) to the corresponding level of directory memory 45, regardless of the comparison result of comparator 49. That is, in this embodiment, L in the corresponding level of the directory memory 45 is determined in each directory search cycle.
The RU value is increased by +1.

The above is the directory search cycle, and this cycle is repeated for each piece of directory information in the 45th level O to F (hexadecimal representation) of the directory memory, thereby completing the directory search corresponding to the read/write command.

At this time, if the cache block has been cached, the RCGAI register 61 in the register file 55 contains the directory memory 35 corresponding to the cache block.
The (starting) address of the level should have been set. Further, the RCGA2 register 62 in the register file 41 is set with the (starting) address of the level of the directory memory 35 having the largest LRU value in the designated column. In the case of a cache miss when specifying a read, this address is used as the replacement target carrier.
The level (entry) of the directory memory 35 corresponding to the source block is shown.

When the directory search is completed, the microprocessor 37 registers the RCGA register 6 in the register file 55.
1 is read via the bus 36, and it is checked whether it was a cash hit or a miss. If there is a cache miss when specifying a read, the microprocessor 37 changes the directory address indicated by the RCGA2 register 62 in the register file 55 to correspond to the oldest referenced cache block at that time (i.e., the cache block to be replaced). It is read as the start address of the level of the directory memory 45 and set in the CDMA 54. And the microprocessor 37 uses CDMA
54, the directory information is registered in the corresponding level (entry) of the directory memory 45. This directory information is basically the register file 4, except that the LRU value is the initial value.
This is the same as the target information in 8. In this example,
The initial value of the LRU value is the cache control bit cc.
Specified by 2~ccO.

As is clear from the above explanation, the directory memory 45 for directory information (at the time of directory registration)
The internal registration level (and therefore the cache block to be replaced in the cache memory 43) is the same as in the case of a magnetic disk control device that controls one magnetic disk drive by including the drive number LUN indicating the magnetic disk drive in the directory information. The LRU value (large/small) of the directory information at each level is determined. Therefore, cache memory 43 (directory memory 4
Unlike the conventional example (see FIG. 5), the area 5) can be allocated to any of the magnetic disk drives 20 to 23 as shown in FIG. Therefore, in this example,
The cache memory 43 is connected to the magnetic disk drives 20 to 2.
It can be shared efficiently depending on the degree of access of item 3.

Note that the operation of reading a disk block indicated by the directory information registered in the directory memory 45, writing to the cache memory 43, etc. will not be described because they are not directly related to the gist of the present invention.

Now, in the embodiment described above, a case has been described in which the cache memory 43 is shared by all the magnetic disk drives 20 to 23, but the present invention is not limited to this. For example, for magnetic disk drives such as O5 (operating system) that have disk blocks that are loaded only once or once (i.e., drives with low access frequency), the cache is not used, and the cache memory 43 is used only by the remaining drives. It is also possible to share. In this case, the limited capacity cache memory 4
3 can be used more efficiently, and the hit rate is further improved.

Note that the designation of whether or not to use the cache (cache mode designation) may be specified for each magnetic disk drive using a command when the power is turned on or the like.

[Effects of the Invention] As described in detail above, according to the present invention, a plurality of magnetic disk drives can efficiently share cache memory regardless of the number of magnetic disk drives.

[Brief explanation of drawings]

FIG. 1(a) is a block diagram of a magnetic disk subsystem according to an embodiment of the present invention, FIG. 1(b) is a diagram showing the format of directory information, and FIG.
Figure 3 shows the format of the write command.
Figure (a) Buileff! - A diagram showing the structure of the re-memory 45,
FIG. 4 is a diagram showing the correspondence between the cache memory 43 and directory memory 45 in the above embodiment, and FIG. 5 is a diagram showing the correspondence between the cache memory and directory memory in the conventional example. 10... Magnetic disk control device, 20-23... Magnetic disk drive, 37... Microprocessor,
43... Cache memory, 44... Cache control circuit, 45... Directory memory, 48
．． 55...Register file, 49...Comparator. Applicant's representative Patent attorney Takehiko Suzue (b) Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] In a magnetic disk control device equipped with a cache memory that can be shared by multiple magnetic disk drives, the disk block has an entry corresponding to each cache block of the cache memory, and each entry corresponds to a disk block of a disk block stored in the corresponding cache block. a directory memory in which directory information including an address and a disk drive identifier indicating a corresponding magnetic disk drive is registered; a directory search means for searching this directory memory in response to a read/write command including the disk drive identifier and a disk logical address; A magnetic disk control device characterized by comprising: registration means for registering corresponding directory information in an entry of the directory memory corresponding to a cache block to be replaced in accordance with the search result of the directory search means and the read/write command.