JPS59114658A - Management of data memory space - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to multi-level data storage hierarchies and, more particularly, to the management of data storage space allocated to data at higher levels of the data storage hierarchy. It depends.

[Background of the invention]

Peripheral storage hierarchies have been used for many years to provide virtual storage (apparent storage) as disclosed in US Pat. No. 3,569,938. According to the above patent, in a demand paging system, data is stored at high speed in a cache-type high-speed front storage (buffer), so that the peripheral storage system has an apparently large capacity, and moreover, can be made to provide access to data faster than the speed provided by memory;
Furthermore, the rear storage may use non-volatile storage such as magnetic tape recording and magnetic disk storage, while the front storage may use volatile storage such as magnetic core storage. With advances in data storage technology, front storage typically includes semiconductor-based data storage elements. Another form of such a storage hierarchy is disclosed by US Pat. No. 3,839,704. It is important for the storage hierarchy to obtain good performance at low cost.

There are various forms of memory hierarchy. For example, according to the aforementioned US Pat. No. 3,569,938, a single high speed storage serves multiple users.

US Pat. No. 3,750,360 shows that each processor may have its own high speed memory, or cache. The performance of the storage hierarchy is also affected by the algorithms and other controls used to place certain data into the cache or fast storage portion. Along these lines, U.S. Pat. No. 3,898,624 shows that the time at which data is retrieved from rear storage to front storage or cache storage can be selected by a computer operator according to a program running on the CPU in use. ing. Thus, while some data in the cache or higher levels of the storage hierarchy is needed by the CPU, other extraneous data is preferably not in the cache. This configuration allows more useful data to be stored in higher level storage. All of these operations can be very complex. Therefore, storage hierarchy evaluation programs are used to evaluate how best to manage the storage hierarchy. U.S. Patent No. 3964028
No. 4,068,304 discloses monitoring storage hierarchy performance to achieve these goals. Even then, much remains to be done at the various storage tiers to improve optimal performance while ensuring data integrity. Much of the research on memory hierarchies has focused on the combination of cache and main memory connected to the CPU. As first suggested by the aforementioned US Pat. No. 3,569,938, the principles of cached main memory can be directly applied to peripheral systems. Of course, even before the above-mentioned U.S. Pat. It is also used as a buffer for peripheral devices.

The above performance monitoring indicates that constant use of cached buffers interposed between usage units and back storage is not necessarily in the best interest for overall data processing performance and integrity. Therefore, for example, U.S. Pat.
No. 75,686 discloses that the cache can be turned on and off by special instructions to selectively bypass the cache. Furthermore, in cases such as sequential I/O operations, the back storage was divided into segments, some of which were bypassed. US Patent No. 4268
No. 907 discloses that an indicator flag is set to a predetermined state for a command that specifies the retrieval of a data word. Such flags cause the replacement circuitry to respond to subsequent predetermined commands to bypass the cache for subsequently retrieved data words.

This is to ensure that many data instructions stored in the cache are not replaced during their execution.

Interestingly, US Pat. No. 4,189,770 shows bypassing the cache for operands, but using the cache to store instructions.

Disk Storage - Direct Access Storage Device (DASD)
A large amount of data is held in a non-volatile manner for data processing. As suggested earlier, D.A.
Caching SDs provides a storage hierarchy with better performance and throughput than DASDs alone. This performance improvement is primarily achieved by reducing the cache miss rate. Managing the data storage hierarchy involves dynamically changing the contents of the cache with the aim of increasing the rate of accesses that can be achieved by the cache. Although such management tends to reduce the size of front storage in terms of cost, further savings may be possible since data does not always fill a DASD record track. In short, it is necessary to carefully manage the utilization of data storage space in front storage. Even if a large data storage space, for example 30 kilobytes or more, is allocated to front storage, it will not always be filled with data signals.

Managing data processing equipment to ensure full utilization of the available space in any data storage unit includes storage of variable length data. For example, U.S. Patent No. 3739
No. 352 discloses a microprogrammed processor associated with a so-called "free field" memory that can process operands of any range of number of bits. The address register that addresses free field memory specifies the boundary between any two bits in memory as the starting point of a field, and also specifies the number of bits in this field up to the maximum bit capacity of free field memory. be able to. Although this method does seem to maximize the efficiency of using a given data storage unit, when replacing one data with another, the probability that both data will be the same (size and number of bits) is Relatively small.

This means that if storage efficiency is to be maintained, the storage format of the memory must be changed each time data is replaced. Therefore, while this method is likely beneficial in many use cases, it is not applicable to front store/rear store data storage hierarchies due to data replacement operations. If applied forcibly, data fragmentation will occur,
It is easy to imagine that complex and time-consuming management methods would be required.

Another U.S. Pat. No. 3,824,561 discloses a technique for allocating storage addresses when storing groups of variable length data elements using a characteristic data set that defines the characteristics of each data element. This technique requires scanning the data set in two directions. In the first pass, information about the length and boundaries of each element is accumulated, and then in the second pass,
Addresses are assigned to each element and gaps within the group are removed while maintaining proper boundary alignment.

This technique is also valuable in certain applications except for data storage hierarchies where replacement operations are required. The performance required in the peripheral data storage hierarchy cannot be achieved with such time-consuming allocation techniques.

U.S. Pat. No. 4,027,288 discloses a technique for arbitrarily lengthening information segments up to the maximum capacity of the storage facility using a character set that includes a starting delimiter and an ending delimiter. Thereby, data storage allocation and reclamation of unused storage space is automatically performed when the length of a data string changes. This method is suitable for sequential access type magnetic tape, but
It is not suitable for random access memory, which is used in most frontal storage.

U.S. Pat. No. 4,035,778 discloses an allocation of working space in the main memory of a host processor, in which the allocation is optimized by adjusting the size of the working space set for each competing program. . host·
In a data storage hierarchy where the processor has a close working relationship with frontal or working memory, the working memory can be thought of as a buffer. The technology of this patent also relates to displacement control, where the allocation of working space is adjusted according to the displacement technique. Peripheral data storage hierarchies cannot take advantage of this technique due to their flexible coupling with the host processor.

No. 4,103,329 discloses processing data represented by variable length fields in a peripheral data storage unit to use smaller data storage. Bit fields are handled independently in normal storage addressing elements and boundaries. This patent discloses the initialization of a displacement register containing an element displacement from a base address containing the first bit of the requested bit field. Such technology is certainly
Although suitable for packing data into main memory for use by a host processor, complexity and cost increase dramatically when amounts of data are in the megabyte range. Therefore, this technique is also not fully satisfactory for managing the front storage of the peripheral data storage hierarchy.

Additionally, other techniques used to improve data storage utilization include IBM TECHNICAL
DISCLO8URE BULLETIN, Vo
l, 14, Na 7, December 1971
, pp.

There is one described in 1955-1957.

This paper presents an asymmetric fast storage consisting of one 8KB (kilobyte) area and two 4KB areas, each with a separate directory. Obviously, smaller data sets are stored in a 4KB area, whereas larger data sets are stored in an 8KB area. Such techniques are suitable for handling relatively large variable length data.
It is not suitable for front storage management where blocks, ie blocks larger than 30 KB, are to be transferred as units. Gates et al.’s paper “Multiword”
SizeStorage”, IBM TECHN
ICAL DISCLO8URE BULLETI
N, Vol, 14, Na 8, January 1
969, pp. , 1019-1020, management of data storage devices to avoid wasted or unused storage bits due to data word size differences is presented. The technique of this article involves storing words of two different sizes and alternating the storage so that there are no unused disks. This article deals with the management of data storage only in the case of an extremely limited set of data formats and does not apply to storage in the general case.

Despite the various prior art techniques for maximizing the utilization of data storage devices, a simple yet effective management device and management capable of processing large data units at a relatively low cost while at the same time maintaining high performance. A method is needed.

[Summary of the invention]

According to the invention, a data storage device has allocable data storage space each having a data storage capacity that is less than the maximum capacity required for a given data transfer. For each input data transfer, an initial maximum allocation of data storage space is made in the data storage unit for the expected data, and the data is transferred to the allocated data storage space.

Once the data transfer is complete, a check is made as to which of the allocated data storage spaces are not actually receiving input data. Any data storage space that does not receive input data is deallocated and can be used to store other data.

In other words, the maximum initial allocation of data storage space is made according to the maximum data transfer size, and when the data transfer is completed, the initial allocation is reduced to the actual data transfer size and the allocated data storage space is The remaining portion of is deallocated.

[Detailed explanation]

In the following detailed description with reference to the drawings,
The same reference numbers indicate the same parts and structural features in different drawings. 1 and 2, one or more usage units 10, such as a central processing unit, host processor, etc., are connected to a storage director 12 via peripheral connections (hereinafter referred to as channels 11).

Storage director 12 is suitably connected via device interface 13 to a plurality of direct access storage devices (hereinafter referred to as DASD14). Cache 15 selectively connects DASD 1 4 to one or more usage units 10 via channel 11 . Access to data stored in cache 15 is via directory 16. Using the identified address of DASD 14, usage unit 10 requests data access to a storage subsystem including cache 15 as front storage and DASD 14 as rear storage. The said address is
When stored in directory 16, cache 1
Data access requests can be satisfied by referring to data stored in DASD 5 and without referring to DASD 14. The operation of the storage system is under the control of a programmable processor 17 which includes a control memory 18 and a processing unit 19. The control memory 18 is stored in the cache 1 by the processing unit 19.
5. Storing a program for properly controlling the directory 16 and the DASD 14 and facilitating communication with the unit 10 used. Most of the functions performed by programmable processor 17 in response to stored programs are well known in such storage systems and will not be described in detail.

Directory 16 has a plurality of registers (directory registers), each of which stores a DASD address (section 20), as will be explained in more detail in connection with FIG. Identifies the address of the DASD 14 that is to be or actually stores data currently stored in the addressable portion. The storage location of cache I5 is pointed to by a cache address pointer P1 contained in section 22 of each directory register, or which register of directory 16 is assigned to DAS.
The storage of the D address 20 may indicate that the address of the directory register is mapped to the addressable data storage space of the cache 15.

In accordance with the present invention, allocatable data storage space (addressable data allocated as a single unit) pointed to by a DASD address 20 in directory 16 has a capacity that is less than the data storage capacity of data storage track 21 of DASDI4. A set of storage registers) are included in cache 15. Rather, the amount of allocable data storage space of cache 15 is an integer divisor of the maximum capacity of data storage tracks 21. In the case of the present invention, the allocatable data storage space of cache 15 is one-third of the track capacity of DASD 14.

Therefore, three cache addresses are required to address the contents of a complete or ASD track stored in cache 15. This addressing is accomplished by obtaining an address pointer P1 in a section 22 of directory 16 that identifies allocatable data storage space 23 of cache 15 and storing the first third of the tracks of DASD 14. It will be done. Allocatable data storage space 23 has a pair of pointers P2 and P3 in J\ spaces 24 and 26 therein. D.A.
P2 of the SD 14 is an allocatable data storage space 25 that stores the second third of the tracks of the DASD 14.
P3 contains an address pointing to an allocatable data storage space 27 that stores the third third of the track. In this way, cache 15 3
The two allocatable data storage spaces are coupled to store the data content of one track. The number of said plurality of allocatable units of cache 15 may be different from three, and additional pointers such as pointers P2 and P3 are added to the first allocatable data storage space 23 pointed to by directory 16. Instead of being stored, pointer P1 is stored in section 22 of directory 16.
may be stored together with. Storing pointers P2, P3 in cache 15 simplifies the structure of directory 16, but requires one more access to cache 15 to set up the data transfer, as will become clear later.

In accordance with the present invention, when cache 15 is to receive data from usage unit 10 or DASD 14, programmable processor 17 is not given an indication of the range of data that cache 15 will receive. That is, it may be a full track of data, or it may be less than a full track of data. Therefore, each time cache 15 is scheduled to receive data, three allocatable data storage spaces of cache 15 are allocated to the incoming data. Following this allocation, data transfer occurs. Once the data transfer is complete, programmed processor 17 checks which of the allocated data storage spaces, such as 23.25 or 27, actually received and stored the data. The data storage space that received no data is then deallocated by setting the appropriate pointer to 0, making it available for reallocation of non-rack related data to one of the DASDs 14 that was just addressed. In this way, cache 1
By managing the data storage space nfJ of 5, a larger number of tracks can be effectively stored in cache 15 with a relatively small cache capacity, reducing costs. In other words, if the same size cache 15 is used, the contents of a larger number of addressable A-8D14 data storage tracks can be stored in the cache 15.

Performance is improved. Of course, cache 15 has a number of allocatable data storage spaces 28 and 29 (indicated by ellipses).

The distribution of data from a single addressable data storage track to multiple unrelated segments or data storage spaces of cache 15 requires rapid concatenation and some buffering when high speed data transfers are involved. In order to improve the flow of input/output data signals of the cache 15,
As shown in FIGS. 1 and 2, a plurality of 5 SARs (System Storage Address Registers) 30 are provided. 5S
The AR-0 retrieves the pointer P from the directory 16 in preparation for accessing the allocated data storage space 23.
Receive 1. 5SAR-1 and 5SAR-2 receive pointers P2 and P3 from spaces 24 and 26 of the allocated data storage space 23, respectively. This operation completes preparations for subsequent data transfer. FIG. 4 shows how multiple address registers can quickly connect multiple addressable data storage spaces to receive high speed data signal bursts.

Each time a data access request is received, programmable processor 17 examines directory 16 to determine whether the associated allocatable data storage space has been allocated to the DASD address received from usage unit 10. If there is no match, a cache miss occurs as shown at 35. Such cache misses cause the DASD 14
Data may be promoted from the cache 15 to the cache 15. Such a cache miss causes processing unit 1
9 accesses control store 18 to execute program 36, which may result in data transfer from DASD, 14 to cache 15. Furthermore, a cache write hit - meaning that data is transferred from the usage unit 10 to the cache 15 - causes the programmable processor 17 to execute a program 36, as shown by arrow 37, and causes the cache 15 to write to the host (use unit 15). unit 10), which may contain up to an entire track of data, the extent of which is, of course, currently unknown to the data storage system. In such host writes, the host data is preferably written to DASD 14 simultaneously.

In any case, programmable processor 17
executes program 40 in response to program 36;
Allocate one DASD track capacity to cache 15 and pointer P1. Set P2 and P3. For example, if no data storage space in cache 15 has been previously allocated, three data storage spaces in cache 15 are allocated and corresponding pointers are generated. On the other hand, if only one data storage space is currently allocated, then two more data storage spaces are allocated and corresponding pointers are generated, as will be explained in more detail in connection with FIG. be done. Upon completion of execution of program 40, programmable processor 17 executes program 41.
Execute. This actually results in data transfer from the host (using unit 10) or DASD 14 to cache 15, depending on the situation. Once the data transfer is complete, programmable processor 17 executes program 42 to check the ending address of the last byte of data transferred to cache 15. This check identifies which of the allocated data storage spaces actually received no data. That is, checking the ending address determines which of the three allocated data storage spaces last received data. Programmed processor 17 then executes program 43 to deallocate unused cache allocations made for data transfers. Of course, other programs 44 typically present in the data storage subsystem are executed before and after the execution of programs 36 and 43, but their details are omitted as they are not relevant to the understanding of the present invention.

In program 40, programmable processor 17 may be required to replace data residing in cache 15, and there is a need to identify free or free data storage space. This operation is similar to the L
This is performed using an RU (least recently used) replacement control list (hereinafter referred to as LRU 47). LRU 47 contains the identification of allocatable data storage space. Accordingly, MRU-LRU program 46 is used by programmable processor 17 to execute program 40 to scan LRU 47 to allocate data storage space. If there is sufficient data storage space available for allocation, these spaces are allocated without further action. However, if there is no data storage space available for allocation, the programmable processor 17 uses a replacement program 45 using known replacement methods.
is used to transfer data in the allocated data storage space to be replaced to DASD 14.

If DASD 14 is updated at the same time as cache 15, space in cache 15 is immediately reallocated for incoming data without pre-replacement data transfer to DASD 14. In this way, cache 15 can always be filled with promoted data. Since program 48 causes programmable processor 17 to access cache 15 using known methods, details of program 48 will be omitted.

FIG. 2 shows a preferred embodiment of the invention using two storage directors 12. Each storage director 12 includes a plurality of channel adapters 50.

These channel adapters also individually
AD (the number need not be four) connects each storage director 12 to a plurality of usage units 10 via a plurality of channels 11 .

Each storage director 12 typically includes a processing unit 19 having a control memory 18 containing a computer program that performs storage director functions. Second
The figure shows the logical structure, ie the functions realized in the processing unit 19 by the execution of the programs located in the control memory 18. The programmable processor 17 includes a usage unit 1.
This includes a program that configures the address and command evaluator JACE52, which receives and evaluates peripheral commands supplied by the JACE52. It is executed in the storage director of , and is a part of "other programs 44" in FIG. Programmable processor 17
It also provides device commands to the DASD 14 to perform well-known DASD access and control functions, as well as
Contains programming for an indirect access control DAC 53 that controls data transfer between usage unit 10 and DASD 14 in response to commands evaluated and decoded by ACE 52. The DAC 53 includes a known program that accesses the DASD 14 and a program 41 that is included in "other programs 44" in connection with accessing the DASD 14 and transferring data between the units 1 to 10 and the DASD 14. . Programmable processor 17 further includes a cache access control program CAC 34 for accessing cache 15 . C provided for each DASD14
The D latches 59 are accessed by the DAC 53 and CAC 34, respectively, and are accessed by the cache 15 or DASD1.
4 is to be accessed directly and the latch is set to D in case of a cache miss. Connections from storage director 12 to DASD 14 are made through DASD circuitry 55, which is constructed using known device adapter and data flow design techniques. Cache 15 is accessed through storage circuitry 56 that includes circuitry, such as 5SAR 30, that generates addresses and access requests. Cache 15 is a large capacity random access memory (hereinafter referred to as system memory 57).
It is a part of.

Preferably, cache 15 can handle data transfers simultaneously and independently with DASDI 4 and the host (Using Unit IO). Directory 16 of cache 15 and LRU 47 are also stored in system memory 57. Furthermore, every usage unit 10 has a storage director 12
This can be done by giving a command to the cache 15 and fixing the data in the cache 15. All pinned tracks are stored in the cache pinned list 60 - directory 16, but are shown separately for clarity.
Both storage directors 1 determine which data recorded in the cache 15 should remain in the cache 15.
2 is instructed. Such fixed data is not written to LRU 47 to prevent reallocation of cache 15 space by replacement program 45.

A plurality of DASDs 14 are each connected to a controller 65--one DC
The storage director 12 is connected to the storage director 12 through the
Access to the DASD 14 is made through a so-called decimal string array connected to the DASD 14. Each storage director 12 has a decimal chain device connection (
It is connected to the controller 65 via the device interface 13). Known radial connection designs may be used.6 The operation of the system shown in FIG. 2 in accordance with the present invention is best understood by reference to the computer operation flowchart shown in FIG.

At step 70 of FIG. 3, programmable processor 17 receives a storage access request. This request is decoded and evaluated by the ACE 52 using known methods. At step 71, the DAC 53 portion of the programmable processor 17 determines whether the D
The CD latch 59 (FIG. 2) associated with the ASD 14 is examined to determine whether the cache 15, or only the DASD 14 to the exclusion of the cache 15, is to be accessed. In case of direct access, DA
SD 14 is accessed at step 72 using conventional DASD access methods. In the case of cache access, in step 73 the programmable processor 17
searches directory 16 to determine whether the track requested in the received storage access request (I10 command) has space allocated in cache 15.

In this regard, some commands are cache 15
It is noteworthy that it requires a direct connection to the DASD 14, excluding the . Therefore, upon detecting such a command, the ACE 52 directs the addressed DASD 14
CD latch 59 is set to direct mode rDJ. An example of such an I10 command is recalibration of the DASD 14.

Search commands may be executed within directory 16 for cache 15 accesses. That is, this command is executed in a virtual manner that is not related to DASD 14. In the preferred embodiment, the relay 16 does not individually identify the records on the track, only the trunk, but of course the invention is not so limited.

When gf4 in directory 16 is finished, step 7
At 4, programmable processor 17 determines whether a cache hit has occurred. If a cache hit occurs, in step 74A, programmable processor 17 transfers Pl stored in register section 22 of directory 16 identified by the received DASD 14 address to 5SAR-0, then P2 and P3. 5SAR-1 and 5S from their respective storage locations
Transfer each to AR-2.

At step 75, storage director 12 examines cache 15 to determine whether the record being accessed is stored in cache 15 (record hit). If the addressed record is in cache 15 (record hit is yes), no additional segments are required to successfully complete the subsequent data transfer. Next, at step 76, the type of data transfer operation to be performed is examined. In the case of a read operation R (data transfer to the host), the storage director 12
transfers the requested data from the cache 15 to the requesting host (using unit hlO). Once the operation is complete with this transfer, the storage director I2 can move on to another data processing operation via path 78.6 In the case of a write operation W (data transfer from the host), in step 80, the storage director 12 The command received from the host is examined to determine whether the write is a format write (only access to DASD 14 is required) or another type of write (allowing writing to cache 15). For format writes, storage director 12 deallocates data storage space in cache 15 and transfers the received data to DASD 14 at step 81 . In step 80, unformatted writing (format =
0), in step 82 the storage director 12 transfers the data from the requesting host (using unit 10) to the addressed data storage area of the cache 15 and DASD 14. In this way, cache 15
and DASD 14 always have identical copies of the same data. From steps 81 and 82, storage director 12 proceeds via path 78 to other data processing operations. This operation allows allocations (partial track allocations) smaller than a full 11-rack allocation in the cache to handle successive data transfers.

In step 75, if the storage director 12 does not find the addressed record (record hit is no), then for the impending data transfer to the cache, an additional ceramic 1- is allocated for the subsequent data transfer. It may happen. At step 85, storage director 12 examines the values of P2 and P3. If either or both pointers are O (the corresponding space has not been allocated in cache 15), then in step 86 storage director 12 allocates additional segments for the track as previously described. Thereafter, the process proceeds to step 87 to transfer the data to the cache 15. The data transfer in step 87 is performed from the host to the DASD 14 and the cache 1.
5, a read from DASD 14 to cache 15 and the host, or a data staging operation from DASD 14 to cache 15.

As a post-transfer machine operation, storage director 12 examines cache 15 to determine which of the three allocated segments actually received data from the data transfer that just completed. At step 88, storage director 12 examines segment counter 129 (FIG. 4), which will be described later, and indicates a value of 1.2 or 3 - one, two or three allocated segments (PI, P2), respectively.
, corresponding to P3), confirms - indicating that the data has actually been received and currently stored. If K=1, then in step 90 storage director 12 stores segments 2 and 3.
(also referred to as XM and YM, respectively) and
RU list 1~ to make these segments available for allocation. At step 91, corresponding pointers P2 and P3 are set to zero. If =2 in step 88, storage director 12 inserts the third segment YM into LRU list 1~ and sets pointer P3 to O in steps 92 and 93.

If =3 in step 88, storage director 12:
Knowing that all three segments 1 have received and are currently storing data, we proceed via path 78 to the direct data processing operation. The process also proceeds to path 78 from steps 91 and 93.

If there is a cache miss (hit=0) in step 74, storage director 12 stores the three segments (XY, XM, YM
) for subsequent data transfer and pointers P1, corresponding to the respective 5SAR0, 1 and 2.
Sera 1- is applied to P2 and P3. Storage director 12 then proceeds to a data transfer operation performed at step 87, as previously described.

In one embodiment of directory 16, directory 1
Each of the registers in cache 15 has one space 2 in cache 15.
8 (Fig. 1). Therefore, section 22
is also the starting address in the cache 15 of the related space (
Using base+offset addressing) there is no need to point to a register address in directory 16.

The allocation then consists of inserting the appropriate ASD address into section 20 of the register. Addresses XM and YM become pointers P2 and P3, respectively, and are stored in spaces 24 and 26 in data storage space 23 corresponding to address XY. Note that there is no change in directory 16 for these last two pointers. For the directory structure described above, where a given register is always associated with one data storage area of cache 15, addresses P2 and P3 are inserted into their respective pointer registers, and registers P2 and P3 are dropped from LRU 47. . With the above steps, setting I to up of pointers for subsequent data transfer is completed.

FIG. 4 shows an addressing circuit for cache 15 that can be used with the present invention. Data path 100 in the case of data transfer to/from DASD 14 runs from cache 15 via storage circuit 56 to DASD circuit 55 . The data path also reaches a channel adapter 50 for data transfer to and from the usage unit 10, as shown in FIG. cache 15, channel adapter 50 and DA
Data transfer between SD circuits 55 is under the control of conventional automatic data transfer circuits of known design and currently used in DASD storage systems.

Such automatic transfer control circuitry is shown in FIG. 4 as automatic control 101, which is part of storage circuitry 56. Programmable processor 17 sends the appropriate start signal to line 10.
2 to the automatic control 101. It is assumed that 5SAR 30 is loaded with the appropriate addresses P1, P2, and P3 received from programmable processor 17 via address buses 110, 111, and 112, respectively. Such loading of address registers from programmable processor 17 is well known.

Automatic control 101 provides a cache 15 access control signal to cache 15 via line 103 as soon as it receives the start signal.

As a result, cache 15 receives addresses that access data storage registers within the cache, as will be explained below. The access control signal on line 103 carries an indication of whether the operation is a read operation from the cache or a write operation to the cache. Many caches 15 sandwich refresh cycles between data access cycles. Cache 15 is 1
Each transfer of a set of data signals via data path 100 instructs automatic control 101 via line 104 for one operating cycle. The automatic control 101 is preset in a known manner to transfer a given number of data signals between the cache 15 and the DASD 14 or the host (utilization unit 10).

When a data signal is being written to cache 15,
Automatic control 101 may not know the number of signals received. In this case, another signal is provided via line 102 to turn off automatic control 101 and remove the signal on line 103. For example, in data transfer from the host to the cache 15, the I8M370 interface
Using the architecture, the host sends the so-called COMMAND OUT I1, which indicates the end of the data transfer.
0 tag signal may be sent. Such an I10 tag signal causes programmable processor 17 to send another signal on line 102 instructing automatic control 101 to terminate the data transfer. Termination of a data transfer, either internally by automatic control 101 or by an externally received command, is indicated to programmable processor 17 by a termination signal provided via line 105.

The automatic control 101 is performed every operation cycle of the cache I5.
issues an address increment signal on line 115. The address increment signal is sent from programmable processor 17 to bus 1.
5SAR 30 selected by the 5SAR address received via 30. The addressing of multiple address registers is well known and will not be described here. Once Pl, P2 and P3 are loaded, the 5SA received from the programmable processor 17
The R address signal selects 5SAR-0.

Decoder 131 decodes the address signal and sends an AND circuit enable signal to AND circuit 116 via line 132.
and 120. AND circuit 116 connects line 11
Send the address increment signal on 5 to 5SAR-0 to 5SA
Increment the address contained in R-0. The same procedure is used when decrementing an address. Each time 5SAR-0 is incremented, one set of address signals is output to AND circuit 120.
is supplied to the cache 15 via the address bus 123, and is further transferred to the cache 15 for data transfer.
The next data storage location within the addressed data storage space is selected.

When 5SAR-0 has counted across all of the addressable data storage locations within one data storage space of cache 15, 5SAR-0 provides a carry signal on line 126 to OR circuit 125 and the segment
Increment counter 129. Data storage location (k
is an integer)
- Counter 129 is preset to zero by a signal received from programmable processor 17 via line 140 and to cellar 1; Segment counter 12
9 sends the signal "0" to the decoder 131 via the line 141.
and sends the received 5SAR-0 address signal to a decoding circuit to produce an AND circuit enable signal on line 132. Ceramen 1~・Counter 129 is 5SA
When incremented by the carry signal of R-0, the signal “1”
is supplied to decoder 131 via line 142.

By adding one to the received 5SAR address, decoder 131 can remove the AND circuit enable signal on line 132 and provide a new AND circuit enable signal on line 133. This signal is 5S
AND circuits 117 and 12 related to AR-1 are enabled.

The address increment signal on line 115 is incremented by 5SAR-1 by AND circuit 117 and the address signal is then provided to cache 15 via AND circuit 121. Similarly, 5SAR-1 sends its carry signal to line 1
27 to the OR circuit 125 to increment the count of the segment counter 129, and the signal ``2J'' is provided to the decoder 131 via line 143, thereby causing the decoder], 31 to 2 and the AND circuit enable signal is on line 134.
to AND circuits 118 and 122 associated with 5SAR-2. 5SAR-2 receives the address increment signal and provides a cache data storage location signal to the cache 15, so that the third data storage space is addressed in subsequent operations.

Counting by segment counter 129 is not limited to segments as large as two. By providing a segment size register, segment counter 129 can count segments of arbitrary size or segments of variable size; however, for simplicity, segments of size 2 are preferred. is desirable.

As shown by the abbreviation 147 in FIG.
It is necessary to recognize that A, R30 may be provided. In that case, any three of the more storage address registers may be cached according to the present invention.
It is sometimes used to order the operations of 5. Therefore, as shown at ellipsis 148, an equally large number of AN
There is a D circuit enable line. In any case, P
The first storage address register to receive l is selected by programmable processor 17 in the usual manner. Programmable processor 17 then indicates which 5SAR received the P1 address which begins a sequence of concatenated addresses of sequentially accessed data storage space 28 in cache 15. Thus, a variable number of data storage spaces 28 can be used to receive data signals from address spaces of different sizes. For example, 2
When different DASDs 14 are connected to the storage director 12, two different sized data transfer units may be included (the data contents of the two DASD tracks have different numbers of stored data bits). first D
For the ASD 14, for example, three data storage spaces 28 may be connected and a larger, newer DASD, 14
For this, five data storage spaces 28 in cache 15 are used. In the latter case, the appropriate number of data storage spaces 28 are selected for data reception.
A table (not shown) is provided in storage director 12 that relates each DASD device address to the size of a data transfer unit. Some DASDs 14 include both tracks that can be addressed separately in 1/3 or 1/4 units and tracks that can be addressed only in 1/4 units.

In that case, the principles of the present invention are similarly applicable. Of course, segment counter 129 must be adjusted accordingly.

To deallocate data storage space 28, segment counter 129 provides over bus 145 the number of segments accessed in the current sequence of data transfer operations. In step 88 of FIG. 3, the value of segment counter 129 is determined.

FIG. 5 illustrates the operation of the directory 16. Directory 16 includes a plurality of registers, each of which has a unique association with only one of the data storage spaces 28 of cache 15. Access to directory 16 is based on DASD addresses received on bus 150 from usage unit 10 via programmable processor 17.

The hash circuit 151 analyzes and dissects the received DASD address into known hash classes. The entire address base of all DASDs 14 in a particular data storage system is divided into classes according to number of tracks, number of devices, and number of DASD cylinders (a cylinder is the entire record track at one radial area or address).

Each hash class has a single register in the SIT (distributed index table) 152. The output of hash circuit 151 addresses only one register in 5IT 152. 5ITI52 is the given SI
Stores the address of a directory register whose section 20 contains DASD addresses belonging to the hash class defined for the T register. This address is supplied as shown by arrow ]54 and is provided in directory 1
Select the designated register from 6. There is a hash pointer 155 within each directory register that points to the next directory register containing a DASD address within the same hash class. The last directory register in a chained list of such directory registers contains a special code indicating all O1s, ie, the end of the chain. Therefore, when scanning a directory register, programmable processor 17
activates hash circuit 151 to access the directory register from 5IT 152, and comparator circuit 157 compares the DASD address contained in section 20 of the first directory register with the DASD received on bus 150.
Compare with address. If both match, line 1
A cache hit has occurred as indicated by the signal above 58.

In the example, line 158 is the programmable processor 1
It is a logical bus in a program such as 36 in 7. If a mismatch is indicated by line 159, hash pointer 155 is read and the DASD address in the directory register pointed to by the hash pointer is compared in the same manner. This cycle is for both DAS
Does the D address match and indicate a cache hit?
or iterated until EOC (end of chain) occurs.

In the case of an EOC, a cache miss occurs, as shown by line 160.

Each of the directory registers that make up directory 16 includes a P1 pointer in section 22. As previously mentioned, the actual address of the directory register may relate linearly to the data storage area 28;
By keeping Pl in Section 2.2, there is no need to have a specific relationship between the structure of directory 16 and the configuration of cache 15.

LRU 47 also exists in directory 16.

Each of the registers in directory 16 is stored in cache 15.
section 167 containing a pointer LRUP that points to a directory register corresponding to the data storage space that was used immediately before the data storage space pointed to by the current register. Similarly, section 168 has a boink MPUP pointing to a directory register corresponding to more recently used data storage space. Sections 167 and 168 thus constitute a doubly linked list of registers, thereby indicating how long ago each data storage space was used. The most recently used data storage space is represented by a special code in the LRUP section 167, and the most recently used data storage space is represented by a special code in the MRUP section 168.

The control store 18 of the programmable processor 17 has so-called LRU anchors 165 and MRU anchors 166.

LRU anchor 165 contains the address of the most recently used directory register, and MRU anchor 166 points to the directory register corresponding to the most recently used data storage space. Section 1 of a doubly linked list
67, j68, and anchors 165 and 166 are well known, so their explanation will be omitted. Step 91 in Figure 3
When P2 or P3 is set to O, as shown in section 167.16 or 93, programmable processor 17 frees the corresponding segment of cache 15 (by setting F bit 171 to 1).
Update the double linked list of 8 and add L of the linked list.
Relink the released segment to the tail of the RU.

Additionally, when DASD 14 is not updated simultaneously with data updates in cache 15, LRU 47 includes a status indicator for the corresponding data storage space 28. M bit 170
indicates whether the data content of the corresponding data storage space 28 has been modified by the usage unit 10. When M bit 170 is 0, the corresponding data storage space can be deallocated. M bit 170 is 1
(data in cache 15 has been changed)
In this case, the data content of the corresponding data storage space 28 is D.
After being moved to the associated data storage area of the ASD 14, the corresponding data storage space can be reallocated. DASD
When cache 14 and cache 15 are updated at the same time, M bit 170 can be unused. F bit 171 indicates whether data storage space 28 is free (unopened) and available for allocation. The LRU traversal described in connection with steps 81 and 95 of FIG.
) is used to scan the register for F bit 171 equal to one. 0 if no free data storage space is found.
A scan of M bits 170 equal to is then performed. Of course, each directory register contains additional control information as indicated by ellipsis 175.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the outline and program flow of a data storage system according to the present invention, FIG. 2 is a block diagram in which the technology shown in FIG. 1 is applied to a peripheral data storage hierarchy, and FIG. FIG. 4 is a block diagram showing details of the storage circuit 56, and FIG. 5 is a block diagram showing details of the directory 16.

Claims (1)

[Claims] In a data storage unit having a large number of allocatable data storage spaces, in response to a write request, a plurality of available data storage spaces are allocated, and data is sequentially written to the plurality of data storage spaces. . A method for managing a data storage space, characterized in that a data storage space in which no data is written among the plurality of storage spaces is deallocated to enable reallocation in response to another write request.