JPS6249428A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the overlap of a two-phase clock by installing a clock generator for generating the multiphases clock of non-overlap from a fundamental clock at every function block and supplying the fundamental clock in accordance with the sequence of a data processing. CONSTITUTION:The sequence of a data processing in a signal processing LSI is executed in order of function blocks A-F, ad the wiring of a fundamental clock phiM is also performed in order of the function blocks A-F. With respect to the function blocks A-F, clock generators 10A-10F are installed, and each clock generator 10A-10F has a sufficient driving capacity against each function block A-F. Also, in said each function block A-F, a data is inputted by a two-phase block phi1, and a data is outputted by phi2 in the same way. In this way, the delay of the fundamental clock phiM in, for instance, the function block C and D is determined by a small wiring capacity and a small wiring resistance between the function block C and D, a delay between adjacent function blocks of the fundamental clock phiM is small, and the delay of two-phase clocks phi1, phi2 is also small.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor integrated circuits, and particularly to a clock generator used for signal processing.

[Conventional technology]

Traditionally, signal processing semiconductor integrated circuits (hereinafter referred to as
(referred to as a signal processing LSI), as shown in FIG. 4, a basic clock φ, a non-overlapping two-phase clock φ1 . One clock generator 10 that generates φ2 was installed in the chip. Note that A-F indicates each functional block.

FIG. 5 shows a clock generator 100 circuit, in which the clock generator 10 is connected to an inverter 11 and two No.
It is composed of 12 and 13 circuits.

FIG. 6 shows the basic clock φ supplied to the turn generator 10 and the output two-phase a clock φ1. A timing chart of φ is shown. 2-phase clock φ1. After one of the clocks φ falls, the other clock rises, so the two-phase clocks φ1 and φ2 do not overlap.

Next, the operation of the (fi processing LSI) shown in FIG. 4 will be explained.

One clock generator 10 installed with a signal processing LSIK receives a basic clock φ1 from the outside, and receives a non-overlapping two-phase clock φ1. φ, is generated. This two-phase clock φ1. φ is given to each of the functional blocks A to F that require a non-overlapping two-phase clock in the signal processing LSI.

[Problem that the invention seeks to solve]

The conventional semiconductor integrated circuit described above uses a two-phase clock φ1.
There are problems such as overramping due to the delay of φ2.

For example, as shown in FIG.
Two-phase clock φ1. φ2 does not have trap accents and does not overlap like the solid line waveform in Fig. 8 (observation point p).

q), However, in the functional block F with a large wiring resistance, the supplied two-phase clock φ8. φ
2, there is an accent like the waveform of the broken line (observation point r,
s), there were problems such as over-ramping.

This invention was made to solve the above-mentioned problems, and includes two-phase clocks φ1. An object of the present invention is to obtain a clock generation device that can prevent overramping of φ.

[Means for solving the interval i@ point]

The clock generator according to the present invention has a configuration in which a clock generator that generates a non-overlapping multiphase clock from a basic clock is installed in each functional block, and the basic clock is supplied according to the sequence of data processing. That is.

[Effect]

In this invention, by arranging a clock generator that generates a multiphase tarlock in each functional block and generating a non-overlapping multiphase tarlock from the basic clock within a narrow functional block, wiring capacitance and wiring resistance can be reduced. The rounding of the waveform of the two-phase p-c is reduced, and overlap is prevented.

〔Example〕

FIG. 1 shows an embodiment of the present invention.

In this invention, clock generators 10A to 1 are provided for each functional block ASF in one signal processing LSI.
The sequence of data processing within the above signal processing LSI, which is installed with 0F, is performed in the order of functional blocks A-F, and the wiring of the basic blocks φ and E & function blocks A-
They are applied in the order of F.

Clock generators 10A to 10F are installed for fiI functional blocks A to F in this semiconductor integrated circuit, and each of these clock generators IOA to IOF has sufficient driving ability for each of functional blocks A to FK.

It is also assumed that in each of the functional blocks A to F, data is taken in by a two-phase clock φ1, and data is outputted by a two-phase clock φ2.

Figure 2 shows the sequence and basics of data processing. This figure shows the wiring method for the clock φ4, in which the order of data processing and the order of supplying the basic clock φ4 are the same.

According to this configuration, two functional blocks next to each other,
For example, the delay of the basic clock φ in functional blocks C and D is determined by the small wiring capacitance and small wiring resistance between the functional blocks C and 0, and the delay between the basic clock φ and the mutual Deka 7° lock is Therefore, the two-phase clock φ4. The delay of φ2 is also small.

FIG. 3 shows the qtsq generator 10 for each of the functional blocks C1 and D. C, 10D two-phase clock φlc,
A timing chart of φ2c, φlD+φ2D is shown. In function blocks C and D, function block C
The functional block D receives the data output during the "H" period of the two-phase clock φ, C during the "H" period of the two-phase clock φ1D. Clockφ? 0 and φ1D can have a sufficient margin to prevent overlap, and there is no problem in receiving and passing data.

Further, since the drive capacity of the turn generators 10A to IOF in each functional block A to F is adjusted depending on the capacity of each block, the two-phase clock generators 10A to IOF have their drive capacities adjusted depending on the capacity of each block. φ does not overlap.

In the above embodiment, a non-overlapping two-phase clock generator was described, but if a non-overlapping clock is required, a multi-phase clock generator with any number of phases may be used, and the same effects as in the above embodiment can be obtained. play.

〔Effect of the invention〕

As explained above, this invention requires valley +! I installed a clock generator in each iWQ Glock and configured it to give the basic clock according to the data processing sequence.
This has the effect of providing stable clocks that do not overlap.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a semiconductor integrated circuit equipped with a clock generator according to an embodiment of the present invention, and FIG. 2 shows data processing and φ in the embodiment of FIG. 3 is a diagram showing the timing chart of two-phase clocks of adjacent functional blocks. FIG. 4 is a diagram showing the configuration of a signal processing LSI using the conventional clock generation method. Figure 5 is a circuit diagram of a general clock generator, Figure 6 is a timing diagram of the basic clock input to the clock generator and the obtained non-overlapping two-phase clock, and Figures 7 and 8 are diagrams. FIG. 4 is an equivalent circuit and waveform diagram for explaining the operation of the conventional example shown in FIG. 4; In the figure, A to F are +A function blocks 10A to 10F.
Beam ptsukjieneta, φM is basically beam ptsuk, φ4.
φ2 is a two-phase p-c. Note that the same reference numerals in each figure indicate 1nJ- or equivalent parts. Agent Masuo Oiwa (2 others) Figure 1 10A-10F: 9゜, 2.゜, -2φM:, Basic clock ψ1.φ2: 2a R Otsuk Figure 2 Figure 3 Φ20 Figure 4 ψ− Figure 5 Figure 6 Figure 7 Figure 8

Claims (1)

[Claims] In a signal processing semiconductor integrated circuit that processes data using a plurality of sequentially arranged functional blocks, a clock generator that receives a basic clock and outputs a non-overlapping multiphase clock is installed in each of the functional blocks; A semiconductor integrated circuit characterized in that a basic clock is supplied to the functional blocks in the order of a data processing sequence.