JPS6249350U - - Google Patents
Info
- Publication number
- JPS6249350U JPS6249350U JP14010185U JP14010185U JPS6249350U JP S6249350 U JPS6249350 U JP S6249350U JP 14010185 U JP14010185 U JP 14010185U JP 14010185 U JP14010185 U JP 14010185U JP S6249350 U JPS6249350 U JP S6249350U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- terminals
- pair
- common line
- pulse transformer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 1
Landscapes
- Bidirectional Digital Transmission (AREA)
- Dc Digital Transmission (AREA)
Description
第1図は本考案装置の一例を示す接続図、第2
図は第1図装置において用いられる入力用クロツ
クと出力用クロツクの波形図、第3図及び第4図
は従来の入力回路と出力回路の接続図である。
PT…パルストランス、n1…一次コイル、n
2,n3…二次コイル、C1,C2…コンデンサ
、D1,D2…ダイオード、Q1…トランジスタ
、11,12…端子。
Fig. 1 is a connection diagram showing an example of the device of the present invention;
1 is a waveform diagram of an input clock and an output clock used in the apparatus shown in FIG. 1, and FIGS. 3 and 4 are connection diagrams of conventional input and output circuits. PT...Pulse transformer, n 1 ...Primary coil, n
2 , n3 ... Secondary coil, C1 , C2 ... Capacitor, D1 , D2 ... Diode, Q1 ... Transistor, 11, 12... Terminal.
Claims (1)
イルとを有したパルストランスと、このパルスト
ランスの一次側に設けられ当該パルストランスを
デユテイレシオが小さい入力用クロツクと、デユ
テイレシオの大きい出力用クロツクによつてドラ
イブする回路手段と、前記パルストランスのセン
タタツプに接続される共通ラインと、この共通ラ
インを基準にして一方の二次コイルに生ずる信号
を整流して得られた電圧によりオン、オフするエ
ミツタが前記共通ラインに接続されたオープンコ
レクタ形式のトランジスタと、このトランジスタ
のエミツタ・コレクタにそれぞれ接続された一対
の端子と、前記共通ラインを基準にして他方の二
次コイルに生ずる信号を整流、平滑して前記一対
の端子の一方に与える回路とを備え、 入力回路モードにおいて前記パルストランスを
入力用クロツクによつてドライブし前記一対の端
子に与えられるステータス信号を一次側コイルの
一端で読み込み、 出力回路モードにおいて前記パルストランスを
出力用クロツクによつてドライブし前記一次コイ
ルに与えられるステータス信号を前記一対の端子
から得るようにした信号絶縁装置。[Claims for Utility Model Registration] A pulse transformer having a primary coil and a secondary coil with a center tap; circuit means driven by a large output clock, a common line connected to the center tap of the pulse transformer, and a voltage obtained by rectifying the signal generated in one of the secondary coils with this common line as a reference. an open collector transistor whose emitter is connected to the common line, a pair of terminals each connected to the emitter and collector of this transistor, and the other secondary coil with the common line as a reference. and a circuit that rectifies and smoothes the generated signal and applies it to one of the pair of terminals, and in an input circuit mode, the pulse transformer is driven by an input clock and the status signal applied to the pair of terminals is sent to the primary coil. The signal isolating device reads the signal at one end of the primary coil, drives the pulse transformer by an output clock in an output circuit mode, and obtains a status signal to be applied to the primary coil from the pair of terminals.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14010185U JPH0419868Y2 (en) | 1985-09-13 | 1985-09-13 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14010185U JPH0419868Y2 (en) | 1985-09-13 | 1985-09-13 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6249350U true JPS6249350U (en) | 1987-03-26 |
JPH0419868Y2 JPH0419868Y2 (en) | 1992-05-07 |
Family
ID=31046630
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14010185U Expired JPH0419868Y2 (en) | 1985-09-13 | 1985-09-13 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0419868Y2 (en) |
-
1985
- 1985-09-13 JP JP14010185U patent/JPH0419868Y2/ja not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPH0419868Y2 (en) | 1992-05-07 |
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