JPS6253829U - - Google Patents
Info
- Publication number
- JPS6253829U JPS6253829U JP14648685U JP14648685U JPS6253829U JP S6253829 U JPS6253829 U JP S6253829U JP 14648685 U JP14648685 U JP 14648685U JP 14648685 U JP14648685 U JP 14648685U JP S6253829 U JPS6253829 U JP S6253829U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- output
- voltage
- input
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
Landscapes
- Electronic Switches (AREA)
- Bidirectional Digital Transmission (AREA)
- Dc Digital Transmission (AREA)
Description
第１図は本考案に係る装置の一例を示す接続図
、第２図は従来のステータス信号入力回路の接続
図、第３図は従来のステータス信号出力回路の接
続図である。
ＰＴ……電源トランス、Ｄ１……整流ダイオー
ド、Ｃ１……平滑コンデンサ、ＰＣ１……出力用
カプラー、Ｑ１……出力トランジスタ、１１，１
２……端子、Ｑ２……入力トランジスタ、ＰＣ２
……入力用カプラー。
FIG. 1 is a connection diagram showing an example of a device according to the present invention, FIG. 2 is a connection diagram of a conventional status signal input circuit, and FIG. 3 is a connection diagram of a conventional status signal output circuit. PT...power transformer, D1...rectifier diode, C1...smoothing capacitor, PC1...output coupler, Q1...output transistor, 11,1
2...terminal, Q2...input transistor, PC2
...Input coupler.
Claims (1)
と、この電源トランスを介して得られた交流信号
を整流平滑し直流電圧を得る回路と、出力端に前
記直流電圧が印加され入力端に印加された信号に
対応しかつ当該信号に対して絶縁されたステータ
ス信号を出力する出力用カプラーと、この出力用
カプラーからの信号によつてオンオフするオープ
ンコレクタ形式の出力トランジスタと、この出力
トランジスタのコレクタ、エミツタにそれぞれ接
続された一対の端子と、前記直流電圧が供給され
て動作し前記一対の端子に印加されたステータス
信号によつてオンオフする入力トランジスタと、
入力端に前記入力トランジスタからの信号が印加
され出力端にこの信号に対応しかつ当該信号に対
して絶縁されたステータス信号を出力する入力用
カプラーとを備えた信号絶縁装置。 A power transformer driven by a clock, a circuit that rectifies and smoothes the AC signal obtained through the power transformer to obtain a DC voltage, and a circuit that applies the DC voltage to the output terminal and converts the signal applied to the input terminal into a DC voltage. An output coupler that outputs a status signal that corresponds to and is insulated from the signal, an open collector output transistor that is turned on and off by the signal from this output coupler, and a collector and an emitter of this output transistor, respectively. a pair of connected terminals, an input transistor that operates when supplied with the DC voltage and is turned on and off by a status signal applied to the pair of terminals;
A signal isolating device comprising: an input coupler having an input end to which a signal from the input transistor is applied and an output end thereof outputting a status signal corresponding to the signal and insulated from the signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14648685U JPS6253829U (en) | 1985-09-25 | 1985-09-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14648685U JPS6253829U (en) | 1985-09-25 | 1985-09-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6253829U true JPS6253829U (en) | 1987-04-03 |
Family
ID=31058996
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14648685U Pending JPS6253829U (en) | 1985-09-25 | 1985-09-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6253829U (en) |
-
1985
- 1985-09-25 JP JP14648685U patent/JPS6253829U/ja active Pending