JPS6248427B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image display system for an image data output end display monitor used in a facsimile machine, a scanner machine for creating newspaper pages, and the like.

Scanner equipment for creating newspaper pages can scan black and white image originals such as line drawings, halftone photographs, continuous tone photographs, and advertisements.
According to the parameter instructions, the image data is read, enlarged, and
This is an image data input device that performs various processes such as reduction, edge emphasis, gradation correction, halftone dot formation, and trimming, converts it into a binary dot image signal sequence, and inputs it to a newspaper editing electronic computer system. The image signal read by this scanner device can be displayed as a black and white binary dot image on a high-resolution cathode ray tube.

However, considering that the size of the document read by a scanner device is the size of one newspaper page, the length in the scanning direction is approximately 400 mm, which is calculated by the scanning line density of 454 LPI with the laser beam normally used.
When scanning with (LINE/INCH), approximately
The number of pixels will be 7000 or more. Furthermore, when reading at a high scanning line density, the number of pixels increases to more than 10,000 per scanning line. In addition, in the case of enlargement processing, the number of pixels will be a multiple of that number.

However, currently available high-resolution monitors have the ability to display at most 1200 pixels per horizontal scanning line, making it impossible to display all of the above pixels simultaneously on the monitor. It is. Therefore, in order to compensate for the above-mentioned points, special measures must be taken in the display method.

Traditionally, such a display method has been used to display pixel rows from the start of reading on a display monitor in order, but with this method, a part of the image data is divided on the monitor. Since the images are displayed one after another, it is difficult to check the correctness of the horizontal and vertical alignment of the read document, the positional accuracy of the document reading range, etc.

The present invention relates to a method for displaying image data, and the present invention provides an image data display system that simultaneously displays an arbitrary number of pixels at both ends of the first pixel column and the last pixel column per input scanning line, divided into one horizontal scanning period on a display monitor. The number of pixels that can be displayed is divided into the first pixel column and the last pixel column, each of which is half the number of horizontal scan lines that can be displayed on the display monitor. In other words, this method displays the image data read by the scanner device on both ends simultaneously on a monitor, thereby improving the positional accuracy of the starting point of the document, the positional accuracy of the end point of the document, and the horizontal and vertical orientation of the document. It is extremely effective because it can be used not only to check the positional accuracy at the time, but also to judge the quality of signal processing (particularly moiré circuit processing).

Embodiments of the present invention will be described in detail below with reference to the drawings.

Figure 1 is a configuration diagram of the monitor system.
2 is a scanner device, 2 is a scanning buffer memory circuit section, 3 is a monitor frame memory circuit section, and 4 is a display monitor including a monitor control section. First, the image signal read by the scanner device 1 and subjected to various processing is transmitted through the image signal data line 5.
The data is taken into the scanning buffer memory circuit section 2.
The control line 6 is composed of a scanning synchronizing signal output from the scanner device 1, an image signal clock, a signal line for requesting writing to the scanning buffer memory circuit section 2, and the like. The image signal taken into the scanning buffer memory circuit section 2 is taken into the monitor frame memory circuit section 3 via the data line 8 in accordance with a read request from the frame memory circuit section 3 through the control line 7 . The display monitor 4 and the frame memory circuit section 3 refresh and display the data on the screen via the data line 10 and the control line 9.
The display method of the present invention is a method in which image signals are written into and read out from the scanning buffer memory circuit section 2.

Since the input image signal processing according to the present invention is performed for each scanning line, the input image signal and the image signal clock,
The relationship between this and the scanning synchronization signal is illustrated in FIG. 2. In the figure, numeral 13 is a scanning synchronization signal, and one scanning line extends from one synchronization signal to the next synchronization signal. 1
1 is a picture signal clock, 12 is a picture signal, and one picture signal clock corresponds to one pixel. Reference numeral 14 denotes a read document, and the correspondence between pixels on the document and an image signal clock is illustrated.

Now, if the display function of the display monitor is to display within a range of 1024 pixels in the horizontal scanning direction using a scrolling method, the third
As shown in the figure, the image signal from the left end of the number of input image signals (m) is displayed for 512 pixels from the left end of the monitor, and the image signal from the right end of the number of input image signals (m) is displayed for 512 pixels from the upper right end of the monitor. . In this case (m/n)
If the number of pixels is less than 1024 pixels, the entire image will be displayed on the top left edge of the monitor. However, n represents the sampling state of the image signal; for example, if n=2, it represents that every other image signal is sampled. In this embodiment, the case where n=1 will be described below.

FIG. 4 is a block circuit diagram of an embodiment of the present invention, in which the scanning buffer memory circuit section described in FIG. 1 is constructed with a shift register or the like.
In the figure, 15 and 16 are shift register memories each having a 512-bit configuration, and 19 and 20 are down counters each having a 9-bit configuration.They manage the address of the image signal, and at the same time, their outputs are used to output the logic level of each of the flip-flop circuits 17 and 18. It works to change the shift registers 15 and 16 and down counters 19 and 20 connected to the multiplexer 25, respectively. 2
Reference numerals 1 to 23 denote gate circuit sections, 21 detects a level change in the scanning synchronization signal and functions to finish capturing the image signal, and the gate circuit 22 controls the flip-flop circuit sections 17 and 18 by the output of the multiplexer 25. At the same time, the down counters 19 and 20 are loaded with preset binary values. Further, the gate circuit 23 is a circuit section for adding together the first pixel and the last pixel of the output pixel sequence and leading the sum to a frame memory (not shown) via the signal line 32. Reference numeral 24 denotes a decoder circuit section for inputting a binary display value of 512 to the down counters 19 and 20, which may be composed of a switch or the like. 25 is a multiplexer circuit section, and depending on the state of the external signal line and the state of the flip-flop output, which will be described later,
This is a circuit section that selects and connects the shift registers 15, 16 and down counters 19, 20 to be connected, and switches and performs both writing and reading operations of image signals.

An input image signal, an image signal clock, and a scanning synchronization signal are applied to the signal lines 26, 27, and 28, respectively.
These are input from a scanner device (not shown). Further, the signal line 29 is connected to an external clock for driving the shift register, the signal line 30 is connected to a signal indicating either the writing state or the reading state, and the signal line 31 is connected to a signal for loading the preset value of the counter. It is assumed that these signals are output from a timing control circuit (not shown) that controls the timing of the scan buffer memory circuit section and the frame memory.

The operation will be explained below.

First, in an initial state indicating both-end display operation (for example, an external switch attached to the control circuit unit may be used), the decoder circuit 2 is
Counter 1 down the binary display value 512 from 4
At the same time as loading the flip-flops 9 and 20, the flip-flops 17 and 18 are set to the initial state (output logic level "L").
Make it. Now, if the signal line 30 is at the logic level "H" indicating the write state, the shift register 15
16 and the down counter 19 or 20 are connected so as to be driven by the input image signal clock on the signal line 27, and at the same time select the counter or shift register connected thereto. This means that the number of input image signal clocks is 512 or less, between 512 and 1024,
This is because the timing of capturing the image signal needs to be different for 1024 or more.

The input image signal clock applied to the signal line 27 is
512 and below, since the outputs of the flip-flops 17 and 18 are at the logic level "L", the multiplexer 25 transfers the image signal clock to the shift register 15 and the down counter 19.
and connect the signal line 26 only to the shift register 15.
Capture the image signal through. At this time, since the input image signal clock is less than 512, the down counter 19 does not output a borrow signal, and the output logic level of the flip-flop 17 remains at "L". When the gate circuit 21 is closed by a level state change representing the end of the scan synchronization signal on the signal line 28, the multiplexer 25 switches the clock to the external clock for driving the shift register on the signal line 29, and the counter 19 is switched to the preset 2. It is a decimal display.
From 512, the remaining number of clocks of the written image signal clock is idle-fed, and the clock is transferred to the shift register 15.
Shift the image signal to the output side. At this time, since the down counter 19 counts all 512 clocks, a borrow signal is output from its output, so the logic output level of the flip-flop 17 becomes "H", and the multiplexer 25 outputs a borrow signal from the output of the down counter 19. At the same time, it works to shift the shift register 16 by 512 times.
Similarly, the down counter 20 outputs a borrow signal, so the output of the flip-flop 18 becomes a logic level "H". This is the end of writing.

To read the image signal, when the signal line 30 goes to the logic level "L" indicating reading by the output from the timing control circuit section (not shown), the multiplexer 25 becomes the initial state and at the same time the gate circuit 22 starts reading the image signal. , the flip-flops 17 and 18 are reset to the logic level "L" state, and the binary display value 512 from the decoder 24 is loaded again. Drive the shift registers 15 and 16 by the number,
An output image signal can be obtained on the signal line 32.

Similarly, when the number of input image signal clocks is 512 or more and 1024 or less, the image signals for the first 512 clocks are taken into the shift register 15, and the remaining 512
After that, up to 1024 image signals are transferred to the shift register 16.
However, when a scanning synchronization signal is input to the signal line 28, the drive clock is sent to the down counter 20 by the external clock on the signal line 29, from the preset image signal clock number of 512 to the remaining clock number. Then, the image signal of the shift register 16 is shifted to the output side. At this time, a borrow signal is similarly outputted from the down counter 20, and the output of the flip-flop 18 goes to level "H", thereby completing the write operation.

Image signals are read using the signal line 29 in the same way as above.
Shift register 1 is controlled by 1024 external clocks.
Image signal output is obtained from 5 and 16.

Even when the number of input image signal clocks is 1024 or more, as described above, the image signals for the first 512 clocks are taken into the shift register 15, and the remaining image signals after 512 are sent to the shift register 16, whose contents are updated. While doing so, the data is captured until a scanning synchronization signal arrives on the signal line 28. That is, the output of the flip-flop 18 becomes a logic level "H" when the first 512 image signals are taken in, but since the multiplexer 25 is always connected to the down counter 20, the shift register 16 remains unchanged until the scanning synchronization signal is input. Continue writing image signals to. Therefore, when the gate circuit 21 is closed by the scan synchronization signal, the write state ends, and the 1024 external clocks 29 drive the shift registers 15, 16 and the down counters 19, 20, and continue from these. to obtain the image signal output. This embodiment has a feature that the circuit configuration is simple, but in response to requests for fast writing and reading, as in the previous embodiment,
A shift register with a multi-bit configuration has a slow response and limited speed.

FIG. 5 shows a first embodiment as another embodiment of the present invention.
As the scanning buffer memory circuit section explained in the figure,
A block circuit diagram of an example configured with a normal random access memory is shown.

In the figure, an input image signal, an image signal clock, and a scanning synchronization signal are applied to signal lines 40, 41, and 42, respectively, and these signals are output from the scanner device as explained in FIG. 43
is a 1-scan line buffer memory used in this embodiment, which in this case is a random access memory with a 1024×1 bit configuration. Numeral 44 is a 10-bit counter that manages the address of the scanning line buffer memory and also connects the address line 46 to the latch circuit 45. 47 is a data selector which functions to load the preset address value from the decoder circuit 50 or the address value from the latch circuit 45 into the counter 44 depending on the output state of the gate circuit 48. . Reference numeral 49 denotes a gate circuit which acts to word the output address value from the decoder circuit 50, according to the output state of the counter 44. 52
1 is a timing control circuit which, by writing to and reading from the 1-scan line buffer memory 43, switches between the image signal clock and the read clock, controls the frame memory circuit section (not shown), and controls the gate circuits 48 and 49. It is something. 53
65 represent signal lines or control lines, the description of which will be given later.

Now, as a representation of the double-end display function, when a signal (for example, logic level "H") from a switch attached to an external panel of the monitor (not shown) is applied to the gate circuit 49 through the signal line 57, the gate circuit 49 is activated. At the same time as opening, the counter 44 is brought to its initial state by the signal line 60. here,
When the scan synchronization signal of the scan line 42 is input to the timing control circuit section 52, the period between one scan synchronization signal and the next scan synchronization signal is used as a write state signal, and a write signal (for example, logic level "H") is sent to the signal lines 54, 56, 63. ”), and furthermore, the gate circuit 49
from the data selector 4 through the signal line 65.
Each of the 7 bit switches is connected to enable the 512 value in binary representation, which is the signal from the decoder circuit 50. Therefore, writing of the image signal is performed as follows.

First, when the number of input image signal clocks is 1024 or less, the image signal is directly passed through the signal line 62,
At the same time that the address lines 46 output from the counter 44 are sequentially written into the 1-line scanning buffer memory 43, the address lines 46 are written into the 1-line scanning buffer memory 43.
It operates by selecting the picture signal address code. When writing to the memory 43 is completed, the final address at that time is stored through the latch circuit 45 by the scan synchronization signal on the signal line 42 and appears on the address line.

On the other hand, when the number of input image signal clocks exceeds 1024, the number of clocks 1024, 1536, 2048, etc.
1024+512×n (however, n=0, 1, 2, 3...
...), a synchronizing pulse is output from the signal lines 58, 59, and the output line 61 of the gate circuit 49 operates to load the 512 value in binary representation as the preset address value of the counter 44. ,
Address 512 of 1-line scanning buffer memory 43
Thereafter, the memory contents up to 1023 are updated every clock count. When the writing to the memory is completed, the final address at that time is similarly transferred to the latch circuit 45 by the scan synchronization signal on the signal line 42.
remembered through.

The timing of this writing is shown in the timing diagram of FIG.
1, the relationship between the image signal 72 and the write signal 73 is shown. In the figure, 74 and 75 indicate vertical and horizontal synchronization signals.

To read the image signal, a signal representing the reading state (for example, shown in FIG. 6 76) is outputted from the timing control circuit 52 to the signal lines 51 and 55, and the counter 44 is set to the initial state by the signal line 60 from the gate circuit 49. At the same time, the gate circuit 48
A second signal line 63 accesses the buffer memory 43 in a read state. Therefore, 512 image signals from the initial addresses 0 to 511 are sequentially read out by the read clock (indicated by 77 in FIG. 6) on the signal line 53 output from the timing generation control circuit 52. However, the image signals after the image signal clock address 512 are set to the preset address of the counter 44 by the gate circuit 49 so that the signal line 65 is activated by each bit switch of the data selector 47, and the address line 64 from the latch circuit 45 is enabled. Since the values are connected, the addresses 1024 and 1024 of the buffer memory 43 are sequentially transferred from the address next to the last clock address stored upon completion of writing.
It reads the image signal up to the th clock address. At this time, as mentioned above, the counter 44
is the 1024th address clock pulse on signal line 5.
Since the synchronization pulse is output to the signal line 6, the signal line 6 is output again.
5, the 512 value from the decoder circuit 50 is loaded into the counter 44 through the data selector 47, so the reading clock reads from the 512th image signal clock address to the final clock address, and in addition to the above, the 512 value from the decoder circuit 50 is loaded into the counter 44. The address image signals (remaining image signals for a total of 512) are read out. The read image signal is sent to the signal line 66
The signal is input to the frame memory shown in FIG.

Now, as an example, the number of input image signal clocks is 3855.
To explain the case, the first image signal clock 1~
The image signals up to the 512th are written as they are to the 1-line buffer memory 43, and the image signals become 0.
Stored at memory address ~511. This is illustrated as a memory address arrangement in FIG. Next, for the last 512 image signals, set the start address of the image signal clock count to 512, 1024, 1536, etc.
The 512 image signals from image signal clocks 3344 to 3855 are stored from buffer memory address 512.
Written by 1023. The image signal clock address values corresponding to the 3344th and 3855th at that time correspond to 784 and 783, as shown in FIG. That is, the image signals from the 3344th image signal clock to the 3583rd image signal clock are written to memory addresses 784 to 1023, and the image signals from the 3584th image signal clock
Image signals up to 3855th are from memory address 512
It will be written by 783. When reading image signals, the first 512 image signals can be read as is, but for the remaining contents from 512 to 1023 memory addresses, the address next to the write final address 783, which corresponds to image signal clock 3855, In other words, the address corresponding to the image signal clock 3344
Reads 240 image signals from 784 to 1023 in order. Next, the starting address of the read counter is set to 512 again as described above, so the memory address corresponding to the final clock 3855 is now read.
A total of 512 image signals of 272 up to 783 are read out.

As mentioned above, the 1-line scanning buffer memory 43
The image signal 66 read out is displayed on the monitor screen through the frame memory and monitor control circuit shown in FIG.

As is well known, the timing of writing and reading is performed using the return line time of the monitor.In this embodiment, the horizontal synchronization signal is 44μsec, so the total time for writing is 750μsec for 16 horizontal synchronization signals. is used to write to and read from frame memory. In this case, the vertical retrace period of 1 msec or more is sufficient. These relationships are illustrated by the relationships among vertical synchronization signal 73, horizontal synchronization signal 74, read signal 76, and read clock 77 in FIG.

In this embodiment, since a random access memory is used as the scanning line buffer memory, the response speed is fast and the writing and reading speeds can be improved, so that even if the reading speed of the image signal becomes faster, it can be followed. This leads to improved functionality of scanner equipment.

FIG. 8 shows an example of an image display according to the present invention, in which a dotted line portion of a read document is displayed on a monitor using a both-end display method.

Note that display methods other than those according to the present invention, for example, a method in which one scanning line data is continuously fetched from an arbitrary position into a line buffer and displayed, so-called
It is also possible to combine the window display method and the both-end display method according to the present invention, thereby further increasing the utility value.

As explained above, the present invention writes the number of pixels at both ends of the first pixel column and the last pixel column of an input scanning image signal to a scanning buffer memory, and sequentially reads them out and monitors the image as an image output terminal display of a scanner reading device. It is characterized by being displayed simultaneously on the top of the screen, and can be used for purposes other than determining the quality of image data, such as horizontal and vertical alignment of an input read document, and its utility value is extremely high.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of a monitor system implementing the image display method of the present invention, and FIG.
3 is a diagram illustrating the relationship between input image signal data in the present invention, FIG. 3 is a diagram explaining the both-end display function of the present invention, FIG. 4 is a block diagram of a both-end display circuit using a shift register implementing the present invention, and FIG. FIG. 5 is a block diagram of a both-end display circuit using a random access memory that implements the present invention, FIG. 6 is a timing diagram showing the relationship between input image signal data, and FIG. 7 is a memory address layout diagram showing a both-end display function using a random access memory. , FIG. 8 is a diagram showing an example of a display monitor in the system of the present invention. DESCRIPTION OF SYMBOLS 1...Scanner device, 2...Scanning buffer memory circuit section, 3...Frame memory circuit section, 4...
...Display monitor, 15, 16...Shift register,
17, 18...flip flop, 19, 20...
...Down counter, 21-23...Gate circuit,
24... Decoder circuit, 25... Multiplexer, 43... 1 line buffer memory, 44...
Counter, 45... Latch circuit, 47... Data selector, 48, 49... Gate circuit, 50...
decoder circuit.

Claims (1)

[Claims] 1. In an image display method in which an input image signal read by a scanner device or the like is stored in a scanning buffer memory circuit section, and an image signal from the scanning buffer memory circuit section is displayed on a display monitor via a frame memory circuit section, Extracting an arbitrary number of the first pixel column and the last pixel column from one scanning signal of the input image signal, storing them in a scanning buffer memory circuit section, and displaying the first pixel column and the last pixel column. An image display method characterized by simultaneously displaying images on divided areas on one horizontal scanning line of a computer monitor.