JPS61169890A - Image processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an image processing apparatus that reduces omissions of information to be displayed and displays the information in a reduced size.

BACKGROUND ART When displaying data with a large amount of information such as an image on a display device that can display a small amount of information, the data is reduced and displayed by sampling the original data at the same size. Conventionally, this sampling position is generally fixed to obtain image data to be displayed in a reduced size. In addition, in order to reduce the loss of information due to sampling, methods have been proposed to obtain reduced data sampled by calculations based on the state of the original data rather than by unique sampling (for example, , ``Refined image signal processing for OA'' (1981.10.20) 8 Nikkan Kogyo Shimbunsha, p. 32).

Problems to be Solved by the Invention The conventional method of fixing the sampling position during reduction has a simple configuration, but on the other hand, information is lost due to reduced display, and especially when displaying a binary image, information is lost due to reduced display. It was difficult to decipher the images. - As an example, FIG. 4 shows a case where the data to be displayed at the same size as shown in FIG. 3 is reduced to H in both the vertical and horizontal directions. Figure 4 a, b,
Of the four pixels surrounded by dotted lines in Figure 3, a and d are the top left pixel, b is the entire top right pixel, C is the bottom left pixel, and d is the bottom right pixel. This is a case where each is fixed as a sampling position. As is clear from the example above, the reduced display causes information to be lost and becomes difficult to read.

Further, in the method of obtaining reduced data by calculating and sampling the original data, it is possible to reduce the amount of missing information, but there are problems in that the configuration becomes complicated and the processing speed decreases.

The present invention has been made in view of the above points, and an object of the present invention is to provide an image processing device that has a simple configuration, enables reduced/J% display with less loss of information, without causing a decrease in processing speed. It is an object.

Means for Solving the Problems In order to solve the above problems, the present invention provides means for changing the sampling position with respect to the original data for obtaining reduced data every n vertical scans of the display device. Data with different sampling positions is given to the display device for each vertical scan, and the data is displayed in a reduced size.

According to the above-mentioned structure of the present invention, by sequentially displaying pixels f:n corresponding to the extension sub-display of the original data every vertical scan, pseudo halftone display is performed, and information loss due to reduced display is prevented. .

Embodiment FIG. 1 is a block diagram showing an embodiment of a reduction display circuit of the present invention. In FIG. 1, 11 is a sampling circuit, 12 is an image memory, 13 is a parallel/serial conversion circuit (hereinafter referred to as P/S), 14 is a sampling position change circuit, 16 is a display device, 16 is sampling position change information, 17 18 is a vertical scanning number setting signal, and 18 is a vertical synchronization signal.

The operation of this embodiment configured as above will be described below. The sampling position change circuit 14 counts the vertical synchronization signals 18 and changes the sampling circuit every n vertical scans by the direct scan number setting signal -17. Sampling position change information 16 is given to 11. - As an example, consider a case where a non-interlaced display device is used and the sampling position is changed every vertical scan (frame) with n; 1. The sampling circuit 11 changes the sampling position every frame based on the sampling position change information 16, for example, as indicated by a, b, a, and d shown in FIG.
The signal is converted into a serial signal by P/813 and displayed on the display device 16.

By changing the sampling position in this manner, a display state as shown in FIG. 2 can be obtained.

In Figure 2, B has 4 pixels, C has 3 pixels, and D has 2 pixels.
If the pixel has the information shown in A in FIG. 3, E shows the case in which 4 pixels have no information shown in F in FIG. 3. The display state in Figure 2 is a pseudo-halftone display depending on the state of the pixels of the image data to be displayed at the same size, for example, the state of the four pixels inside the dotted line in Figure 3, and is reduced without missing information. Indicates the displayed status.

In this embodiment, the case where sampling is performed on data read from the image memory has been explained.
The image memory is composed of m memory elements that can be independently given addresses, performs replacement processing in m-bit image data and writes, and when reading m-bit image data,
The present invention is also effective for an image processing apparatus that obtains sampled and reduced image data by changing the address given to a memory element and supplies it to a display device.

Further, although the case where a non-interlaced display device is used as the display device has been described as an example, the present invention is effective even when an interlaced display device is used.
For example, if n = 2, the sampling position can be changed on a frame-by-frame basis as in the above embodiment.

Effects of the Invention As described above, according to the present invention, with an extremely simple circuit configuration, reduced image data that can be displayed without any loss of information without causing a decrease in processing speed even when reduced display is obtained. This is extremely useful in practical terms.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an image processing device according to an embodiment of the present invention, and Fig. 2 shows a reduced display state of the same, and shows a state reduced to H in the vertical and horizontal directions with the ring position fixed. This is a state diagram. 11... Sampling circuit, 12... Image memory, 13... Parallel/serial conversion circuit,
14... Sampling position change circuit, 15...
... Display device, 16 ... Sampling position change information, 17 ... Vertical scanning number setting signal, 18
...Vertical synchronization signal. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2

Claims (1)

[Claims] An image processing device that includes means for changing a sampling position of display data every n vertical scans, and generates reduced image data by sampling image data in a same-size display and provides it to a display device.